PCS1P2860A [ONSEMI]

Multi-Output Clock Synthesizer; 多路输出时钟合成器


型号：	PCS1P2860A
厂家：	ONSEMI
描述：	Multi-Output Clock Synthesizer 多路输出时钟合成器时钟
文件：	总6页 (文件大小：146K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCS1P2860A

Multi-Output Clock Synthesizer

Features

• Generates multiple clock outputs from an

Product Description

The PCS1P2860A is

a Precision multi-PLL based

frequency synthesizer. Six Clock outputs are generated

using an inexpensive 25MHz Crystal or external

reference clock. The outputs consist of 25MHz Refout,

127MHz and four 125MHz clocks. SHUTDOWNB signal

tri-states all the clocks when enabled. The device

operates from a Supply Voltage of 3.3V ± 5%V. The

device is available in a 16-pin TSSOP JEDEC package.

inexpensive 25MHz crystal or external reference

clock

• Frequency outputs:

o 25MHz Reference clock

o 125MHz

o 127MHz

• Zero ppm frequency synthesis error for all CLK

outputs

Application

• 3.3V ± 5%V Supply Voltage

• Low jitter design

PCS1P2860A is targeted for use in high-end multimedia,

communications and consumer applications.

• Packaged in 16-pin TSSOP

• Compatible with CY22393XC-MZ2

• Advanced CMOS process

Block Diagram

SHUTDOWNB

AVDD

VDD

125MHz

CLKIN / XIN

Crystal

PLL

Oscillator

XOUT

127MHz

25MHz

GND

JANUARY 2010 – Rev. 1

Publication Order Number:

PCS1P2860/D

PCS1P2860A

Pin Diagram

125MHz

SHUTDOWNB

VDD

AGND

XIN

AVDD

PCS1P2860A

XOUT

GND

125MHz

REFOUT

125MHz

127MHz

Pin Description

Pin #

Pin Name

Pin Type

Pin Description

125MHz

VDD

Output

Power

125MHz Clock Output.

Connect to +3.3V.

AGND

Connect to ground.

Crystal connection or external reference frequency input. It can be connected

to a 25MHz Fundamental mode crystal.

Connection to crystal. If using an external reference clock, this pin must be

left unconnected.

XIN

Input

XOUT

Output

REFOUT

125MHz

Output

25MHz Reference Clock output.

125MHz Clock Output.

125MHz

127MHz

125MHz

GND

Output

Power

125MHz Clock Output.

127MHz Clock Output.

125MHz Clock Output.

Connect to ground.

No connection.

AVDD

Power

Input

Connect to +3.3V.

No connection.

Output Enable bit. When this pin is made HIGH, all clocks are enabled.

SHUTDOWNB

Tri-states all clocks when this pin is LOW

Rev. 1 | Page 2 of 6 | www.onsemi.com

PCS1P2860A

Absolute Maximum Ratings

Symbol

Parameter

Rating

Unit

VDD

V_IN

T_STG

T_s

Power Supply Voltage relative to Ground

Input Voltage relative to Ground (Input Pins)

Storage temperature

-0.5 to +4.6

-0.5 to VDD+0.3

-65 to +150

260

°C

Max. Soldering Temperature (10 sec)

Junction Temperature

T_J

125

Static Discharge Voltage

T_DV

(As per JEDEC STD22- A114-B)

Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect

device reliability.

Operating Conditions

Parameter

Description

Min

3.135

Typ

Max

3.465

Unit

VDD / AVDD Operating Voltage

3.3

T_A

C_L

Operating Temperature (Ambient Temperature)

Load Capacitance

°C

C_IN

Input Capacitance

DC Electrical Characteristics

Symbol Parameter

VDD / AVDD Operating Voltage

Conditions

Min

3.135

2.2

Typ

Max

Units

3.3

3.465

VDD+0.3

1.0

Input High Voltage

Input Low Voltage

Input HIGH current

Input LOW current

Output High Voltage

Output Low Voltage

Output Leakage Current

GND-0.3

VIN = VDD

µA

VIN = GND

VDD = 3.135, IOH = -12mA

VDD = 3.135, IOL = 12mA

Three-state outputs

2.4

0.4

µA

CLKIN and SHUTDOWNB

Pins pulled low

Static Current

5.5

Dynamic Current

No Load, All Clocks on

OUT

Nominal output impedance

ꢀ

Rev. 1 | Page 3 of 6 | www.onsemi.com

PCS1P2860A

AC Electrical Characteristics

Symbol

Parameter

Min

Typ

Max Unit

CLKIN / XIN

Input Frequency

MHz

Pin 6

Pin 1,7,8,10

Pin 9

125

127

CLK OUT

Output Frequency

MHz

t_LH

Rising edge slew rate (Measured from 20% to 80%)

Falling edge slew rate (Measured from 80% to 20%)

Peak-to-peak Period Jitter @ VDD/2

Synthesis Error (Output Frequency)

1.1

1.3

1.7

V/nS

t_HL

T_PJ

300

ppm

t_D

Output Duty Cycle @ VDD/2

t_LOCK

PLL Lock Time from Power-Up

NOTE: 1. CL= 15pF for outputs < 100MHz; CL = 10pF for outputs > 100MHz;

Typical Crystal Specifications

Fundamental AT cut parallel resonant crystal

Nominal frequency

25MHz

Frequency tolerance

± 50 ppm or better at 25°C

-25°C to +85°C

-40°C to +85°C

18pF

Operating temperature range

Storage temperature

Load capacitance(C_P)

Shunt capacitance

7pF maximum

ESR

25 Ω

Note: Note: C_Lis Load Capacitance and Rx is used to prevent oscillations at overtone frequency of the Fundamental frequency.

Typical Crystal Interface Circuit

C_L

Crystal

C_L

C_L= 2*(C_P– C_S),

Where C_P= Load capacitance of crystal

C_S= Stray capacitance due to C_IN,PCB, Trace etc.

Rev. 1 | Page 4 of 6 | www.onsemi.com

PCS1P2860A

Package Information

16-lead Thin Shrunk Small Outline Package (4.40-MM Body)

PIN 1 ID

Seating Plane

Dimensions

Symbol

Inches

Millimeters

Min

Max

Min

Max

1.20

0.15

1.05

0.30

0.20

5.10

4.50

0.043

0.006

0.041

0.012

0.008

0.201

0.177

0.002

0.031

0.007

0.004

0.193

0.169

0.05

0.80

0.19

0.09

4.90

4.30

0.026 BSC

0.252 BSC

0.65 BSC

6.40 BSC

0.020

0°

0.030

8°

0.50

0°

0.75

8°

Rev. 1 | Page 5 of 6 | www.onsemi.com

PCS1P2860A

Ordering Information

Part Number

Marking

Package

Temperature

1P28

60A

PCS1P2860AG-16TR

16-Pin TSSOP, TAPE & REEL, Green

0°C to +70°C

A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb-free.

Licensed under US patent #5,488,627 and #5,631,920.

Note: This product utilizes US Patent #6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

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was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. U.S Patent Pending; Timing-Safe

and Active Bead are trademarks of PulseCore Semiconductor, a wholly owned subsidiary of ON Semiconductor. This literature is subject to all applicable

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