RFD14N05LSM [ONSEMI]
N 沟道逻辑电平功率 MOSFET 50V，14A，100mΩ;
| 型号： | RFD14N05LSM |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道逻辑电平功率 MOSFET 50V，14A，100mΩ 局域网 开关 脉冲 晶体管 |
| 文件： | 总10页 (文件大小：1043K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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RFD14N05L, RFD14N05LSM
Data Sheet
October 2013
Features
N-Channel Logic Level Power MOSFET
50 V, 14 A, 100 mΩ
• 14A, 50V
• r = 0.100Ω
These are N-channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. This performance is accomplished
through a special gate oxide design which provides full rated
conductance at gate bias in the 3V-5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.
DS(ON)
®
• Temperature Compensating PSPICE Model
• Can be Driven Directly from CMOS, NMOS, and
TTL Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
o
• 175 C Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA09870.
Ordering Information
Symbol
PART NUMBER
PACKAGE
TO-251AA
TO-252AA
BRAND
14N05L
D
RFD14N05L
RFD14N05LSM
14N05L
14N05L
G
RFD14N05LSM9A TO-252AA
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A.
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
GATE
DRAIN (FLANGE)
SOURCE
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM Rev. C0
RFD14N05L, RFD14N05LSM
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
RFD14N05L, RFD14N05LSM,
RFD14N05LSM9A
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
50
V
V
V
A
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
50
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
10
GS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
14
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Refer to Peak Current Curve
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Refer to UIS Curve
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
48
0.32
W
D
o
o
Derate above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
T
-55 to 175
C
J, STG
o
300
260
C
C
L
o
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T
= 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
= 250µA, V = 0V, Figure 13
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate Threshold Voltage
BV
I
50
1
-
-
-
DSS
D
GS
= V , I = 250µA, Figure12
V
V
V
V
V
-
2
1
V
GS(TH)
GS
DS
DS
GS
DS D
Zero Gate Voltage Drain Current
I
= 40V, V
= 40V, V
= 10V
= 0V
-
µA
µA
nA
Ω
DSS
GS
GS
o
= 0V, T = 150 C
-
-
50
100
0.100
60
-
C
Gate to Source Leakage Current
I
-
-
-
GSS
Drain to Source On Resistance (Note 2)
Turn-On Time
r
I
= 14A, V
= 5V, Figures 9, 11
-
DS(ON)
D
GS
t
V
R
R
= 25V, I = 7A,
-
-
ns
(ON)
DD
D
= 3.57Ω, V
= 5V,
L
GS
Turn-On Delay Time
Rise Time
t
-
13
24
42
16
-
ns
d(ON)
= 0.6Ω
GS
t
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
-
ns
d(OFF)
t
-
-
ns
f
Turn-Off Time
t
-
100
40
25
1.5
-
ns
(OFF)
Total Gate Charge
Q
V
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 40V, I = 14A,
-
-
nC
nC
nC
pF
pF
pF
g(TOT)
GS
GS
GS
DS
DD
D
R = 2.86Ω
Figures 20, 21
L
Gate Charge at 5V
Q
-
-
g(5)
Threshold Gate Charge
Input Capacitance
Q
-
-
g(TH)
C
= 25V, V
= 0V, f = 1MHz
GS
-
670
185
50
-
ISS
OSS
RSS
Figure 14
Output Capacitance
C
C
-
-
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
-
-
o
R
R
R
-
3.125
100
100
C/W
θJC
θJA
θJA
o
TO-251
-
-
C/W
o
TO-252
-
-
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
NOTES:
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.5
UNITS
V
V
I
I
= 14A
-
-
-
-
SD
SD
SD
t
= 14A, dI /dt = 100A/µs
SD
125
ns
rr
2. Pulse Test: Pulse Width ≤300ms, Duty Cycle ≤2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM Rev. C0
RFD14N05L, RFD14N05LSM
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
16
12
8
4
0
0
125
o
0
25
50
75
100
175
150
25
50
75
100
150
125
175
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
2
1
0.5
0.2
P
DM
0.1
0.1
0.05
t
1
t
2
0.02
0.01
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
x Z
x R
+ T
JC C
J
DM
JC
θ
θ
0.01
-5
-4
-3
-2
-1
10
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
200
o
= 25 C
T
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
C
o
T
= MAX. RATED
J
100
175 - T
150
C
I = I
25
100µs
10
1ms
10ms
OPERATION IN THIS
AREA MAY BE
V
= 5V
100ms
DC
GS
1
LIMITED BY r
V
= 10V
DS(ON)
GS
o
T
= 25 C
C
0.5
10
10
10
, DRAIN TO SOURCE VOLTAGE (V)
1
100
-5
-4
-3
-2
-1
0
1
10
10
10
10
10
10
V
t, PULSE WIDTH (s)
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM Rev. C0
RFD14N05L, RFD14N05LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
50
35
30
25
20
15
10
5
V
= 10V
GS
V
= 5V
GS
V
= 4.5V
GS
V
= 4V
o
GS
o
STARTING T = 25 C
J
PULSE DURATION = 80µs, T = 25 C
C
10
DUTY CYCLE = 0.5% MAX.
o
STARTING T = 150 C
J
V
= 3V
GS
If R = 0
t
= (L)(I )/(1.3*RATED BV
DSS
- V )
DD
AV
AS
V
= 2.5V
GS
If R ≠ 0
AV
t
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
-V ) +1]
DSS DD
1
0
0.01
0.1
1
10
1.5
0
3.0
4.5
6.0
7.5
t
, TIME IN AVALANCHE (ms)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7. SATURATION CHARACTERISTICS
35
250
200
150
o
-55 C
I
= 28A
I
= 7A
I = 14A
D
D
D
30
o
25 C
o
175 C
25
20
15
10
I
= 3.5A
100
50
D
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
5
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
V
= 15V
DD
0
0
1.5
3.0
4.5
6.0
7.5
2.5
3.0
3.5
4.0
4.5
5.0
V
, GATE TO SOURCE VOLTAGE (V)
V
GS
, GATE TO SOURCE VOLTAGE (V)
GS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
160
140
120
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
V
= 25V, I = 14A, R = 3.57Ω
t
DD
D
L
d(OFF)
V
= 10V, I = 14A
GS
D
2.0
100
80
1.5
1.0
0.5
0
t
r
t
f
60
40
t
d(ON)
20
0
20
30
40
50
0
10
-80
-40
0
40
80
120
160
200
o
R
, GATE TO SOURCE RESISTANCE (Ω)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM Rev. C0
RFD14N05L, RFD14N05LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0
1.5
2.0
1.5
1.0
0.5
0
V
= V , I = 250µA
DS
I
= 250µA
GS
D
D
1.0
0.5
0
-80
-80
-40
0
40
80
120
160
200
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
50
40
5
4
800
C
ISS
V
= BV
V
= BV
DD DSS
DD
DSS
600
V
= 0V, f = 1MHz
GS
30
20
3
2
C
C
C
= C
+ C
ISS
GS
= C
GD
RSS
OSS
GD
400
200
0
≈
C
+ C
DS
GD
OSS
0.75 BV
0.50 BV
0.25 BV
DSS
DSS
DSS
C
C
10
0
R
= 3.57Ω
1
0
L
I
= 0.4mA
G(REF)
V
= 5V
GS
RSS
I
I
G(REF)
G(REF)
0
5
10
15
20
25
t, TIME (µs)
20------------------------
80------------------------
I
I
G(ACT)
G(ACT)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260,
FIGURE 15. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM Rev. C0
RFD14N05L, RFD14N05LSM
Test Circuits and Waveforms (Continued)
t
t
ON
OFF
t
d(OFF)
t
d(ON)
V
DS
t
t
f
r
V
DS
90%
90%
R
L
V
GS
+
10%
10%
0
V
DD
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
V
DS
V
Q
R
DD
g(TOT)
L
V
DS
V
= 10V
GS
V
GS
Q
+
-
g(5)
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
G(REF)
Q
g(TH)
I
G(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM Rev. C0
RFD14N05L, RFD14N05LSM
PSPICE Electrical Model
.SUBCKT RFP14N05L 2 1 3 ;
rev 9/15/94
CA 12 8 1.464e-9
CB 15 14 1.64e-9
CIN 6 8 6.17e-10
DPLCAP
5
DRAIN
2
10
LDRAIN
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
RSCL1
DBREAK
RSCL2
51
+
5
51
ESCL
EBREAK 11 7 17 18 65.35
EDS 14 8 5 8 1
50
11
+
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
DBODY
6
8
RDRAIN
ESG
17
18
EBREAK
MOS2
16
+
VTO
+
EVTO
21
GATE
1
9
20
+
IT 8 17 1
6
18
8
MOS1
8
LGATE
RGATE
LDRAIN 2 5 1e-9
LGATE 1 9 5.68e-9
LSOURCE 3 7 5.35e-9
RIN
CIN
LSOURCE
RSOURCE
7
3
SOURCE
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
S1A
S2A
RBREAK
12
15
14
13
13
8
17
18
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 33.1e-3
RGATE 9 20 5.85
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
S1B
CA
S2B
13
RVTO
19
VBAT
CB
IT
14
+
+
6
8
5
8
EDS
EGS
+
RSOURCE 8 7 RDSMOD 14.3e-3
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.485
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))}
.MODEL DBDMOD D (IS = 2.23e-13 RS = 1.15e-2 TRS1 = 1.64e-3 TRS2 = 7.89e-6 CJO = 6.83e-10 TT = 3.68e-8)
.MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5)
.MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6)
.MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5)
.MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6)
.MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; authored by William J. Hepp and C. Frank Wheatley.
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM Rev. C0
RFD14N05L, RFD14N05LSM
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intended to be an exhaustive list of all such trademarks.
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tm
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PowerXS™
Programmable Active Droop™
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QS™
Quiet Series™
RapidConfigure™
™
®
TinyBoost
TinyBuck
®
®
Green FPS™ e-Series™
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TinyLogic
TINYOPTO™
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®
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®
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®
®
SPM
Fairchild
®
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SuperFET
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Fairchild Semiconductor
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®
®
UHC
®
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®
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OPTOPLANAR
FACT
FAST
®
®
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®
®
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Datasheet contains the design specifications for product development. Specifications
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Full Production
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Semiconductor. The datasheet is for reference information only.
Not In Production
Rev. I66
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM Rev. C0
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