RFD16N06LESM9A [ONSEMI]
N 沟道逻辑电平功率 MOSFET 60V，16A，47mΩ;
| 型号： | RFD16N06LESM9A |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道逻辑电平功率 MOSFET 60V，16A，47mΩ PC 开关 晶体管 |
| 文件： | 总9页 (文件大小：663K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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RFD16N06LESM
Data Sheet
October 2013
Features
N-Channel Logic Level Power MOSFET
60 V, 16 A, 47 mΩ
• 16A, 60V
These are N-Channel power MOSFETs manufactured
using a modern process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, relay drivers and emitter switches for bipolar
transistors. This performance is accomplished through a
special gate oxide design which provides full rated
conductance at gate bias in the 3V to 5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.
• r
= 0.047Ω
DS(ON)
®
• Temperature Compensating PSPICE Model
• Can be Driven Directly from CMOS, NMOS, TTL
Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA49027.
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
16N06LE
D
RFD16N06LESM9A TO-252AA
G
S
Packaging
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. C0
RFD16N06LESM
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
RFD16N06LESM
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
60
V
V
V
A
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
60
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
+10, -8
GS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
16
Refer to Peak Current Curve
Refer to UIS Curve
90
D
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.606
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 175
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V, Figure 11
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate Threshold Voltage
I
60
1
-
-
-
-
3
DSS
D
GS
= V , I = 250µA, Figure 10
V
V
V
V
V
V
GS(TH)
GS
DS
DS
GS
DS D
Zero Gate Voltage Drain Current
I
= 55V, V
= 50V, V
= 0V
-
1
µA
µA
µA
Ω
DSS
GSS
GS
GS
o
= 0V, T = 150 C
-
-
250
10
0.047
100
-
C
Gate to Source Leakage Current
I
= +10, -8V
= 5V
-
-
Drain to Source On Resistance (Note 2)
Turn-On Time
r
I
= 16A, V
D GS
-
-
DS(ON)
t
V
V
= 30V, I = 16A, R = 1.88Ω,
-
-
ns
ON
DD
GS
D
L
= 5V, R
= 5Ω
GS
Turn-On Delay Time
Rise Time
t
-
11
60
48
35
-
ns
d(ON)
Figures 16, 17
t
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
-
ns
d(OFF)
t
-
-
ns
f
Turn-Off Time
t
-
115
62
35
2.6
-
ns
OFF
Total Gate Charge
Q
V
V
V
V
= 0V to 10V
V
= 48V,
= 16A, R = 3Ω
-
51
29
1.8
1350
300
90
-
nC
nC
nC
pF
pF
pF
g(TOT)
GS
GS
GS
DS
DD
I
D
L
Gate Charge at 5V
Q
= 0V to 5V
= 0V to 1V
-
g(5)
Figures 18, 19
Threshold Gate Charge
Input Capacitance
Q
-
g(TH)
C
= 25V, V
= 0V,
GS
-
ISS
OSS
RSS
f = 1MHz
Figure 12
Output Capacitance
C
C
-
-
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
-
-
o
R
-
1.65
80
C/W
θJC
o
R
TO-252AA
-
-
C/W
θJA
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
NOTES:
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
V
I
I
= 16A
-
-
-
-
1.5
SD
SD
SD
t
= 16A, dI /dt = 100A/µs
SD
125
ns
rr
2. Pulse Test: Pulse Width ≤300µs, Duty Cycle ≤2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature.
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. C0
RFD16N06LESM
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
0
20
15
10
5
0
50
25
75
T , CASE TEMPERATURE ( C)
C
100
125
o
150
175
125
o
0
25
50
75
100
175
150
T
, CASE TEMPERATURE ( C)
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
200
500
o
= 25 C
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
o
T
C
T
= 25 C
C
o
100
10
1
T
= MAX RATED
J
CURRENT AS FOLLOWS:
175 - T
150
C
V
= 10V
I = I
25
GS
)
(
100µs
100
V
= 5V
GS
1ms
OPERATION IN THIS
AREA MAY BE
10ms
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
LIMITED BY r
DS(ON)
V
MAX = 60V
DSS
10
10
-4
10
-2
10
1
-6
-5
-3
10
-1
0
100
1
10
, DRAIN TO SOURCE VOLTAGE (V)
10
10
10
10
V
DS
t, PULSE WIDTH (s)
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. PEAK CURRENT CAPABILITY
100
100
80
60
40
20
0
o
V
= 10V
GS
T
=25 C
C
o
STARTING T = 25 C
J
V
= 5V
o
GS
STARTING T = 150 C
J
V
V
= 4.5V
= 4V
GS
GS
10
V
= 3V
GS
If R = 0
t
= (L)(I )/(1.3*RATED BV
- V
)
DD
AV
AS DSS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
If R ≠ 0
t
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
- V ) +1]
DSS DD
AV
0.01
1
0
1.5
3.0
4.5
6.0
7.5
0.1
1
10
t
, TIME IN AVALANCHE (ms)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
AV
FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 6. SATURATION CHARACTERISTICS
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. C0
RFD16N06LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
100
80
60
40
20
0
2.5
2.0
1.5
V
= 15V
DD
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 5V, I = 16A
D
GS
o
o
o
175 C
25 C
-55 C
1.0
0.5
0
6.0
0
1.5
7.5
3.0
4.5
160
-80
-40
120
o
200
0
40
80
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
1.5
2.0
I
,
DS
D
= 250µA
V
= V
I
= 250µA
GS
D
1.5
1.0
1.0
0.5
0
0.5
0
-80
-40
0
40
80
120
160
200
-80
160
-40
120
200
0
40
80
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs
TEMPERATURE
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
5.00
3.75
2.50
1.25
0
60
45
2000
V
= BV
DSS
V
= BV
DD
DD
DSS
C
ISS
1500
1000
500
0
30
15
0
V
C
= 0V, f = 1MHz
GS
0.75 BV
0.50 BV
0.25 BV
= C
+ C
0.75 BV
0.50 BV
0.25 BV
DSS
DSS
DSS
ISS
GS
= C
GD
DSS
DSS
DSS
C
C
RSS
OSS
GD
≈
C
DS
+ C
GD
C
C
OSS
R
= 3.75Ω
L
I
= 0.65mA
G(REF)
GS
V
= 5V
RSS
I
I
G(REF)
G(REF)
0
5
10
15
20
25
t, TIME (µs)
---------------------
---------------------
20
80
I
I
G(ACT)
G(ACT)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. C0
RFD16N06LESM
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
VARY t TO OBTAIN
P
I
+
AS
R
REQUIRED PEAK I
V
DD
G
AS
V
DD
-
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
V
DS
t
d(ON)
t
t
f
r
R
L
V
V
DS
GS
90%
90%
+
V
DD
-
10%
10%
DUT
R
GS
90%
50%
V
GS
V
GS
50%
PULSE WIDTH
10%
FIGURE 15. SWITCHING TIME TEST CIRCUIT
FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
V
DS
V
Q
DD
g(TOT)
R
L
V
DS
V
= 20V
GS
V
= 10V FOR
Q
OR Q
GS
g(10)
g(5)
2
V
GS
L
DEVICES
+
-
V
V
= 10V
DD
GS
V
GS
V
2
= 5V FOR
GS
L
DEVICES
V
GS
= 2V
V
= 1V FOR
DEVICES
DUT
GS
2
L
0
I
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 17. GATE CHARGE TEST CIRCUIT
FIGURE 18. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. C0
RFD16N06LESM
PSPICE Electrical Model
SUBCKT RFD16N06LESM 2 1 3 ;
rev 8/2/93
CA 12 8 1.46e-9
CB 15 14 1.46e-9
CIN 6 8 1.0e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 66.0
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
+
RSLC2
5
ESLC
11
51
-
50
+
-
17
18
-
DBODY
RDRAIN
6
8
EBREAK
ESG
IT 8 17 1
EVTHRES
+
16
21
+
-
19
8
MWEAK
LDRAIN 2 5 1e-9
LGATE 1 9 5.5e-9
LSOURCE 3 7 4.4e-9
LGATE
EVTEMP
+
RGATE
GATE
1
6
-
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.0e-3
RGATE 9 20 3.6
RLDRAIN 2 5 10
RLGATE 1 9 55
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLSOURCE 3 7 44
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.45e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),3.5))}
.MODEL DBODYMOD D (IS = 6.3e-13 RS = 6.8e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI = 4.3 CJO = 1.28e-9 TT = 5.1e-8 M = 0.5)
.MODEL DBREAKMOD D (RS = 2.9e-1 TRS1 = 1e-4 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 9.5e-10 IS = 1e-30 N = 10 M = 0.82)
.MODEL MMEDMOD NMOS (VTO = 2.10 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6)
.MODEL MSTROMOD NMOS (VTO = 2.45 KP = 60.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.79 KP = 0.13 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 36 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.2e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.3e-2 TC2 = 3.1e-5)
.MODEL RSLCMOD RES (TC1 = 5.5e-3 TC2 = 7e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -5.8e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.7e-3 TC2 = 8e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.8 VOFF= -2.8)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.8 VOFF= -4.8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.6 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.6)
.ENDS
For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. C0
RFD16N06LESM
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intended to be an exhaustive list of all such trademarks.
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Sync-Lock™
®*
®
®
®
tm
®
Global Power ResourceSM
GreenBridge™
Green FPS™
PowerTrench
PowerXS™
Programmable Active Droop™
QFET
QS™
Quiet Series™
RapidConfigure™
™
®
TinyBoost
TinyBuck
®
®
Green FPS™ e-Series™
Gmax™
GTO™
TinyCalc™
®
TinyLogic
TINYOPTO™
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Current Transfer Logic™
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®
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THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
www.Fairchildsemi.com, under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild
Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of
up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and
warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is
committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
Preliminary
First Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
No Identification Needed
Obsolete
Full Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Not In Production
Rev. I66
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. C0
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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