SN54LS193J [ONSEMI]
PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER; 可预置BCD / DECADE UP / DOWN COUNTER可预置4位二进制加/减计数器
| 型号： | SN54LS193J |
| 厂家： | 
ONSEMI |
| 描述： | PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER |
| 文件： | 总7页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS192
SN54/74LS193
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate
Count Up and Count Down Clocks are used and in either counting mode the
circuits operate synchronously. The outputs change state synchronous with
the LOW-to-HIGH transitions on the clock inputs.
LOW POWER SCHOTTKY
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without extra
logic, thus simplifying multistage counter designs. Individual preset inputs
allow the circuits to be used as programmable counters. Both the Parallel
Load (PL) and the Master Reset (MR) inputs asynchronously override the
clocks.
J SUFFIX
CERAMIC
CASE 620-09
16
1
• Low Power . . . 95 mW Typical Dissipation
• High Speed . . . 40 MHz Typical Count Frequency
• Synchronous Counting
• Asynchronous Master Reset and Parallel Load
• Individual Preset Inputs
N SUFFIX
PLASTIC
CASE 648-08
16
1
• Cascading Circuitry Internally Provided
• Input Clamp Diodes Limit High Speed Termination Effects
D SUFFIX
SOIC
CASE 751B-03
CONNECTION DIAGRAM DIP (TOP VIEW)
16
1
V
P
MR
14
TC
TC
PL
11
P
P
3
CC
16
0
D
U
2
15
13
12
10
9
ORDERING INFORMATION
NOTE:
SN54LSXXXJ
SN74LSXXXN Plastic
SN74LSXXXD SOIC
Ceramic
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
2
3
4
5
6
8
7
P
1
Q
1
Q
0
CP
CP
Q
Q
GND
LOGIC SYMBOL
D
U
2
3
11 15
1
10
9
PIN NAMES
LOADING (Note a)
HIGH
LOW
PL
P
P
P
P
3
0
1
2
12
13
CP
TC
CP
CP
MR
PL
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Flip-Flop Outputs (Note b)
Terminal Count Down (Borrow) Output (Note b)
Terminal Count Up (Carry) Output (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5
4
U
U
U
D
CP
TC
D
D
MR Q
Q
Q
Q
2 3
0
1
P
Q
TC
TC
n
n
10 U.L. 5 (2.5) U.L.
10 U.L. 5 (2.5) U.L.
10 U.L. 5 (2.5) U.L.
D
U
14
3
2
6
7
V
= PIN 16
CC
GND = PIN 8
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
FAST AND LS TTL DATA
5-1
SN54/74LS192 • SN54/74LS193
STATE DIAGRAMS
LS192 LOGIC EQUATIONS
FOR TERMINAL COUNT
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
TC = Q
Q
Q
CP
U
2
U
0
0
3
1
15
14
13
12
15
14
13
12
TC = Q
Q
Q
CP
3 D
D
LS193 LOGIC EQUATIONS
FOR TERMINAL COUNT
TC = Q
Q
Q
Q
Q
Q
Q
CP
3 U
U
0
0
1
1
2
2
TC = Q
CP
3 D
D
11
10
9
11
10
9
COUNT UP
COUNT DOWN
LS192
LS193
LOGIC DIAGRAMS
P
P
P
P
0
1
2
3
11
15
10
9
1
P
L
(LOAD)
5
CP
U
TC
12
U
(UP COUNT)
(CARRY
OUTPUT)
S
C
S
S
C
S
C
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
T
T
T
T
Q
C
D
D
D
TC
D
13
(BORROW
OUTPUT)
CP
D
4
(DOWN
COUNT)
MR
14
(CLEAR)
3
6
7
2
Q
Q
Q
Q
3
0
1
2
LS192
V
= PIN 16
CC
GND = PIN 8
= PIN NUMBERS
FAST AND LS TTL DATA
5-2
SN54/74LS192 • SN54/74LS193
LOGIC DIAGRAMS (continued)
P
P
P
P
0
1
2
3
11
5
15
10
9
1
P
L
(LOAD)
CP
U
TC
(CARRY
OUTPUT)
U
12
(UP COUNT)
S
C
S
S
S
C
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
T
T
T
T
C
C
D
D
TC
D
13
(BORROW
OUTPUT)
CP
D
4
(DOWN
COUNT)
MR
14
(CLEAR)
3
6
7
2
Q
Q
Q
Q
3
0
1
2
LS193
V
= PIN 16
CC
GND = PIN 8
= PIN NUMBERS
FAST AND LS TTL DATA
5-3
SN54/74LS192 • SN54/74LS193
FUNCTIONAL DESCRIPTION
The LS192 and LS193 are Asynchronously Presettable
Decade and 4-Bit Binary Synchronous UP/DOWN (Revers-
able) Counters. The operating modes of the LS192 decade
counter and the LS193 binary counter are identical, with the
only difference being the count sequences as noted in the
State Diagrams. Each circuit contains four master/slave
flip-flops, with internal gating and steering logic to provide
master reset, individual preset, count up and count down
operations.
Each flip-flop contains JK feedback from slave to master
such that a LOW-to-HIGH transition on its T input causes the
slave, and thus the Q output to change state. Synchronous
switching, as opposed to ripple counting, is achieved by
driving the steering gates of all stages from a common Count
Up line and a common Count Down line, thereby causing all
state changes to be initiated simultaneously. A LOW-to-HIGH
transition on the Count Up input will advance the count by one;
a similar transition on the Count Down input will decrease the
count by one. While counting with one clock input, the other
should be held HIGH. Otherwise, the circuit will either count by
twos or not at all, depending on the state of the first flip-flop,
which cannot toggle as long as either Clock input is LOW.
The Terminal Count Up (TC ) and Terminal Count Down
U
(TC ) outputs are normally HIGH. When a circuit has reached
D
the maximum count state (9 for the LS192, 15 for the LS193),
the next HIGH-to-LOW transition of the Count Up Clock will
cause TC to go LOW. TC will stay LOW until CP goes
U
U
U
HIGH again, thus effectively repeating the Count Up Clock,
but delayed by two gate delays. Similarly, the TC output will
D
go LOW when the circuit is in the zero state and the Count
Down Clock goes LOW. Since the TC outputs repeat the clock
waveforms, they can be used as the clock input signals to the
next higher order circuit in a multistage counter.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset. When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW, information
present on the Parallel Data inputs (P , P ) is loaded into the
0
3
counter and appears on the outputs regardless of the
conditions of the clock inputs. A HIGH signal on the Master
Reset input will disable the preset gates, override both Clock
inputs, and latch each Q output in the LOW state. If one of the
Clock inputs is LOW during and after a reset or load operation,
the next LOW-to-HIGH transition of that Clock will be
interpreted as a legitimate signal and will be counted.
MODE SELECT TABLE
MR
PL
CP
CP
MODE
U
D
H
L
L
L
L
X
L
H
H
H
X
X
H
X
X
H
H
Reset (Asyn.)
Preset (Asyn.)
No Change
Count Up
H
Count Down
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
= LOW-to-HIGH Clock Transition
FAST AND LS TTL DATA
5-4
SN54/74LS192 • SN54/74LS193
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
= MAX, V = V
IN
CC
OH
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
= V or V
IL
MIN,
CC
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
Output LOW Voltage
Input HIGH Current
IH
OL
per Truth Table
OL
20
0.1
µA
mA
mA
mA
mA
V
V
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
CC
CC
I
IH
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–100
34
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
Power Supply Current
–20
= MAX
= MAX
OS
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
f
Maximum Clock Frequency
25
32
MHz
MAX
t
t
CP Input to
17
18
26
24
PLH
PHL
U
ns
ns
ns
TC Output
U
t
t
CP Input to
16
15
24
24
PLH
PHL
D
TC Output
D
V
C
= 5.0 V
CC
= 15 pF
L
t
t
27
30
38
47
PLH
PHL
Clock to Q
t
t
24
25
40
40
PLH
PHL
PL to Q
ns
ns
t
MR Input to Any Output
23
35
PHL
FAST AND LS TTL DATA
5-5
SN54/74LS192 • SN54/74LS193
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Unit
ns
Test Conditions
Min
20
Max
t
t
t
t
Any Pulse Width
W
Data Setup Time
Data Hold Time
Recovery Time
20
ns
s
V
CC
= 5.0 V
5.0
40
ns
h
ns
rec
DEFINITIONS OF TERMS
SETUP TIME (t ) is defined as the minimum time required for
s
tion. A negative HOLD TIME indicates that the correct logic
level may be released prior to the PL transition from
LOW-to-HIGH and still be recognized.
thecorrectlogicleveltobepresentatthelogicinputpriortothe
PLtransitionfromLOW-to-HIGHinordertoberecognizedand
transferred to the outputs.
RECOVERY TIME (t ) is defined as the minimum time
rec
HOLD TIME (t ) is defined as the minimum time following the
h
PL transition from LOW-to-HIGH that the logic level must be
maintained at the input in order to ensure continued recogni-
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
FAST AND LS TTL DATA
5-6
SN54/74LS192 • SN54/74LS193
AC WAVEFORMS
t
W
1.3 V
1.3 V
CP or CP
U
D
t
PLH
t
PHL
Q
1.3 V
1.3 V
Figure 1
CP or CP
1.3 V
t
1.3 V
P
n
U
D
t
PHL
PLH
t
t
PLH
PHL
Q
n
TC or TC
1.3 V
1.3 V
U
D
NOTE: PL = LOW
Figure 2
Figure 3
1.3 V
P
n
PL
1.3 V
t
w
t
t
rec
W
1.3 V
PL
1.3 V
CP or CP
t
t
U
D
PHL
PLH
t
PHL
1.3 V
Q
n
1.3 V
Q
Figure 4
Figure 5
P
1.3 V
1.3 V
n
t
t
h(H)
h(L)
t
s(H)
t
1.3 V
MR
s(L)
1.3 V
PL
Q
t
t
W
rec
1.3 V
CP or CP
U
D
Q = P
Q = P
n
t
PHL
1.3 V
* The shaded areas indicate when the input is permitted
* to change for predictable output performance
Q
Figure 6
Figure 7
FAST AND LS TTL DATA
5-7
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