STK554U392C-E [ONSEMI]
智能功率模块 (IPM)，600V，15A;
| 型号： | STK554U392C-E |
| 厂家： | 
ONSEMI |
| 描述： | 智能功率模块 (IPM)，600V，15A |
| 文件： | 总14页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK554U392C-E
Intelligent Power Module
(IPM)
600 V, 15 A
The STK554U392C−E is a fully−integrated inverter power stage
consisting of a high−voltage driver, six IGBT’s and a thermistor,
suitable for driving permanent magnet synchronous (PMSM) motors,
brushless−DC (BLDC) motors and AC asynchronous motors. The
IGBT’s are configured in a 3−phase bridge with separate emitter
connections for the lower legs for maximum flexibility in the choice of
control algorithm.
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The power stage has a full range of protection functions including
cross−conduction protection, external shutdown and under−voltage
lockout functions. Output stage uses IGBT/FRD technology and
implements Under Voltage Protection (UVP) and Over Current
Protection with a Fault Detection output flag. Internal Boost diodes
are provided for high side gate boost drive.
SIP29 62 x 21.8FP−1
CASE 127EZ
Features
MARKING DIAGRAM
• Three−phase 15 A/600 V IGBT Module with Integrated Drivers
• Typical Values: V (sat) = 1.7 V, V = 1.9 V
CE
F
ABCDD
STK554U392C
• 62.0 mm × 21.8 mm Single In−line Package with Vertical LF Type
• Cross−conduction Protection
• Integrated Bootstrap Diodes and Resistors
• These Devices are Pb−Free and are RoHS Compliant
STK554U392C = Specific Device Code
Certification
• UL1557 (File number : E339285)
A
= Year
B
= Month
C
DD
= Production Site
= Factory Lot code
Typical Applications
• Industrial Pumps
• Industrial Fans
• Industrial Automation
• Heat Pumps, Home Appliances
Device marking is on package underside
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
HS1
HS1
HS2
HS3
LS1
HS2
LS2
HS3
LS3
IC Driver
Pre driver
+
Level Shifter
with
protection
Circuits
LS1
LS3
LS2
Figure 1. Functional Diagram
1
© Semiconductor Components Industries, LLC, 2018
Publication Order Number:
June, 2019 − Rev. 1
STK554U392C/D
STK554U392C−E
STK554U392C
VB 1: 9pin
VCC
+
+
+
CB1
CB2
CB3
13pin: P
U,VS 1:10pin
VB 2: 5pin
CS1
CS2
+
V,V2:6pin
VB 3: 1pin
RSU
7pin: U −
RSV
19pin: V −
21pin: W −
RSW
W,VS 3: 2pin
HIN1:20pin
HIN2:22pin
HIN3:23pin
LIN1:24pin
LIN2:25pin
LIN3:26pin
Op −Amp,
Controller
10pin:U, VS 1
6pin:V, VS 2
2pin:W, VS 3
Control
Circuit
(5V)
:27pin
TH
FLTEN:18pin
ITRIP:16pin
Motor
RTH
RP
RS,
Controller
VD 4 = 15 V
VDD:28pin
VSS :29pin
CD4
Figure 2. Application Schematic
Usage Precaution
please connect the pull−down resistor(about 2.2 to
3.3 kW) outside to decrease the influence of the
noise by wiring etc
1. It is essential that warning length between
terminals in the snubber circuit be kept as short as
possible to reduce the effect of surge voltages.
Recommended value of “CS” is in the range of 0.1
to 10 mF
2. The “FLTEN” terminal (Pin 18) is I/O terminal;
Fault output / Enable input. It is used to indicate an
internal fault condition of the module and also can
be used to disable the module operation
3. Inside the IPM, a thermistor used as the
temperature monitor for internal substrate is
connected between VSS terminal and TH terminal
therefore, an external pull up resistor connected
between the TH terminal and an external power
supply should be used
5. As protection of IPM to the unusual current by a
short circuit etc. it recommends installing shunt
resistors and an over−current protection circuit
outside. Moreover, for safety, a fuse on Vcc line is
recommended
6. Disconnection of terminals U, V, or W during
normal motor operation will cause damage to IPM,
use caution with this connection
7. When input pulse width is less than 1 ms, an output
may not react to the pulse. (Both ON signal and
OFF signal)
This data shows the example of the application circuit,
does not guarantee a design as the mass production set.
4. The pull−down resistor (:33 kW(typ)) is connected
with the inside of the signal input terminal, but
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2
STK554U392C−E
V+ (13)
VB
3 (1)
3 (2)
W,VS
VB
2 (5)
V,VS2 (6)
VB
1 (9)
U,VS1 (10)
U.V.
U.V.
U.V.
DB
DB DB
RB
U- (17)
V- (19)
W- (21)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1 (20)
HIN2 (22)
HIN3 (23)
LIN1 (24)
LIN2 (25)
LIN3 (26)
Logic
Logic
Logic
Thermistor
TH (27)
VDD (28)
shutdown
Under Voltage
Derect
VSS
(29)
S Q
R
ITRIP (16)
+
−
Timer
Enable / Disable
Latch time about 2msec.
FLTEN (18)
Figure 3. Simplified Block Diagram
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STK554U392C−E
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
Name
VB3
Description
High Side Floating Supply Voltage 3
2
W, VS3
VB2
Output 3 − High Side Floating Supply Offset Voltage
High Side Floating Supply voltage 2
Output 2 − High Side Floating Supply Offset Voltage
High Side Floating Supply voltage 1
Output 1 − High Side Floating Supply Offset Voltage
Positive Bus Input Voltage
5
6
V,VS2
VB1
9
10
13
16
17
18
19
20
21
22
23
24
25
26
27
28
29
U,VS1
V+
ITRIP
U−
Current protection pin
Low Side Emitter Connection − Phase U
Enable input / Fault output
FLTEN
V−
Low Side Emitter Connection − Phase V
Logic Input High Side Gate Driver − Phase U
Low Side Emitter Connection − Phase W
Logic Input High Side Gate Driver − Phase V
Logic Input High Side Gate Driver − Phase W
Logic Input Low Side Gate Driver − Phase U
Logic Input Low Side Gate Driver − Phase V
Logic Input Low Side Gate Driver − Phase W
Thermistor output
HIN1
W−
HIN2
HIN3
LIN1
LIN2
LIN3
TH
VDD
VSS
+15 V Main Supply
Negative Main Supply
NOTE: Pins 3, 4, 7, 8, 11, 12, 14, 15 are not present.
Table 2. ABSOLUTE MAXIMUM RATINGS at T = 25°C (Note 1, 2)
C
Rating
Supply Voltage
Symbol
VCC
VCE
Io
Conditions
Value
450
600
+15
8
Unit
V
V+ to U−, V−, W−, surge < 500 V (Note 3)
V+ to U, V, W or U, V, W, to U−, V−, W−
V+, U−, V−, W−, U, V, W terminal current
Collector−emitter Voltage
V
Output Current
A
V+, U−, V−, W−, U, V, W terminal current,
Tc = 100°C
A
Output Peak Current
Iop
V+, U−, V−, W−, U, V, W terminal current,
+30
20
A
V
P.W. = 1 ms
Pre−driver Voltage
VD1, 2, 3, 4
VB1 to U, VB2 to V, VB3 to W, VDD to VSS
(Note 4)
Input Signal Voltage
VIN
VFLTEN
Pd
HIN1, 2, 3, LIN1, 2, 3
FLTEN terminal
−0.3 to VDD
−0.3 to VDD
35
V
V
FLTEN Terminal Voltage
Maximum Power Dissipation
Junction Temperature
Storage Temperature
Operating Case Temperature
Tightening Torque
IGBT per 1 channel
IGBT, FRD, Pre−Driver IC
W
°C
°C
°C
Tj
150
Tstg
Tc
−40 to +125
−40 to +100
0.9
IPM case
A screw part (Note 5)
50 Hz sine wave AC 1 minute (Note 6)
Nm
Withstand Voltage
Vis
2000
VRMS
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
3. Surge voltage developed by the switching operation due to the wiring inductance between + and U−(V−, W−) terminal.
4. VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS terminal voltage.
5. Flatness of the heat−sink should be less than −50 μm to +100 μm.
6. Test conditions : AC2500V, 1 second
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STK554U392C−E
Table 3. RECOMMENDED OPERATING RANGES at Tc = 25_C (Note 7)
Rating
Symbol
Conditions
V+ to U−(V−,W−)
VB1 to U, VB2 to V, VB3 to W
to V (Note 7)
Min
0
Typ
280
15
15
−
Max
450
17.5
16.5
5.0
0.3
20
Unit
V
Supply Voltage
V
CC
Pre−driver Supply Voltage
VD1, 2, 3
VD4
12.5
13.5
3.0
0
V
V
DD
V
SS
ON−state Input Voltage
OFF−state Input Voltage
PWM Frequency
VIN(ON)
VIN(OFF)
fPWM
HIN1,HIN2,HIN3,
LIN1,LIN2,LIN3
V
−
1.0
0.5
1.0
0.6
−
kHz
μs
Dead Time
DT
Turn−off to turn−on (external)
ON and OFF
−
−
Allowable Input Pulse Width
Package Mounting Torque
PWIN
−
−
μs
‘M3’ type screw
−
0.9
Nm
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Pre−drive power supply (VD4 = 15 1.5 V) must have the capacity of Io = 20 mA (DC), 0.5 A (Peak).
Table 4. ELECTRICAL CHARACTERISTICS at Tc = 25_C, VD1, VD2, VD3, VD4 = 15 V
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
POWER OUTPUT SECTION
Collector−emitter Leakage Current
Bootstrap Diode Reverse Current
Collector to Emitter Saturation Voltage
V
= 600 V
I
−
−
−
−
−
−
−
−
−
−
100
100
2.4
−
mA
mA
V
CE
CE
VR(BD) = 600 V
Ic = 15 A, Tj = 25_C
Ic = 8 A, Tj = 100_C
IF = −15 A, Tj = 25_C
IF = −8 A, Tj = 100_C
IGBT
IR(BD)
(sat)
V
1.7
1.4
1.9
1.4
−
CE
V
Diode Forward Voltage
VF
2.6
−
V
V
Junction to Case Thermal Resistance
3.5
5.0
_C/W
qj−c(T)
qj−c(D)
FRD
−
SWITCHING CHARACTER
Switching Time
Io = 15 A
Inductive load
t ON
t OFF
Eon
−
−
−
−
−
−
−
−
−
−
0.45
0.55
410
390
800
270
280
550
12
−
−
−
−
−
−
−
−
−
−
ms
ms
mJ
mJ
mJ
mJ
mJ
mJ
mJ
ns
+
Turn−on Switching Loss
Ic = 15 A, V = 300 V,
V
DD
= 15 V, L=3.9 mH
Turn−off Switching Loss
Eoff
Tc = 25_C
Total Switching Loss
Etot
+
Turn−on Switching Loss
Ic = 8 A, V = 300 V,
= 15 V, L = 3.9 mH
Eon
V
DD
Turn−off Switching Loss
Eoff
Tc = 100_C
Total Switching Loss
Etot
+
Diode Reverse Recovery Energy
Diode Reverse Recovery Time
Reverse Bias Safe Operating Area
Short Circuit Safe Operating Area
Allowable Offset Voltage Slew Rate
CONTROL (PRE−DRIVER) SECTION
Pre−driver Power Dissipation
I = 8 A, V = 400 V, V = 15 V,
Erec
Trr
F
DD
L = 3.9 mH, Tc = 100_C
Io = 20°, VCE = 450 V
54
RBSOA
SCSOA
dv/dt
Full Square
VCE = 400 V, Tc = 100_C
Between U(V,W) to U−(V−,W−)
4.0
−
−
−
ms
−50
50
V/ns
VD1, 2, 3 = 15 V
VD4 = 15 V
ID
−
−
0.08
1.6
−
0.4
4.0
−
mA
High level Input Voltage
Low level Input Voltage
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to VSS
Vin H
Vin L
2.5
−
V
V
−
0.8
143
Logic 1 input Leakage Current
VIN = +3.3 V
I
−
100
mA
IN+
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STK554U392C−E
Table 4. ELECTRICAL CHARACTERISTICS at Tc = 25_C, VD1, VD2, VD3, VD4 = 15 V (continued)
Parameter
Logic 0 input Leakage Current
FLTEN Terminal Sink Current
FLTEN Clearance Delay Time
FLTEN Threshold
Test Conditions
Symbol
Min
Typ
−
Max
2.0
−
Unit
mA
mA
ms
V
VIN = 0 V
I
IN−
−
FAULT: ON / VFLTEN = 0.1 V
From time fault condition clear
VEN rising
IoSD
FLTCLR
VEN+
−
2.0
1.9
−
1.55
−
2.25
2.5
−
VEN falling
VEN−
0.8
0.44
340
250
10.5
−
V
ITRIP Threshold Voltage
ITRIP(16) to VSS(29)
VITRIP
0.49
550
350
11.1
0.54
800
V
ITRIP to Shutdown Propagation Delay
ITRIP Blanking Time
t
ns
ns
V
ITRIP
t
ITRIPBL
V
and V Supply Undervoltage
V
CCUV+
11.7
11.5
−
CC
BS
Protection Reset
V
BSUV+
V
and V Supply Undervoltage
V
V
10.3
0.14
42.3
10.9
0.2
47
V
V
CC
BS
CCUV−
Protection set
BSUV−
V
CC
and V Supply Undervoltage
V
CCUVH
BS
Hysteresis
V
BSUVH
Thermistor for Substrate Temperature
Monitor
Resistance between TH(27) and VSS(29)
Rt
51.7
kW
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Reference voltage is “VSS” terminal voltage unless otherwise specified.
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STK554U392C−E
APPLICATIONS INFORMATION
Input / Output Timing Chart
VBS under voltage protection reset signal
ON
HIN1, 2, 3
OFF
LIN1, 2, 3
VDD
VDD under voltage protection reset signal (Note 2)
VBS under voltage protection reset signal (Note 3)
VB1, 2, 3
VIT ≥ 0.54 V
(Note 4)
ITRIP terminal
Voltage
FLTEN
(Note 1)
(Note 1)
ON
U pper
U, V, W
OFF
Lower
U, V, W
Automatically reset after protection
(typ.2 msec)
NOTES:
1. Shows the prevention of shoot−thru via control logic, however, more dead time must be added to account for switching delay
externally.
2. When VDD decreases all gate output signals will go low and cut off all 6 IGBT outputs. When VDD rises the operation will resume
immediately.
3. When the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The outputs return
to normal operation immediately after the upper side gate voltage rises.
4. When VITRIP exceeds threshold all IGBT’s are turned off and normal operation resumes 2 ms (typ) after over current condition
is removed.
Figure 4. Input / Output Timing Chart
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STK554U392C−E
Table 5. LOGIC LEVEL TABLE
INPUT
OUTPUT
HIN
LIN
Itrip
High side IGBT
Low side IGBT
U,V,W
VP
FLTEN
OFF
OFF
OFF
OFF
ON
H
L
L
ON
OFF
ON
L
L
H
L
L
L
NU, NV, NW
OFF
OFF
OFF
OFF
OFF
OFF
OFF
High Impedance
High Impedance
High Impedance
H
X
H
X
L
H
Table 6. THERMISTOR CHARACTERISTICS
Parameter
Symbol
Condition
Min
44.6
1.28
4010
−40
Typ
47.0
1.41
4050
−
Max
49.4
1.53
4091
+125
Unit
R
Tc = 25℃
kW
kW
K
25
Resistance
R
Tc = 125℃
125
B−Constant (25 to 50℃)
B
−
−
Temperature Range
−
°C
Figure 5. Thermistor Resistance versus Case Temperature
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STK554U392C−E
Condition:Pull−up resistor = 4.7 kphm, Pull−up voltage of TH = 5 V
Figure 6. Thermistor Voltage versus Case Temperature
FAULT Output
Capacitors on High Voltage and VDD Supplies
The FLTEN terminal is an open drain output requiring a
pull−up resistor. If the pull−up voltage is 5 V, use a pull−up
resistor with a value of 6.8 kW or higher. If the pull−up
voltage is 15 V, use a pull−up resistor with a value of 20 kW
or higher. The FAULT output is triggered if there is a VDD
undervoltage or an overcurrent condition.
The terminal has a function of enable output, this pin is
used to enable or shut down the built−in driver. If the voltage
on the FLTEN pin rises above the ENABLE ON−state
voltage, the output drivers are enabled. If the voltage on the
ELTEN pin falls below the ENABLE OFF−state voltage, the
drivers are disabled.
Both the high voltage and V
electrolytic capacitor and an additional high frequency
capacitor.
supplies require an
DD
Minimum Input Pulse Width
When input pulse width is less than 1.0 ms, an output may
not react to the pulse. (Both ON signal and OFF signal)
Calculation of bootstrap capacitor value.
The bootstrap capacitor value CB is calculated using the
following approach. The following parameters influence the
choice of bootstrap capacitor:
• VBS : Bootstrap power supply.
15 V is recommended
UnderVoltage Lockout Protection
• QG : Total gate charge of IGBT at VBS = 15 V.
132 nC
• UVLO : Falling threshold for UVLO.
Specified as 12 V
If VDD goes below the VDD supply undervoltage lockout
falling threshold, the FAULT output is switched on. The
FAULT output stays on until VDD rises above the VDD
supply undervoltage lockout rising threshold. After VDD
has risen above the threshold to enable normal operation, the
driver waits to receive an input signal on the LIN input
before enabling the driver for the HIN signal.
• ID
: High side drive consumption current.
Specified as 400 mA
MAX
• t
: Maximum ON pulse width of high side IGBT
ONMAX
Overcurrent Protection
Capacitance calculation formula
CB = (QG + IDMAX × tONMAX) / (VBS − UVLO)
An over−current condition is detected if the voltage on the
ITRIP pin is larger than the reference voltage. There is a
blanking time of typically 350 ns to improve noise
immunity. After a shutdown propagation delay of typically
550ns, the FAULT output is switched on.
The over−current protection threshold should be set to be
equal or lower to 2 times the module rated current (IO).
An additional fuse is recommended to protect against
system level or abnormal over−current fault conditions.
CB is recommended to be approximately 3 times the value
calculated above. The recommended value of CB is in the
range of 1 to 47 mF, however, the value needs to be verified
prior to production. When not using the bootstrap circuit,
each high side driver power supply requires an external
independent power supply.
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STK554U392C−E
100
The internal bootstrap circuit uses a MOSFET. The turn
on time of this MOSFET is synchronized with the turn on of
the low side IGBT. The bootstrap capacitor is charged by
turning on the low side IGBT.
If the low side IGBT is held on for a long period of time
(more than one second for example), the bootstrap voltage
on the high side MOSFET will slowly discharge.
10
1
0.1
0.01
0.1
1
10
100
1000
tONMAX [ms]
Figure 7. Bootstrap Capacitance versus tONMAX
Table 7. MOUNTING INSTRUCTIONS
Item
Recommended Condition
Pitch
56.0 0.1 mm (Please refer to Package Outline Diagram)
Diameter : M3
Screw head types: pan head, truss head, binding head
Screw
Plane washer
Washer
The size is D : 7 mm, d : 3.2 mm and t : 0.5 mm JIS B 1256
Material: Aluminum or Copper
Warpage (the surface that contacts IPM) : −50 to +100 mm
Screw holes must be countersunk
No contamination on the heat sink surface that contacts IPM
Heat sink
Final tightening : 0.6 to 0.9 Nm
Temporary tightening : 20 to 30 % of final tightening
Torque
Grease
Silicone grease
Thickness : 100 to 200 mm
Uniformly apply silicone grease to whole back
Figure 8. Module Mounting Details: Components; Washer Drawing; Need for Even Spreading of Thermal Grease
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STK554U392C−E
TEST CIRCUITS
ICE
• I
CE
M
9
A
VD1 = 15 V
U+
13
10
V+
13
6
W+
13
2
U−
10
17
V−
6
W−
10
5
M
N
2
VD2 = 15 V
19
21
VCE
6
1
VD3 = 15 V
VD4 = 15 V
U(DB)
9
V(DB)
W(DB)
2
M
N
5
1
28
29
29
29
N
29
NOTE: U+, V+, W+ : High side phase
U−, V−, W− : Low side phase
Figure 9. Test Circuit for ICE
• V (sat) (Test by pulse)
CE
M
9
VD1 = 15 V
U+
13
10
20
V+
13
6
W+
13
2
U−
10
17
24
V−
6
W−
10
5
M
N
2
VD2 = 15 V
19
25
21
6
1
V
VCE
(sat)
m
22
23
26
IC
VD3 = 15 V
2
5V
VD4 = 15 V
m
25
N
29
27
Figure 10. Test Circuit for VCE(sat)
• V (Test by pulse)
F
M
U+
V+
13
6
W+
13
2
U−
10
17
V−
6
W−
2
M
N
13
10
19
21
V
IF
VF
N
Figure 11. Test Circuit for VF
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STK554U392C−E
ID
• ID
M
A
VD1
9
VD2
5
VD3
1
VD4
28
M
N
10
6
2
29
VD*
N
Figure 12. Test Circuit for ID
• Switching time (The circuit is a representative example of the low side U phase.)
Input signal
(0 to 5V)
13
10
9
VS1 = 15 V
10
5
VS2 = 15 V
VCC
6
1
90%
VS3 = 15 V
IO
2
10%
Input signal
24
28
Io
VDD = 15 V
tOFF
tON
29
16
17
A
Figure 13. Switching Time Test Circuit
• RB−SOA (The circuit is a representative example of the lower side U phase.)
Input signal
(0 to 5V)
13
10
9
VS1 = 15 V
VS2 = 15 V
10
5
VCC
6
1
VS3 = 15 V
Input signal
VDD = 15 V
2
IO
24
28
Io
29
16
17
A
Figure 14. RB−SOA Test Circuit
ORDERING INFORMATION
Device
Package
Shipping
STK554U392C−E
MODULE
SIP29 62x21.8FP−1
Vertical Type (Pb−Free)
8 Units / Tube
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP29 62x21.8FP−1
CASE 127EZ
ISSUE O
DATE 07 MAY 2018
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DOCUMENT NUMBER:
DESCRIPTION:
98AON87197G
SIP29 62x21.8FP−1
PAGE 1 OF 1
ON Semiconductor and
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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© Semiconductor Components Industries, LLC, 2018
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