STK672-640CN-E [ONSEMI]
Unipolar 2-Phase Stepper Motor Driver;型号: | STK672-640CN-E |
厂家: | ONSEMI |
描述: | Unipolar 2-Phase Stepper Motor Driver 电动机控制 |
文件: | 总31页 (文件大小:487K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Ordering number : ENA2317
STK672-640CN-E
Thick-Film Hybrid IC
2-phase Stepper Motor Driver
http://onsemi.com
Overview
The STK672-640CN-E is a hybrid IC for use as a unipolar, 2-phase stepper motor driver with PWM current control.
Applications
Office photocopiers, printers, etc.
Features
Built-in motor terminal open detection function(output current OFF).
There is a terminal to coordinate motor terminal open detection current.
Built-in overcurrent detection function, overheat detection function (output current OFF).
FAULT1 signal (active low) is output when any of motor terminal open, overcurrent or overheat is detected.
The FAULT2 signal is used to output the result of activation of protection circuit detection at 3 levels.
Built-in power on reset function.
The motor speed is controlled by the frequency of an external clock signal.
2 phase or 1-2 phase excitation switching function.
Using either or both edges of the clock signal switching function.
Phase is maintained even when the excitation mode is switched.
Rotational direction switching function.
Supports schmitt input for 2.5V high level input.
Incorporating a current detection resistor (0.089Ω: resistor tolerance 2%), motor current can be set using two
external resistors.
The ENABLE pin can be used to cut output current while maintaining the excitation mode.
With a wide current setting range, power consumption can be reduced during standby.
No motor sound is generated during hold mode due to external excitation current control.
Supports compatible pins with STK672-630CN-E.
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Maximum supply voltage 1
Maximum supply voltage 2
Input voltage
Symbol
Conditions
Ratings
Unit
V
V
V
max
ENABLE=GND
No signal
50
0.3 to 6.0
0.3 to 6.0
20
CC
max
V
DD
Vin max
IOP max
IOH max1
IOH max2
IOF max
PdMF max
PdPK max
Tcmax
Logic input pins
V
Output current 1
10μs 1 pulse (resistance load)
A
Output current 2
V
V
= 5V, CLOCK 200Hz
A
4.0
DD
Output current 3
= 5V, CLOCK 200Hz, V 29V
A
4.5
DD
CC
Output current 4
16pin Output current
mA
W
W
°C
°C
°C
10
Allowable power dissipation 1
Allowable power dissipation 2
Operating substrate temperature
Junction temperature
Storage temperature
With an arbitrarily large heat sink. Per MOSFET
No heat sink
8.3
3.1
105
Tjmax
150
Tstg
40 to 125
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 31 of this data sheet.
Semiconductor Components Industries, LLC, 2014
March, 2014 Ver. 2.2
31814HK 018-14-0004 No.2317-1/31
STK672-640CN-E
Allowable Operating Ranges at Tc=25C
Parameter
Operating supply voltage 1
Operating supply voltage 2
Input high voltage
Symbol
Conditions
With signals applied
Ratings
unit
V
V
0 to 46
CC
DD
IH
V
V
V
With signals applied
55%
V
Pins 10, 12, 13, 14, 15, 17, V =55%
DD
2.5 to V
V
DD
Input low voltage
Pins 10, 12, 13, 14, 15, 17, V =55%
0 to 0.8
V
IL
DD
Tc=105C, CLOCK200Hz,
Output current 1
Output current 2
I
1
3.0
3.3
A
A
OH
Continuous operation, duty=100%
Tc=80C, CLOCK200Hz,
I
I
2
3
4
Continuous operation, duty=100%,
OH
See the motor current (I
) derating curve
OH
Tc=105C, CLOCK200Hz, V 29V
CC
Output current 3
Continuous operation, duty=100%
3.5
3.8
A
A
OH
See the motor current (I
) derating curve
OH
Tc=80C, CLOCK200Hz, V 29V
CC
Output current 4
I
f
Continuous operation, duty=100%,
OH
See the motor current (I
) derating curve
OH
CLOCK frequency
Minimum pulse width: at least 10s
0 to 50
0 to 105
kHz
C
V
CL
Recommended operating
substrate temperature
Tc
Vref
No condensation
Recommended Vref range
Tc=105C
0.14 to 1.31
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics at Tc=25C, V =24V, V =5.0V *1
CC DD
Parameter
Symbol
Conditions
min
typ
5.0
max
8.0
unit
mA
A
V
supply current
I
Pin 9 current, ENABLE=Low
DD
CCO
Output average current *2
FET diode forward voltage
Output saturation voltage
Ioave
Vdf
R/L=1/0.62mH in each phase
0.519
0.625
0.83
0.20
0.731
1.5
If=1A (R =23)
V
L
Vsat
R =23
0.33
V
L
Input high voltage
V
Pins 10, 12, 13, 14, 15, 17
Pins 10, 12, 13, 14, 15, 17
Pins 10, 12, 13, 14, 15, 17=5V
Pins 10, 12, 13, 14, 15, 17=GND
2.5
V
V
IH
DD
Input low voltage
V
0.3
0.8
V
Control
IL
Input pin
5V level input current
GND level input current
Output low voltage
I
I
50
75
10
A
A
V
ILH
ILL
V
Pin 16 (I =5mA)
O
0.25
0.5
FAULT 1
pin
OLF
5V level leakage current
Pin 16 =5V
I
10
A
ILF
FAULT2 opened motor pin
detection output voltage
FAULT2 Overcurrent detection
output voltage
V
1
2
3
0.0
2.4
3.1
0.01
2.5
0.2
OF
OF
OF
FAULT 2
pin
Pin 8 (when all protection functions have
been activated)
V
V
2.6
3.5
V
FAULT2 Overheat detection
output voltage
3.2
Vref input bias current
I
Pin 19 =1.0V
1
A
kHz
C
IB
PWM frequency
fc
29
45
61
Overheat detection temperature
Drain-source cut-off current
TSD
Design guarantee
144
I
V
=100V, Pins 2, 6, 9, 18=GND
1
A
DSS
DS
Notes
*1: A fixed-voltage power supply must be used.
*2: The value for Ioave assumes that the lead frame of the product is soldered to the mounting circuit board.
*3: Maximum value of operating supply voltage 1 (Vcc) can not supply to STK672-6** series, depending on motor
current value. Refer to “8. Other usage notes ” of Technical data.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.2317-2/31
STK672-640CN-E
Derating Curve of Motor Current, I
vs. STK672-640CN-E Operating Substrate Temperature, Tc
OH,
5
4.5
4
200Hz 2phaseEx ,Vcc 29V
200Hz 2phaseEx ,Vcc 46V
3.5
3
2.5
Hold
2
Hold
Vcc 29V
1.5
1
Vcc 46V
0.5
0
0
10 20 30 40 50 60 70 80 90 100 110
Operation substrate temperature Tc °C
Notes
The current range given above represents conditions when output voltage is not in the avalanche state.
If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-6** series hybrid ICs
given in a separate document.
The operating substrate temperature, Tc, given above is measured while the motor is operating.
Because Tc varies depending on the ambient temperature, Ta, the value of I , and the continuous or intermittent
OH
operation of I , always verify this value using an actual set.
OH
The Tc temperature should be checked in the center of the metal surface of the product package.
No.2317-3/31
STK672-640CN-E
Block Diagram
VrefOP
7
FAULT2
8
A
AB
F2
B
BB
F4
4
5
3
1
V
=5V
DD
9
V
DD
F1
F3
MODE1
N.C
10
11
Excitation mode
selection
FAO
Phase
FAB
FBO
FBB
excitation
signal
generator
MODE2 17
CLOCK 12
Phase
advance
counter
13
CWB
Output
Open
detection
Latch
Circuit
R2
R1
Power-on
reset
RESETB
ENABLE
14
15
Overcurrent
detection
Latch
Circuit
P.G2
P.G1
2
6
AI
BI
Current control
chopper circuit
FAULT1 signal
FAULT2 signal
16
FAULT1
Vref/4.9
Vref
Latch
Circuit
Overheating
detection
Amplifier
V
SS
V
SS
18
19
N.C
Vref
No.2317-4/31
STK672-640CN-E
Measurement Circuit
(The terminal which is not appointed is open. The measurement circuit of STK672-630CN-E is the
same as STK672-640CN-E.)
24V
1. Vdf
23Ω
9
2
6
V
Vdf
12
10
4
5
3
17
13
1
15
14
19
STK672-
64xCN-E
16
18
GND
2. IILF,IILH,IILL,IIB
3. Vsat
5V
CLOCK
5V
24V
23Ω
5V
9
9
12
12
IILF
10
17
13
15
14
5V
10
17
13
15
14
4
5
3
IILH
4
5
3
A
IILL
1
GND
1
STK672-
64xCN-E
STK672-
64xCN-E
IIB
16
19
V
Vsat
1V
19
16 18
A
2
6
18
2
6
GND
GND
4. Icco, Ioave, fc,VOLF
Icco
A
5V
0.62mH
9
1Ω
Ioave
12
4
10
5
24V
17
13
15
14
3
1
+
100μ
STK672-
64xCN-E
Ioave
fc
SW
Close SW at
mesurement of VOLF
7.5K
1K
910
19
16 18
2
6
VOLF
GND
No.2317-5/31
STK672-640CN-E
Sample Application Circuit
2 phase stepper motor driver
V
(5V)
DD
9
CLOCK
MODE1
MODE2
CWB
12
10
17
13
15
A
4
V
AB
5
CC
24V
ENABLE
B
3
RESETB
BB
14
1
STK672
+
-640CN-E
R01
+
R03
C01
at least 100F
FAULT
16
19
P.G2
2
Vref
C02
10F
6
18
P.G1
P.GND
N.C
R02
Precautions
[GND wiring]
To reduce noise on the 5V/24V system, be sure to place the GND of C01 in the circuit given above as close as possible
to Pin 2 and Pin 6 of the hybrid IC.
In addition, in order to set the current accurately, the GND side of RO2 of Vref must be connected to the shared ground
terminal used by the Pin P.G1 and P.G2.
[Input pins]
If V
is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to P. GND,
DD
Pin 2,6. Measures must also be taken so that a voltage equal to or greater than V
is not input.
DD
Do not wire by connecting the circuit pattern on the P.C.B side to N.C Pins. shown in the internal block diagram.
Apply 2.5V high level input to pins 10, 12, 13, 14, 15, and 17.
Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 14, 15, and 17
are used as inputs, a 1 to 20k pull-up resistor (to V ) must be used.
DD
At this time, use a device for the open collector driver that has output current specifications that pull the voltage down to
less than 0.8V at Low level (less than 0.8V at Low level when I =5mA).
OL
[Current setting Vref]
Considering the specifications for the Vref input bias current IIB, we recommend a value 1k or less for R02.
If the motor current is temporarily reduced, the circuit given below(STK672-640CN-E: I >0.3A)
OH
is recommended.
5V
5V
R01
Vref
R01
Vref
R02
R3
R3
R02
No.2317-6/31
STK672-640CN-E
[Setting the motor current]
The motor current, I , is set using the Pin 19 voltage, Vref, of the hybrid IC.
OH
Equations related to I
and Vref are given below.
OH
Vref (RO2 (RO2+RO1))V (5V) ··········································· (1)
DD
(Vref 4.9) Rs ······························································· (2)
I
OH
The value of 4.9 in Equation (2) above represents the Vref voltage as divided by a circuit inside the control IC.
Rs : 0.089 (Current detection resistor inside the hybrid IC)
IOH
0
Input Pin Functions
Pin Name
CLOCK
Pin No.
12
Function
Input Conditions When Operating
Reference clock for motor phase current switching
Operates on the rising edge of the signal (MODE2=H)
Low: 2-phase excitation
High: 1-2 phase excitation
High: Rising edge
MODE1
MODE2
CWB
10
17
13
Excitation mode selection
Motor direction switching
Low: Rising and falling edge
Low: CW (forward)
High: CCW (reverse)
System reset
RESETB
ENABLE
14
15
Initial state of A and BB phase excitation in the timing charts
is set by switching from low to high.
A reset is applied by a low level
The A, AB, B, and BB outputs are turned off, and after
operation is restored by returning the ENABLE pin to the
high level, operation continues with the same excitation
timing as before the low-level input.
The A, AB, B, and BB outputs are turned off by a
low-level input.
Output Pin Functions
Pin Name
Pin No.
Function
Input Conditions When Operating
Low level is output when detected.
Monitor pin used when over-current detection or overheat
detection function is activated.
FAULT1
16
The result of activation of protection circuit detection is
output.
FAULT2
VrefOP
8
7
3 levels output voltage
Monitor pin of reference voltage used when opened motor
terminal detection.
Normal DC voltage output (typ98mV)
Note : See the timing chart for the concrete details on circuit operation.
No.2317-7/31
STK672-640CN-E
Timing Charts
2-phase excitation
V
DD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB
CLOCK
ENABLE
FAO
FAB
FBO
FBB
1-2 phase excitation
V
DD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB
CLOCK
ENABLE
FAO
FAB
FBO
FBB
No.2317-8/31
STK672-640CN-E
1-2 phase excitation (CWB)
V
DD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB
CLOCK
ENABLE
FAO
FAB
FBO
FBB
2 phase excitation Switch to 1-2 phase excitation
V
DD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB
CLOCK
ENABLE
FAO
FAB
FBO
FBB
No.2317-9/31
STK672-640CN-E
1-2 phase excitation (ENABLE)
V
DD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB
CLOCK
ENABLE
FAO
FAB
FBO
FBB
1-2 phase excitation (Hold operation results during fixed CLOCK)
V
DD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB
CLOCK
ENABLE
FAO
Hold operation
FAB
FBO
FBB
No.2317-10/31
STK672-640CN-E
2 phase excitation (MODE 2)
V
DD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB
CLOCK
ENABLE
FAO
FAB
FBO
FBB
1-2 phase excitation (MODE 2)
V
DD
Power On Reset
(or RESETB)
MODE1
MODE2
CWB
CLOCK
ENABLE
FAO
FAB
FBO
FBB
No.2317-11/31
STK672-640CN-E
Package Dimensions
unit : mm
SIP19 29.2x14.4
CASE 127CF
ISSUE O
19
1
No.2317-12/31
STK672-640CN-E
STK672-640CN-E
Technical data
1. Input Pins and Functional Overview
2. STK672-640CN-E over current detection, thermal shutdown detection.
3. STK672-640CN-E Allowable Avalanche Energy
4. STK672-640CN-E Internal Loss Calculation
5. Thermal Design
6. Package Power Loss PdPK Derating Curve for the Ambient Temperature Ta
7. Example of Stepper Motor Driver Output Current Path (1-2 phase excitation)
8. Other usage notes
No.2317-13/31
STK672-640CN-E
1. I/O Pins and Functions of the Control Block
[Pin description]
HIC pin
Pin Name
MODE1
MODE2
CLOCK
CWB
Function
10
17
12
13
14
15
16
8
Excitation mode selection
External CLOCK (motor rotation instruction)
Sets the direction of rotation of the motor axis
System reset
RESETB
ENABLE
FAULT1
FAULT2
VrefOP
Vref
Motor current OFF
Motor terminal open /Overcurrent /over-heat detection output
7
Monitor pin of reference voltage used when opened motor terminal detection.
Current value setting
19
Description of each pin
1-1. [MODE1, MODE2 (Selecting the excitation mode, and selecting one edge or both edges of the CLOCK)]
Excitation select mode terminal (7pages of input pin functions for excitation mode selection),
selecting the CLOCK input edge(s).Mode setting active timing
MODE1=0: 2-phase excitation
MODE2=1: Rising edge of CLOCK
MODE1=1: 1-2 phase excitation
MODE2=0: Rising and falling edges of CLOCK
See the timing charts for details on output operation in these modes.
Note: Do not change the mode within 5s of the input rising or falling edge of the CLOCK signal.
1-2.[CLOCK (Phase switching clock)]
Input frequency: DC-20kHz (when using both edges) or DC-50kHz (when using one edge)
Minimum pulse width: 20s (when using both edges) or 10s (when using one edge)
Pulse width duty: 40% to 50% (when using both edges)
Both edge, single edge operation
MODE2:1 The excitation phase moves one step at a time at the rising edge of the CLOCK pulse.
MODE2:0 The excitation phase moves alternately one step at a time at the rising and falling edges of the CLOCK pulse.
1-3.[CWB (Motor direction setting)]
When CWB=0: The motor rotates in the clockwise direction.
When CWB=1: The motor rotates in the counterclockwise direction.
See the timing charts for details on the operation of the outputs.
Note: Do not allow CWB input to vary during the 6.25s interval before and after the rising and falling edges of
CLOCK input.
1-4.[RESETB (System-wide reset)]
The reset signal is formed by the power-on reset function built into the HIC and the RESETB terminal.
When activating the internal circuits of the HIC using the power-on reset signal within the HIC, be sure to connect Pin
14 of the HIC to V
.
DD
1-5. [ENABLE (Forcible OFF control of excitation drive output A, AB, B, and BB, and selecting operation/hold status
inside the HIC)]
ENABLE=1: Normal operation
When ENABLE=0: Motor current goes OFF, and excitation drive output is forcibly turned OFF.
The system clock inside the HIC stops at this time, with no effect on the HIC even if input pins other than RESET input
vary. In addition, since current does not flow to the motor, the motor shaft becomes free.
If the CLOCK signal used for motor rotation suddenly stops, the motor shaft may advance beyond the control position
due to inertia. A SLOW DOWN setting where the CLOCK cycle gradually decreases is required in order to stop at the
control position.
No.2317-14/31
STK672-640CN-E
1-6. [FAULT1]
FAULT1 is an open drain output. It outputs low level when any of motor terminal open, overcurrent, or overheat is
detected.
1-7. [FAULT2]
Output is resistance divided (3 levels) and the type of abnormality detected is converted to the corresponding output
voltage.
Motor terminal open: 10mV (typ)
Overcurrent: 2.5V (typ)
Overheat: 3.3V (typ)
Abnormality detection can be released by a RESETB operation or turning V
voltage on/off.
DD
1-8. [VrefOP]
To set the motor current detection circuit operates when pin is open, to monitor the reference voltage VrefOP terminal.
It is also possible to set any detectable current by connecting an external pull-up resistor to 5V supply.
<I d by setting pull-up resistor current sensing pin 7 open>
OH
When 7 pins open, VrefOP (typ) is 98mV. In this case, detection current I d is expressed as follows.
OH
VefOP = I d × Rs (Rs: Current detection resistor)
OH
Detection current is 0.7A for the STK672-630CN-E, 1.1A for the STK672-640CN-E motor drivers.
Note: Detective current IOHdX is greatly set when used 5V pulling up resistance.
Reference voltage VrefOPX is calculated as above.Pull-up resistor Rdx by pin 7 is calculated as follows.
RdX = (180 × RTX) ÷ (180 - RTX)
RTX = (5.0V - VrefOPX) ÷ ((1.0588 × VrefOPX) - 0.0765) (RdX and RTX unit is kΩ)
*To disable pin open detection, please connect a 5V pull-up resistor of 10k to 15kΩ.
1-9.[Vref (Voltage setting to be used for the current setting reference)]
Input voltage is in the voltage range of 0.14V to 1.31V.
The recommended Vref voltage is 0.14V or higher because the output offset voltage of Vref/4.9 amplifier cannot be
controlled down to 0V.
Note:Pin type is analog input configuration.
1-10. [Input timing]
The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations
when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate
voltage is 5V5%, conduction of current to output at the time of power on reset adds electromotive stress to the
MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while V
which is outside the operating supply voltage, is less than 4.75V.
,
DD
In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10s until CLOCK
input.
4Vtyp
3.8Vtyp
Control IC power (V ) rising edge
DD
Control IC power on reset
RESETB signal input
ENABLE signal input
No time specification
CLOCK signal input
At least 10s
At least 10s
ENABLE, CLOCK, and RESETB Signals Input Timing
No.2317-15/31
STK672-640CN-E
1-11. [Configuration of control block I/O pins]
<Configuration of the MODE1, MODE2, CLOCK,
CWB, ENABLE, and RESETB input pins>
Input pins 10,12,13,14,15,17pin
<Configuration of the FAULT2 pin>
VDD
50k
VDD
Output pin
Pin 8
10kΩ
Motor terminal open
50k
Overcurrent
50k
Input pin
100kΩ
VSS
Overheating
(The buffer has an open drain configuration.)
The input pins of this driver all use Schmitt input. Typical specifications at Tc=25C are given below. Hysteresis
voltage is 0.3V (VIHa-VILa).
When rising
When falling
1.8Vtyp
1.5Vtyp
Input voltage
VIHa
VILa
Input voltage specifications are as follows.
V
V
=2.5Vmin
IH
=0.8Vmax
IL
<Configuration of the Vref input pin>
<Configuration of the FAULT output pin>
VDD
Output pin
Pin16
Vref/4.9
Motor terminal open
Overcurrent
Amplifier
Overheating
Inputpin
Pin19
VSS
VSS
<Configuration of the VrefOP output pin>
VDD
1.3V
180k
17k
Output pin
Pin 7
-
To opened motor pin
detection circuit
1k
+
V
SS
No.2317-16/31
STK672-640CN-E
2. Overcurrent detection, overheat detection, and motor terminal open functions
Each detection function operates using a latch system and turns output off. Because a RESET signal is required to
restore output operations, once the power supply, V , is turned off, you must either again apply power on reset with
DD
V
ON or apply a RESETB=HighLowHigh signal.
DD
2-1.[Motor terminal open detection]
This hybrid IC is equipped with a function for detecting open output terminals to prevent thermal destruction of the
MOSFET due to repeated avalanche operation that occurs when an output terminal connected to the motor is open.
The open condition is determined by checking the presence or absence of the flyback current that flows in the motor
inductance during the off period of the PWM cycle.
Detection is performed by using the fact that the flyback current does not flow when a motor terminal is open.
Terminal open
Used to see the motor current
Current
detection
resistor voltage
0V (GND potential)
Used for open detection
(Negative current does not flow
when the terminal is open.)
MOSFET gate signal
PWM period
When the current level drops, the difference with the GND potential decreases, making detection difficult.
The motor current that can be detected by motor terminal open detection is 0.7A for the STK672-630CN-E, 1.1A for
the STK672-640CN-E motor drivers
<Notes on the ENABLE high edge>
When ENABLE changes from low to high and the STK672-6xxCN-E performs constant-current PWM operation that
flows a negative current during the 30s period after the high edge, open detection may activate and stop the driver.
The motor current setting voltage Vref must be set so that PWM operation is not performed within a period of 30s
after the high edge.
If the motor current setup voltage is set for the rated motor current, PWM operation is not performed during this 30s
period after the high edge, so this is not a problem.
In addition, there is no problem with operation that lowers the current setting Vref after the motor rated current is
reached as shown in the diagram on the following page.
Whether constant-current PWM operation is performed during the 30s period after the high edge can be judged by
substituting the motor L and R values into the formula on the following page.
Vref= (R02 ÷ (R01+R02)) × 5V (or 3.3V)
I
I
1= (Vref ÷ 4.9) ÷ Rs
I
I
1: Motor current value to be set
2: Current value 30s after the ENABLE high edge
OH
OH
OH
OH
2= (V
÷ R) × (1-e-tR/L
)
CC
Judgment standard: I 1I
OH OH
2
R01, R02, 5V (or 3.3V): See the Sample Application Circuit documents.
Rs: Current detection resistance value ()
V
: Motor supply voltage (V)
CC
R: Motor winding resistance ()
L: Motor winding inductance (H)
There is no problem if the I 2 obtained by substituting t = 30s and the motor L and R values is smaller than
OH
the current setting value I 1.
OH
No.2317-17/31
STK672-640CN-E
ENABLE
Vref
Output current
Constant-current PWM operation must not be performed for 30 µs or less.
<Connection of capacitors between output pins and GND prohibited>
Capacitors must not be connected between the phase A (pin 4), phase AB (pin 5), phase B (pin 3) and phase BB (pin
1) outputs and GND. What happens if capacitors are connected is that open-circuit detection may be triggered by the
discharge current of the capacitors when the internal MOSFET is set ON. This current is not an inductance current
generated by the motor winding but a capacitor current so a negative current will not flow to the other phase in each
pair of phases, possibly causing the driver to shut down.
<Excessive external noise>
If, when the motor current rises prior to the PWM operation, a spike-shaped current exceeding the Vref-setting
current is generated by excessive external noise, for instance, before the current level (0.7A for the STK672-630CN-E,
1.1A for the STK672-640CN-E motor drivers) at which motor pin open-circuiting can be detected is reached, the
internal MOSFET is set OFF.
Since the MOSFET has been set OFF before the actual motor current reaches 0.7A (or 1.1A), the level of the negative
current subsequently flowing to the other phase in each pair of phases is low, and it may be judged that no negative
current is flowing, possibly causing open-circuit detection to be triggered.
During normal constant-current PWM operation, the duration of 5.5s, which is equivalent to 25% of the initial
operation in the PWM period, corresponds to the section where the current is not detected, and this ensures that no
current is detected for the linking part of the current that is generated in this section. The no-current detection section
is not synchronized at the current rise prior to the PWM operation so when a spike-shaped current exceeding the
Vref-setting current is generated, the MOSFET is set OFF at the stage where the level of the actual motor current is
low. As a result, the level of the negative current subsequently flowing to the other phase in each pair of phases is low,
and it may be judged that no negative current is flowing, possibly causing open-circuit detection to be triggered.
Spike-shaped current
Vref setting
current (I
)
OH
Motor
current
Current level at
which
open-circuiting is
detected
No-current detection time (5.5s typ)
PWM period
No.2317-18/31
STK672-640CN-E
2-2.[Overcurrent detection]
This hybrid IC is equipped with a function for detecting overcurrent that arises when the motor burns out or when there
is a short between the motor terminals.
Overcurrent detection occurs at 3.5A typ with the STK672-630CN-E, and 5.5A typ with the STK672-640CN-E.
Current when motor terminals are shorted
PWM period
Overcurrent detection
max
I
OH
Set motor
current, I
MOSFET all OFF
OH
No detection interval
(5.5s typ)
5.5s typ
Operation when motor pins are shorted
Normal operation
Overcurrent detection begins after an interval of no detection (a dead time of 5.5s typ) during the initial ringing part
during PWM operations. The no detection interval is a period of time where overcurrent is not detected even if the
current exceeds I
.
OH
2-3. [Overheat detection]
Rather than directly detecting the temperature of the semiconductor device, overheat detection detects the temperature
of the aluminum substrate (144C typ).
Within the allowed operating range recommended in the specification manual, if a heat sink attached for the purpose of
reducing the operating substrate temperature, Tc, comes loose, the semiconductor can operate without breaking.
However, we cannot guarantee operations without breaking in the case of operations other than those recommended,
such as operations at a current exceeding I
max that occurs before overcurrent detection is activated.
OH
No.2317-19/31
STK672-640CN-E
3. Allowable Avalanche Energy Value
(1) Allowable Range in Avalanche Mode
When driving a 2-phase Stepper motor with constant current chopping using an STK672-6** Series hybrid IC, the
waveforms shown in Figure 1 below result for the output current, I , and voltage, V
.
DS
D
VDSS: Voltage during avalanche operations
I
: Motor current peak value
OH
IAVL: Current during avalanche operations
tAVL: Time of avalanche operations
Figure 1 Output Current, I , and Voltage, V , Waveforms 1 of the STK672-6** Series when Driving a
D
DS
2-Phase Motor with Constant Current Chopping
When operations of the MOSFET built into STK672-6** Series ICs is turned off for constant current chopping, the I
D
signal falls like the waveform shown in the figure above. At this time, the output voltage, V , suddenly rises due to
DS
electromagnetic induction generated by the motor coil.
In the case of voltage that rises suddenly, voltage is restricted by the MOSFET V
DSS
. Voltage restriction by V
DSS
results in a MOSFET avalanche. During avalanche operations, I flows and the instantaneous energy at this time, EAVL1,
D
is represented by Equation (3-1).
EAVL1=V
IAVL0.5tAVL ------------------------------------------- (3-1)
: V units, IAVL: A units, tAVL: sec units
DSS
V
DSS
The coefficient 0.5 in Equation (3-1) is a constant required to convert the IAVL triangle wave to a square wave.
During STK672-6** Series operations, the waveforms in the figure above repeat due to the constant current chopping
operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (3-2) used to find the average
power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (3-1).
PAVL=V
IAVL0.5tAVLfc ------------------------------------------- (3-2)
DSS
fc: Hz units (fc is set to the PWM frequency of 50kHz.)
For V
DSS
, IAVL, and tAVL, be sure to actually operate the STK672-6** Series and substitute values when operations
are observed using an oscilloscope.
Ex. If V =110V, IAVL=1A, tAVL=0.2s, the result is:
DSS
PAVL=11010.50.210-650103=0.55W
=110V is a value actually measured using an oscilloscope.
V
DSS
The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3.
When examining the avalanche energy, be sure to actually drive a motor and observe the I , V , and tAVL waveforms
D
DSS
during operation, and then check that the result of calculating Equation (3-2) falls within the allowable range for
avalanche operations.
No.2317-20/31
STK672-640CN-E
(2) I
V
Operating Waveforms in Non-avalanche Mode
D and DSS
Although the waveforms during avalanche mode are given in Figure 1, sometimes an avalanche does not result during
actual operations.
Factors causing avalanche are listed below.
Poor coupling of the motor’s phase coils (electromagnetic coupling of A phase and AB phase, B phase and BB phase).
Increase in the lead inductance of the harness caused by the circuit pattern of the board and motor.
Increases in V
, tAVL, and IAVL in Figure 1 due to an increase in the supply voltage from 24V to 36V.
DSS
If the factors above are negligible, the waveforms shown in Figure 1 become waveforms without avalanche as shown
in Figure 2.
Under operations shown in Figure 2, avalanche does not occur and there is no need to consider the allowable loss
range of PAVL shown in Figure 3.
I
: Motor current peak value
OH
Figure 2 Output Current, I , and Voltage, V , Waveforms 2 of the STK672-6** Series when Driving
DS
D
a 2-Phase Stepper Motor with Constant Current Chopping
Figure 3 Allowable Loss Range, PAVL-I
During STK672-640CN-E Avalanche Operations
OH
PAVL-IOH
5
4.5
4
3.5
3
Tc=105°C
Tc=80°C
2.5
2
1.5
1
0.5
0
0
1
2
3
4
Motor current, IOH A
Note :
The operating conditions given above represent a loss when driving a 2-phase stepper motor with constant current
chopping.
Because it is possible to apply 3.0W or more at I =0A, be sure to avoid using the MOSFET body diode that is used to
OH
drive the motor as a zener diode.
No.2317-21/31
STK672-640CN-E
4. Calculating STK672-640CN-E HIC Internal Power Loss
The average internal power loss in each excitation mode of the STK672-640CN-E can be calculated from the following
formulas. *1
Each excitation mode
2-phase excitation mode
2PdAVex=(Vsat+Vdf) 0.5CLOCKI t2+0.5CLOCKI (Vsatt1+Vdft3)
OH OH
1-2 Phase excitation mode
1-2PdAVex=(Vsat+Vdf) 0.25CLOCKI t2+0.25CLOCKI (Vsatt1+Vdft3)
OH OH
Motor hold mode
HoldPdAVex= (Vsat+Vdf) I
OH
Vsat : Combined voltage represented by the Ron voltage drop+shunt resistor
Vdf : Combined voltage represented by the MOSFET body diode+shunt resistor
CLOCK: Input CLOCK (CLOCK pin signal frequency)
*1
t1, t2, and t3 represent the waveforms shown in the figure below.
t1 : Time required for the winding current to reach the set current (I
t2 : Time in the constant current control (PWM) region
)
OH
t3 : Time from end of phase input signal until inverse current regeneration is complete
IOH
0 A
t1
t2
t3
Motor COM Current Waveform Model
t1= (-L/(R+0.20)) ln (1-(((R+0.20)/V ) I ))
CC OH
t3= (-L/R) ln ((V +0.20)/(I R+V +0.20))
CC OH CC
: Motor supply voltage (V)
: Motor inductance (H)
V
L
R
CC
: Motor winding resistance ()
I
: Motor set output current crest value (A)
OH
Relationship of CLOCK, t1, t2, and t3 in each excitation mode
2-phase excitation mode : t2= (2/CLOCK) - (t1+t3)
1-2 phase excitation mode : t2= (3/CLOCK) -t1
For the values of Vsat and Vdf, be sure to substitute from Vsat vs I
(See pages to follow)
and Vdf vs I
at the setting current value I .
OH
OH
OH
Then, determine if a heat sink is necessary by comparing with the Tc vs Pd graph (see next page) based on the
calculated average output loss, HIC.
For heat sink design, be sure to see ‘5. Thermal Design’.
The HIC average power, PdAVex described above, represents loss when not in avalanche mode.
To add the loss in avalanche mode, be sure to add PAVL using the formula (for average power loss , PAVL, for
STK672-6** during avalanche mode, described below to PdAVex described above.)
When using this IC without a fin, always check for temperature increases in the set, because the HIC substrate
temperature, Tc, varies due to effects of convection around the HIC.
No.2317-22/31
STK672-640CN-E
4-2. [Calculating the average power loss, PAVL, during avalanche mode]
The allowable avalanche energy, EAVL, during fixed current chopping operation is represented by Equation (3-2) used
to find the average power loss, PAVL, during avalanche mode that is calculated by multiplying Equation (3-1) by the
chopping frequency.
PAVL=V IAVL0.5tAVLfc ············································································· (3-2)
DSS
fc : Hz units (fc is set to the PWM frequency of 50kHz.)
Be sure to actually operate an STK672-6** series and substitute values found when observing operations on an
oscilloscope for V , IAVL, and tAVL.
DSS
The sum of PAVL values for each excitation mode is multiplied by the constants given below and added to the average
internal HIC loss equation, except in the case of 2-phase excitation.
1-2 excitation mode and higher: PAVL(1)=0.7PAVL························································(4-1)
During2-phase excitation mode and motor hold: PAVL(1)=1PAVL·······································(4-2)
No.2317-23/31
STK672-640CN-E
No.2317-24/31
STK672-640CN-E
5. Thermal design
[Operating range in which a heat sink is not used]
Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the
quality of the HIC.
The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the HIC.
The value of PdAV increases as the output current increases. To calculate PdAV, refer to “Calculating Internal HIC
Loss” in the specification document.
Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since
conduction during motor rotation and off time both exist during actual motor operations,
IO1
Motor phase current
(sink side)
IO2
0 A
-IO1
T1
T3
T2
T0
Figure 1 Motor Current Timing
T1 : Motor rotation operation time
T2 : Motor hold operation time
T3 : Motor current off time
T2 may be reduced, depending on the application.
T0 : Single repeated motor operating cycle
I 1 and I 2 : Motor current peak values
O
O
Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form.
Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ.
The hybrid IC internal average power dissipation PdAV can be calculated from the following formula.
PdAV= (T1P1+T2P2+T30) TO ---------------------------- (I)
(Here, P1 is the PdAV for I 1 and P2 is the PdAV for I 2)
O
O
If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60C or less, there is no
need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used.
[Operating range in which a heat sink is used]
Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of
c-a in Equation (II) below and the graph depicted in Figure 3.
c-a= (Tc max-Ta) PdAV ---------------------------- (II)
Tc max : Maximum operating substrate temperature =105C
Ta: HIC ambient temperature
Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and
confirm that the substrate temperature, Tc, is 105C or less.
The average HIC power loss, PdAV, described above represents the power loss when there is no avalanche operation.
To add the loss during avalanche operations, be sure to add Equation (3-2), “Allowable STK672-6** Avalanche
Energy Value”, to PdAV.
No.2317-25/31
STK672-640CN-E
Figure 2
Figure 3
No.2317-26/31
STK672-640CN-E
6. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta
Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink.
The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta.
Power loss of up to 3.1W is allowable at Ta=25C, and of up to 1.75W at Ta=60C.
* The package thermal resistance θc-a is 25.8°C/W.
No.2317-27/31
STK672-640CN-E
7. Example of Stepper Motor Driver Output Current Path (1-2 phase excitation)
2-phase stepper motor
I A
O
I AB
O
FAULT2 VrefOP
A
AB
F2
B
BB
8
7
4
5
3
1
V
=5V
9
DD
V
DD
F1
F3
F4
Excitatin
mode setting
MODE1 10
N.C 11
FAO
Phase
FAB
FBO
V
excitation
signal
CC
MODE2 17
Phase
advnce
counter
24V
generation
CLOCK
CWB
12
13
FBB
Opened
motor pin
detection
Latch
Latch
R2
R1
Power
on
reset
C02
14
RESETB
Over
current
detection
at least 100F
P.G2
ENABLE 15
FAULT1 16
2
AI
BI
Chopper
circuit
FAULT1,
FAULT2
signal
P.GND
P.G1
6
Vref/4.9
Vref
Over heat
detection
Latch
Amp
SS
V
V
SS
18
19
N.C
Vref
CLOCK
Phase A output
current
I A
O
PWM operations
When PWM operations of I
A
O
are OFF, for I AB, negative
O
Phase AB output
current
current flows through the
parasitic diode, F2.
I AB
O
When PWM operations of I AB
O
are OFF, for I A, negative
O
current flows through the
parasitic diode, F1.
No.2317-28/31
STK672-640CN-E
8. Other usage notes
In addition to the “Notes” indicated in the Sample Application Circuit, care should also be given to the following
contents during use.
(1) Allowable operating range
Operation of this product assumes use within the allowable operating range. If a supply voltage or an input voltage
outside the allowable operating range is applied, an overvoltage may damage the internal control IC or the
MOSFET.
If a voltage application mode that exceeds the allowable operating range is anticipated, connect a fuse or take other
measures to cut off power supply to the product.
(2) Input pins
If the input pins are connected directly to the board connectors, electrostatic discharge or other overvoltage outside
the specified range may be applied from the connectors and may damage the product. Current generated by this
overvoltage can be suppressed to effectively prevent damage by inserting 100 to 1k resistors in lines connected
to the input pins.
Take measures such as inserting resistors in lines connected to the input pins.
(3) Power connectors
If the motor power supply V
is applied by mistake without connecting the GND part of the power connector
when the product is operated, such as for test purposes, an overcurrent flows through the V decoupling capacitor,
CC
CC
of the internal control IC and GND, and may damage the power supply
C1, to the parasitic diode between the V
pin block of the internal control IC.
DD
To prevent damage in this case, connect a 10 resistor to the V
pin, or insert a diode between the V
CC
DD
decoupling capacitor C1 GND and the V
pin.
DD
Overcurrent protection measure: insert a resistor
VDD=5V
A
AB
BB
FAULT2 VrefOP
B
3
1
4
5
5V
Reg.
.
9
VDD
FAO
FABO
FBO
MODE1
CLOCK
Vcc
FBBO
CWB
24V
Reg
.
RESETB
R2
R1
C1
GND
2
ENABLE
MODE2
MODE3
A1
B1
6
Vref
FAULT1
Vref
VSS
S.G
18
open
Overcurrent protection measure: insert a diode
Overcurrent path
(4) Input Signal Lines
1) Do not use an IC socket to mount the driver, and instead solder the driver directly to the board to minimize
fluctuations in the GND potential due to the influence of the resistance component and inductance component of
the GND pattern wiring.
2) To reduce noise caused by electromagnetic induction to small signal lines, do not design small signal lines (sensor
signal lines, and 5V or 3.3V power supply signal lines) that run parallel in close proximity to the motor output line
A (Pin 4), AB (Pin 5), B (Pin 3), or BB (Pin 1) phases.
No.2317-29/31
STK672-640CN-E
(5) When mounting multiple drivers on a single board
When mounting multiple drivers on a single board, the GND design should mount a V
decoupling capacitor, C1, for
CC
each driver to stabilize the GND potential of the other drivers. The key wiring points are as follows.
24v
5V
9
9
9
Motor
3
Motor
1
Motor
2
Input
Signals
Input
Signals
Input
Signals
IC1
IC2
IC3
2
6
2
6
2
6
18
18
18
19
19
19
GND
GND
Thick and short
Short
Thick
(6) V
operating limit
CC
When the output (for example F1) of a 2-phase stepper motor driver is turned OFF, the AB phase back electromotive
force eab produced by current flowing to the paired F2 parasitic diode is induced in the F1 side, causing the output
voltage VFB to become twice or more the V
voltage. This is expressed by the following formula.
CC
VFB = V
+ eab
CC
CC
= V
+ V
+ I
x RM + Vdf (1.5V)
CC OH
V
: Motor supply voltage, I : Motor current set by Vref
CC OH
Vdf: Voltage drop due to F2 parasitic diode and current detection resistor R1, RM: Motor winding resistance value
Using the above formula, make sure that VFB is always less than the MOSFET withstand voltage of 100V. This is
because there is a possibility that operating limit of V
falls below the allowable operating range of 46V, due to the
CC
RM and I
OH
specifications.
V
CC
V
CC
AB phase
eab
A phase
AB phase
A phase
eab is generated by the
mutual induction M.
Current path
Current path
VFB
eab
CC
M
M
V
F2
F2
OFF
OFF
F1
OFF
F1
ON
R1
GND
R1
GND
The oscillating voltage in excess of VFB is caused by LCRM (inductance, capacitor, resistor, mutual inductance)
oscillation that includes micro capacitors C, not present in the circuit. Since M is affected by the motor characteristics,
there is some difference in oscillating voltage according to the motor specifications. In addition, constant voltage drive
without constant current drive enables motor rotation at V
CC
0V.
No.2317-30/31
STK672-640CN-E
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
15 / Tube
SIP-19
(Pb-Free)
STK672-640CN-E
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PS No.2317-31/31
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