TPS2399DMT7G [ONSEMI]
热插拔控制器，带启用，-48 V;
| 型号： | TPS2399DMT7G |
| 厂家： | 
ONSEMI |
| 描述： | 热插拔控制器，带启用，-48 V 控制器 开关 光电二极管 |
| 文件： | 总15页 (文件大小：660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2398, TPS2399
-48 V Hot Swap Controller
for Redundant Supply
Systems
The TPS2398 and TPS2399 integrated circuits are hot swap power
managers optimized for use in nominal −48 V systems. They
incorporate an improved circuit breaker response that provides rapid
protection from short circuits, while still enabling plug−ins to tolerate
large transients that can be generated by the sudden switchover to a
higher voltage supply. They are designed for supply voltage ranges up
to −80 V, and are rated to withstand spikes to −100 V. In conjunction
with an external N−channel FET and sense resistor, they can be used to
enable live insertion of plug−in cards and modules in power
systems. Both devices provide load current slew rate and eak
magnitude limiting, easily programmed by sense resistor valand a
single external capacitor.
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MSOP−8
Z SUFFIX
CASE 846AD
PIN CONNECTIONS AND
MARKING DIAGRAM
Features
1
• Wide Input Supply: −36 V to −80 V
• Transient Rating to −100 V
• Improved Transient Response
• Εnable Input (EN)
RTN
PG
EN
FLTTIME
IRAMP
GATE
ISENS
−VIN
• Programmable Current Limit
• Programmable Current Slew Re
• Fault Timer to Eliminate Nuisance Trips
• Open−Drain Power Gout (PG
• MSOP−8 Package
(Top View)
239x
= Specific Device Code
x = 8 or 9
= Assembly Location
= Year
= Work Week
= Pb−Free Package
A
Y
W
G
• These are Pb−FreDevice
(Note: Microdot may be in either location)
Typical Applic
• −48 V DistribSystems
• Redundant NegatiVoltage Supplies
• Central Office Switching Systems
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of
this data sheet.
DC/DC
−48V
RTN
VIN+
VOUT+
VOUT+
C3
1V
100 mF
R3
33 kW
C4
EN
R2
100 kW
VIN−
VOUT−
VOUT−
TPS2398/99
1
2
3
4
8
7
6
5
RTN
PG
EN
Q1
NTD6414AN
GATE
FLTTIME ISENS
IRAMP −VIN
C1
47 nF
R1
0.02 W
−48V
IN−A
C2
3.9 nF
−48V
IN−B
Figure 1. Application Diagram
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
August, 2017 − Rev. 0
TPS2398/D
TPS2398, TPS2399
−48V
RTN
VOUT+
RTN
REG
VDDs
8
2
R3
R1
100 kW
30 V
Enabled
1.4 V
EN
PG
1
Priority:
R
Logic
GateHi
SET
S
Q
Q
C3
100 V
100 mF
RampHi
Fault
Enabled
Logic
CLR
R
Enabled
10 uA
0.6 uA
OL
IRAMP
7.5V
OC
4
Slow/Fast
RaHi
GateHi
0.5 V
RSE
99 R
Overcurrent
comparator
4.5 V
VOUT−
Linear current
amplifier (LCA)
R
40mV
Q1
NTD6414
GATE
7
6
Faul
EN
C1
47 nF
Enabled
OC
RSE
Slow/Fast
Fault
Enabled
50 uA
ISNS
.0 V
.5 V
SET
CLR
S
R
Q
Q
FLTTIME
Fault
3
OL
4us
0.4 uA
R1
0.02 W
100mV
C2
3.9 nF
Overload
comparator
−VIN
5
TPS2398 − Log0
TPS2399 − Log1
Enabled
−48V
IN
Figure 2. Internal Block Diagram
Table 1. PIN FUNCTION DESCRIPTIN
Pin Number
Pin Name
EN
Description
Enble input to turn on/off power to the load
2
1
3
7
4
6
8
5
PG
Open−drain, active−low indication of a load power good condition.
Connection for user−programming of the fault timeout period.
Gate drive for external N−channel FET
FLTTIME
GATE
IRAMP
ISENS
RTN
Programming input for setting the inrush current slew rate.
Current sense input.
Positive supply input for the TPS2398 and TPS2399.
−VIN
Negative supply input and reference pin for the TPS2398 and TPS2399.
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2
TPS2398, TPS2399
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 15
−0.3 to 100
−0.3 to 100
−0.3 to 100
10
Unit
V
Input voltage range, all pins except RTN, EN, PG (Note 1)
Input voltage range, RTN (Note 1)
RTN
EN
V
Input voltage range, EN (Notes 1, 2)
Output voltage range, PG (Notes 1, 3)
Continuous output current, PG
V
PG
V
I
mA
mW
°C
°C
°C
kV
kV
PG
Continuous total power dissipation, T < 25
P
420
A
D(MAX)
Operating junction temperature range
T
−40 to 125
−55 to 150
260
J(MAX)
Storage temperature range
T
T
STG
Lead temperature soldering 1.6 mm (1/16 inch) from case for 10 seconds
Human Body Model (HBM) (Note 4)
OL
D
ESD
2.0
HM
Charged Device Model (CDM) (Note 4)
1.5
M
Stresses exceeding those listed in the Maximum Ratings table may damage tdee. If any of hese limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INORMATION foafe Operating Area.
2. With 100−kW minimum input series resistance, −0.3 V to 15 V witow imedance.
3. With 10−kW minimum input series resistance, −0.3 V to 80 V with w ipedance.
4. All pins except RTN pin which is specified up to 1.0 kV.
Table 3. RECOMMENDED OPERATING CONDITINS
Rating
Min
−80
−40
Nom
Max
−36
85
Unit
V
Nominal input supply, −VIN to RTN
Operating ambient temperature
°C
Functional operation above the stresses tein the ended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges mits may affect device reliability.
Table 4. DISSIPATION RATING TABLE
Package
T
< 255C
Deratig Factor
T
< 855C
A
A
MSOP−8
420 mW
4.3 mW/°C
160 mW
Table 5. ELECHARCTERISTICS
V
= −48 V RTN, V
= 2.8 V, V
= 0 V, all outputs unloaded, device not in fault mode, T = 25°C; unless
I(−VIN)
I(EN)
I(ISENS) J
otherwise noted. Max specifications are guaranteed at −40°C ≤ T ≤ 85°C. (Notes 5, 6)
J
Param
INPUT SUPPLY
Test Conditions
Symbol
Min
Typ
Max
Unit
Supply current, RTN
V
V
= 48 V
= 80 V
I
310
310
−30
2.3
450
450
−25
3.0
mA
mA
V
I(RTN)
CC
I(RT
UVLO threshold, input voltage rising
UVLO hysteresis
To GATE pull−up, referenced to RTN
V
−36
UVLO_L
V
HYS
1.8
V
ENABLE INPUT (EN)
Threshold voltage, input voltage rising
EN hysteresis
To GATE pull−up
V
1.25 1.35
1.5
90
2
V
TH
V
20
40
1
mV
mA
HYS_EN
High−level input current
LINEAR CURRENT AMPLIFIER (LCA)
High−level output, GATE
Output sink current
V
I(EN)
= 5 V
I
IH
−2
V
V
= 0 V
V
OH
11
50
−1
14
17
1
V
I(ISENS)
= 80 mV, V
= 5 V, Fault mode
I
100
mA
mA
I(ISENS)
O(GATE)
SINK
Input current, ISENS
0 V < V
< 0.2 V
I
I
I(ISENS)
5. All voltages are with respect to the −VIN terminal unless otherwise stated.
6. Currents are positive into and negative out of the specified terminal.
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3
TPS2398, TPS2399
Table 5. ELECTRICAL CHARACTERISTICS
V
= −48 V with respect to RTN, V
= 2.8 V, V
= 0 V, all outputs unloaded, device not in fault mode, T = 25°C; unless
I(−VIN)
I(EN)
I(ISENS) J
otherwise noted. The Min and Max specifications are guaranteed at −40°C ≤ T ≤ 85°C. (Notes 5, 6)
J
Parameter
LINEAR CURRENT AMPLIFIER (LCA)
Reference clamp voltage
Test Conditions
Symbol
Min
Typ
Max
Unit
V
V
= open
V
REF_K
33
40
46
6
mV
mV
O(IRAMP)
Input offset voltage
= 2 V
V
IO
−7
O(IRAMP)
RAMP GENERATOR
IRAMP source current, slow turn−on rate
IRAMP source current, normal rate
Low−level output voltage
V
V
V
V
= 0.25 V
I
I
−850 −600 −400
nA
mA
O(IRAMP)
SRC1
= 1 V, 3 V
−11
−10
−9
5
O(IRAMP)
SRC2
= 0 V
V
OL
mV
I(EN)
Voltage gain, relative to ISENS
OVERLOAD COMPARATOR
Current overload threshold, ISENS
Glitch filter delay time
= 1 V, 3 V
A
V
9.5
10
10.5
mV/V
O(IRAMP)
TH_OL
80
2
100
4
120
7
mV
V
= 200 mV
t
ms
I(ISENS)
DLY
FAULT TIMER
Low−level output voltage
V
V
= 0 V
V
5
mV
mA
V
I(EN)
OL
Charging current, current limit mode
Fault threshold voltage
= 80 mV, V
= 2
I
CHG
−55
−50
−45
4.25
I(ISENS)
O(FLTE)
O(FLTTE)
V
FLT
3.75
4.0
Discharge current, retry mode (TPS2399)
Output duty cycle (TPS2399)
Discharge current, timer reset mode
PG OUTPUT
V
V
V
= 80 mV
= 2 V, Fault Mode
I
0.38 0.75
mA
%
I(ISENS)
DSG
D
0.8
1
1.5
I
mA
O(
R
High−level output (leakage) current
Driver ON resistance
= 0 V, V
= 65 V
I
10
80
mA
O(PG)
OH
I
1 mA
R
35
W
O(PG
DS(ON)
5. All voltages are with respe −VIN inal unless otherwise staed.
6. Currents are positive ine out of the specified terminal.
Product parametric performanted in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may noicatee Electrical Charteristics if operated under different conditions.
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4
TPS2398, TPS2399
TYPICAL CHARACTERISTICS
V
I(−VIN)
= −48 V with respect to RTN, V
= 2.8 V, V = 0 V, all outputs unloaded, device not in fault mode, T = 25°C
I(ISENS) J
I(EN)
V
EN
(20 V/div)
V
EN
(20 V/div)
V
DRAIN
(20 V/div)
V
DRAIN
(50 V/div)
I
RTN
C
C
C
= 3.9 nF
= 100 nF
= 50 mF
C
C
C
= 3.9 nF
= 100 nF
= 100 mF
IRAMP
IRAMP
FLTTM
(500 mA/div)
FLTTM
OUT
OUT
I
RTN
(500 mA/div)
1 ms/div
1 ms/div
Figure 3. Live Insertion Event, VIN = −48 V
Figure 4ive Insertion Event, VIN = −80 V
C
C
= 47 nF
= 330 mF
C
= 3.9 nF
C
= 47 nF
IRAMP
FLTTM
IRAMP
V
EN
(5 V/div)
C
22 nF
OUT
IRAM
V
DRAIN
(50 V/)
V
IRP
(2 V/div)
C
= 100 mF
OUT
V
I
iv)
I
RTN
(500 mAiv)
I
(500 mA/div)
RTN
10 ms/div
Figurup frm Enable, VIN = −80 V
Figure 6. Output Current Ramp Profiles
V
/PG
(50 V/div)
V
/PG
(50 V/div)
C
C
= 3.9 nF
= 47 nF
C
C
= 3.9 nF
= 47 nF
IRAMP
FLTTM
IRAMP
FLTTM
V
V
IRAMP
IRAMP
(2 V/div)
(2 V/div)
V
FLTTM
V
FLTTM
(2 V/div)
(2 V/div)
I
I
RTN
RTN
(1 A/div)
(1 A/div)
1 ms/div
1 ms/div
Figure 7. Turn−On into Short (TPS2399 only)
Figure 8. Turn−On into Short (TPS2398 only)
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5
TPS2398, TPS2399
TYPICAL CHARACTERISTICS
V
I(−VIN)
= −48 V with respect to RTN, V
= 2.8 V, V
= 0 V, all outputs unloaded, device not in fault mode, T = 25°C
I(EN)
I(ISENS)
J
V
/PG
(50 V/div)
V
/PG
(50 V/div)
V
FLTTM
V
FLTTM
(2 V/div)
(2 V/div)
V
DRAIN
C
C
C
R
= 3.9 nF
= 47 nF
= 100 mF
= 12.5 W
V
IRAMP
FLTTM
C
C
C
R
= 3.9 nF
= 47 nF
= 100 mF
(20 V/div)
DRAIN
IRAMP
FLTTM
(20 V/div)
OUT
LOAD
OUT
I
I
RTN
RTN
= 12.5 W (unconnected)
LOAD
(1 A/div)
(1 A/div)
50 ms/div
50 ms/div
Figure 9. Fault−Retry Operation
Fig10. Recovery from a Fault
(TPS2399 only)
(TPS2399 only)
V
/PG
C
C
C
= 3.9 nF
= 100 nF
= 100 mF
IRAMP
FLTTM
V
IRAMP
(2 V/div)
(50 V/div)
OUT
V
FLT
V/div
V
DRAIN
(20 V/div)
AIN
C
C
C
= 3.9 nF
= 47 nF
= 100 mF
IRAMP
FLTTM
(20 V/div)
OUT
I
RTN
V
/PG
(50 V/div)
(1 A/div)
1 ms/div
Figure ery fom a Fault − Expande
Figure 12. PG Ouput Timing − Voltage
(TPS2399 only)
Qualified
1200
1000
800
C
C
C
= 3.9 nF
= 100 nF
= 100 mF
IRAMP
FLTTM
.5 V
OUT
V
IRAMP
(2 V/div)
V
V
= 80 V
= 48 V
600
RTN
V
(20 V/div)
DRAIN
400
200
0
V
(50 V/div)
/PG
RTN
−40
−20
0
20
40
60
80
1 ms/div
TEMPERATURE (°C)
Figure 13. PG Ouput Timing − Current
Figure 14. Supply Current
Qualified
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TPS2398, TPS2399
TYPICAL CHARACTERISTICS
V
I(−VIN)
= −48 V with respect to RTN, V
= 2.8 V, V
= 0 V, all outputs unloaded, device not in fault mode, T = 25°C
I(EN)
I(ISENS)
J
15.0
45
43
41
39
37
14.8
14.6
14.4
14.2
14.0
13.8
13.6
13.4
35
33
13.2
13.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
0
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. GATE High Output Voltage
Figure 16. Reference Clamp Voltage
−0.55
−0.60
−0.65
−9.5
−9.
Average for V
= 1 V, 3 V
I(IRAMP)
−9.7
−9.8
−9.9
−10.0
−10.1
−10.2
−0.70
−0.75
−10.3
−10.4
−10.5
−40 −20
0
20
60
80
100 120
−40 −20
0
20
40
60
80
100 120
MPERTURE (°C)
TEMPERATURE (°C)
Figure Output Current − Slow Rate
Figure 18. IRAMP Output Current − Fast Rate
10.5
10.4
10.3
10.2
10.1
10.0
9.9
120
115
110
105
100
95
9.8
90
9.7
85
80
9.6
9.5
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Voltage Gain, relative to ISNS
Figure 20. Current Overload Threshold, ISNS
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TPS2398, TPS2399
TYPICAL CHARACTERISTICS
V
I(−VIN)
= −48 V with respect to RTN, V
= 2.8 V, V
= 0 V, all outputs unloaded, device not in fault mode, T = 25°C
I(EN)
I(ISENS)
J
7.0
−45
V
V
= 80 mV
I(ISENS)
6.5
6.0
5.5
5.0
4.5
4.0
3.5
V
= 0 to 200 mV
−46
−47
−48
−49
−50
−51
−52
−53
I(ISENS)
= 2 V
O(FLTTIME)
3.0
2.5
2.0
−54
−55
−40
−20
0
20
40
60
80
−40
−
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Glitch Filter Delay Time
Figure 22. FLTTIME Charging Current
4.25
4.20
4.15
4.10
4.05
4.00
0.7
0.6
0.5
0.4
3.95
3.90
3.85
0.3
0.2
0.1
0
3.80
3.75
−40
−20
0
40
60
80
−40
−20
0
20
40
60
80
MPERTURE (°C)
TEMPERATURE (°C)
FigTIME Threshold Voltage
Figure 24. FLTTIME Discharge Current
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
−40
−20
0
20
40
60
80
TEMPERATURE (°C)
Figure 25. Fault−Retry Duty Cycle
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TPS2398, TPS2399
DETAILED PIN DESCRIPTIONS
EN
to the load is enabled. The device charges the external
Enable input to turn on/off power to the load. The EN pin
capacitor to establish the reference input to the LCA. The
closed−loop control of the LCA and pass FET acts to
maintain the current sense voltage at ISENS at the reference
potential. Since the sense voltage is developed as the drop
across a resistor, the charging current ramp rate is set by the
voltage ramp rate at the IRAMP pin. When the output is
disabled via the EN input or due to a load fault, the capacitor
is discharged and held low to initialize for the next turn−on.
is referenced to the −VIN potential of the circuit. When this
input is pulled high (above the nominal 1.4 V threshold) the
device enables the GATE output, and begins the ramp of
current to the load. When this input is low, the linear current
amplifier (LCA) is disabled, and a large pull−down device
is applied to the FET gate, disabling power to the load.
FLTTIME
Connection for user−programming of the fault timeout
period. An external capacitor connected from FLTTIME to
−VIN establishes the timeout period to declare a fault
condition. This timeout protects against indefinite current
sourcing into a faulted load, and also provides a filter against
nuisance trips from momentary current spikes or surges. The
TPS2398 and TPS2399 define a fault condition as voltage at
the ISENS pin at or greater than the 40 mV fault threshold.
When a fault condition exists, the timer is active. The
devices manage fault timing by charging the external
capacitor to the 4 V fault threshold, then subsequently
discharging it to reset the timer (TPS2398), or dischging
it at approximately 1% the charge rate to establish the dy
cycle for retrying the load (TPS2399). r th
internal fault latch is set (timer expired), T is
rapidly turned off, and the /PG output is de−
ISENS
Current sensinput. An external low value resistor
connected beween this pin and −VIN is used to feedback
current maitudinformation to the TPS2398/99. There
are twinterdeve thresholds associated with the
voltat the ISEpin. During charging of the load’s input
capacitane, or during other periods of excessive demand,
the HSPM as to limit this voltage to 40 mV. Whenever the
LA is in current regulation mode, the capacitor at
LTTIE pin is charged to activate the timer. If, when the
Cis driving to its supply rail, a fast−acting fault such as
a short−circuit, causes the ISENS voltage to exceed 100 mV
(the overload threshold), the GATE pin is pulled low rapidly,
bypassing tfault timer.
PG
Open−drain, active−low indication of load power good. A
power goostatus is declared when the output is enabled, the
GATE pin voltage has ramped to at least 7.5 V, and the
voltage on the IRAMP pin exceeds approximately 4.5 V.
This last condition assures that full programmed sourcing
current is available prior to declaring power good, even with
very slow current ramp rates. This additional protection
prevents potential discharging of the module input bulk
capacitance during load turn−on.
GATE
Gate drive for external N−channl ET. When enabled,
and the input supply is abovUVLO thrhold, the gate
drive is enabled and the ds charging an external
capacitor connected to the n. This pin voltage is
used to develop the erencge at the non−verting
input of the inteThe inverting input is connect
to the current seENS. The LCA acts to slew the
pass FET gate the ISENS voltage to track the
reference. The reference is internally clamped at 40 mV, so
the maximum current that can be sourced to the load is
determined by the sense resistor value as
RTN
Positive supply input for the TPS2398/99. For negative
voltage systems, the supply pin connects directly to the
return node of the input power bus. Internal regulators lower
down the input voltage to generate the various supply levels
used by the TPS2398 and TPS2399.
I
≤ 40 mV / R . Once the load vltage haramped up
MAX
SNS
to the input dc potential, and current demand drops off, the
LCA drives the GATE output to about 14 V to fully enhance
the pass FET, completing the low−impedance supply return
path for the load.
−VIN
Negative supply input and reference pin for the
TPS2398/99. This pin connects directly to the input supply
negative rail. The input and output pins and all internal
circuitry are referenced to this pin, so it is essentially the
GND or VSS pin of the device.
IRAMP
Programming input for setting the inrush current slew
rate. An external capacitor connected between this pin and
−VIN establishes the load current slew rate whenever power
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TPS2398, TPS2399
APPLICATIONS INFORMATION
General
The voltage at IRAMP is divided down by a factor of 100,
When a plug−in module or printed circuit card is inserted
and applied to the non−inverting input of the LCA. Load
current magnitude information at the ISENS pin is applied
to the inverting input. This voltage is developed by
connecting the current sense resistor between ISENS and
−VIN. The LCA controls the gate of the external pass FET
to force the ISENS voltage to track the divided down
IRAMP voltage. Consequently, the load current slew rate
tracks the linear voltage ramp at the IRAMP pin, producing
a linear di/dt of the load current. The IRAMP capacitor is
charged to about 5 V; however, the LCA input is clamped at
40 mV. Therefe, the current sourced to the load during
into a live chassis slot, discharged supply bulk capacitance
on the board can draw huge transient currents from the
system supplies. Without some form of inrush limiting,
these currents can reach peak magnitudes ranging up to
several hundred amps, particularly in high−voltage systems.
Such large transients can damage connector pins, PCB etch,
and plug−in and supply components. In addition, current
spikes can cause voltage droops on the power distribution
bus, causing other boards in the system to reset.
The TPS2398 and TPS2399 are hot swap power managers
designed to limit these peaks to preset levels, as well as
control the slew rate (di/dt) at which charging current ramps
to the user−programmed limit. These devices use an external
N−channel pass FET and sense element to provide
closed−loop control of current sourced to the load. Input
supply under−voltage lockout (UVLO) protection allows
hot swap circuits to turn on automatically with the
application of power, or to be controlled with a system
command via the EN input. External capacitors control both
the current ramp rate, and the time−out period for oad
voltage ramping. In addition, an internal overlo
comparator provides circuit breaker protainst
shorts occurring during steady−state on)
operation of the card.
The TPS2398 and TPS2399 oprate directly from the
input supply (nominal −48 VDra. Te –VIN pin
connects to the negative votge rail, and he RTN pin
connects to the supply reternal regulators convert
input power to the suppquired by the device
circuitry. An input UVLO cirs the GATE output low
until the supply eacha nominal 30 V level.
second comparthe EN input; this pin must be
pulled above the le threshold to turn on power to
the load.
Once enabled, and when the input supply s above the
UVLO threshold, the GATE pull−down is removed, the
linear control amplifier (LCA) is enabled, ad a large
discharge device in the RAMP CONTROL bock is turned
off. Subsequently, a small current source is now able to
charge an external capacitor connected to the IRAMP pin.
This results in a linear voltage ramp at IRAMP. The voltage
ramp on the capacitor actually has two discrete slopes. As
shown in Figure 2, charging current is supplied from either
of two sources. Initially at turn−on, the 600 nA source is
selected, to provide a slow turn−on rate. This slow turn−on
helps ensure that the LCA is pulled out of saturation, and is
slewing to the voltage at its non−inverting input before
normal rate load charging is allowed. This mechanism helps
reduce current steps at turn−on. Once the voltage at the
IRAMP pin reaches approximately 0.5 V, an internal
comparator de−asserts the SLOW signal, and the 10 mA
source is selected for the remainder of the ramp period.
turn−on is liited to a value given by I
≤ 40 mV / R
,
MAX
SNS
where R
te value of the sense resistor.
NS
The esultant oad current, regulated by the controller,
chagethe modue’s input bulk capacitance in a safe
ashion. nder normal conditions, this capacitance
eventually charges up to the dc input potential. At this point,
te load demand drops off, and the voltage at ISENS
ecrees. The LCA now drives the GATE output to its
sly rail.
The device detects this condition as the GATE voltage
rises through 7.5 V, latches thistatus and asserts the /PG
output. If the full srced current limit is not yet available to
the loa, as evidenced by the IRAMP voltage being less than
5 Ven the /PG asseron is delayed until that condition is
also met.
The peak, steady−state GATE pin output, typically 14 V,
ensures suffiient overdrive to fully enhance the external
FET, whilnot exceeding the typical 20 V V rating of
GS
common N−channel power FETs.
Fault timing is accomplished by connecting a capacitor
between the FLTTIME and −VIN pins, allowing
user−programming of the timeout period. Whenever the hot
swap controller is in current control mode as described
above, the LCA asserts an overcurrent indication – OC
signal in the Figure 2. Overcurrent fault timing is inhibited
during the slow turn−on portion of the IRAMP waveform.
However, once the device transitions to the normal rate
current ramp (V
≥ 0.5 V), the external capacitor is
IRAMP
charged by a 50 mA source, generating a voltage ramp at the
FLTTIME pin. If the load voltage ramps successfully, the
fault capacitor is discharged, and load initialization can
begin. However, if the timing capacitor voltage attains the
4 V fault threshold, the LCA is disabled, the pass FET is
rapidly turned off, and the fault is latched. Fault capacitor
charging ceases, and the capacitor is then discharged. In
addition, latching of a fault condition causes rapid discharge
of the IRAMP capacitor. In this manner, the soft−start
function is then reset and ready for the next output enable,
if and when conditions permit.
Subsequent to a plug−in’s start−up, and during the
module’s steady−state operation, load faults that force
current limit operation also initiate fault timing cycles as
www.onsemi.com
10
TPS2398, TPS2399
described above. In this case, a fault timeout also clears the
previously latched power good status.
Figure 26 is a scope capture of the TPS2398/99 response
in a diode−OR configuration to such an input transient event.
(All waveforms are referenced to the −VIN pin.) In this
example, the module is initially operating from a nominal
−43 V supply (relative to the backplane supply return node).
At the first major time division, another power supply, with
an output of −48 V, is suddenly hot swapped into a
secondary, or INB, input. This sudden voltage step is
reflected in the −48V_RTN trace. On this board, the 5 V
The TPS2398 latches off in response to faults; once a fault
timeout occurs, a large NMOS device is activated to rapidly
discharge the external capacitor, resetting the timer for any
subsequent device reset. The TPS2398 can only be reset by
cycling power to the device, or by cycling the EN input.
In response to a latched fault condition, the TPS2399
enters a fault retry mode, wherein it periodically retries the
load to test for continued existence of the fault. In this mode,
the FLTTIME capacitor is discharged slowly by a about a
0.4 mA constant−current sink. When the voltage at the
FLTTIME pin decays below 0.5 V, the LCA and RAMP
CONTROL circuits are re−enabled, and a normal turn−on
current ramp ensues. Again, during the load charging, the
OC signal causes charging of the FLTTIME capacitor until
the next delay period elapses. The sequential charging and
discharging of the FLTTIME capacitor results in a typical
1% retry duty cycle. If the fault subsides, the timing
capacitor is rapidly discharged, duty−cycle operation stops,
and the /PG output is asserted.
potential difference caused an 8 A spike, as shown by the I
IN
trace (I trace has been measured after the diode−OR). The
IN
GATE pin is rapidly pulled low, which quickly terminates
the overload spike. However, it is quickly released, and seen
to drive back the pass FET ON−threshold, in this case,
about 5 V. he rultant current−limit operation of the
circuit ievided by he 2 A load on the B supply. Once
supplcurrent iflwing again, the filter capacitance is
chrged p to the new input supply level, seen here on the
V
DRAIN
tre. Once the capacitance is fully charged, the
load demand rolls off to the operating 1 A level. As an added
enefit, this event is transparent to the /PG signal, which
emas asserted throughout the disturbance.
Note that because of the timing inhibit during the initial
slow ramp period, the duty cycle in practice is sightly
greater than the nominal 1% value. However, soued
current during this period peaks at only about ohth th
maximum limit. The duty cycle of the noand
constant−current periods is approximately 1
V
RTN
(5 V/div, offset 43 V)
V
IRAMP
(2 V/div)
The FAULT LOGIC within tTIMOCK
automatically manages capacitocharge and discharge
actions, and the enabling of the GAoutpu
C
C
C
R
R
= 3.9 nF
= 100 nF
= 100 mF
= 50 W
= 20 W
IRAMP
FLTTM
OUT
OUT
SNS
Supply Transient Respo
The TPS2398 and TPfeature a fast−acting
overload comparator which clamp large transients
from catastrophicurrionce the pass FET is fu
enhanced, such cuits. This function provides a
back−up protectLCA by providing a hard gate
discharge action whee LCA is saturated. If sense voltage
excursions above 100 mV are detected, this comparator
rapidly pulls down the GATE output, bypassing the fault
timer, and terminating the short−circuit conditio. Once the
spike has been brought down below the overlad threshold,
the GATE output is released, allowing the circuit to turn on
again in either current−ramp or current−limit mode. A 4 ms
deglitch filter is applied to the OL signal to help reduce the
occurrence of nuisance trips.
I
(2 A/div)
IN
V
(5 V/div)
GATE
V
(5 V/div)
DRAIN
V
(50 V/div)
/PG
In redundant−supply systems, the sudden switchover to a
supply of higher voltage potential is one more source of
large current spikes. Due to the low impedance of filter
capacitance under such high−frequency transients, these
spikes are generally indistinguishable from true
short−circuit faults to a hot swap controller. However, the
TPS2398 and TPS2399 transient response addresses this
issue by providing rapid circuit−breaker protection for load
faults along with minimal interruption of power flow during
supply switching events. The scope plots in Figure 26
illustrate how.
Figure 26. Input Transient Response
In order for downstream loads (bricks, etc.) to operate
through the distribution bus transient, it is important to
properly size the filtering capacitance to supply the needed
energy during the OFF−time of the pass FET. In this
example, once the RTN node jumps by 5 V higher than the
original potential, about 6 V develops across the FET,
www.onsemi.com
11
TPS2398, TPS2399
Setting the Inrush Slew Rate
indicating approximately a 1 V droop across the brick input.
Therefore, due to the fast response of the TPS2398/99
devices, the 100 mF capacitor achieves excellent hold−up of
the brick input voltage. Actual requirements depend heavily
on the individual application. Whether the device turns back
on in either current−ramp or current−limit mode depends in
The TPS2398 and TPS2399 devices enable
user−programming of the maximum current slew rate
during load start−up events. A capacitor tied to the IRAMP
pin (C in the typical application diagram) controls the di/dt
2
rate. Once the sense resistor value has been established, a
value for ramp capacitor C
, in microfarads, can be
part on the size of the ramp capacitor (C ) and the input
IRAMP
IRAMP
determined from Equation 2.
capacitance of the pass FET. But in any case, the circuit turns
back on in a controlled−current manner after rapidly
clamping the potentially damaging spike.
11
CIRAMP
+
(eq. 2)
di
@ ǒ Ǔ
100 @ RSNS
dt
MAX
Setting the Sense Resistor Value
Where:
Due to the current−limiting action of the internal LCA, the
maximum allowable load current for an implementation is
easily programmed by selecting the appropriate sense
resistor value. The LCA acts to limit the sense voltage
• R
is in hms, and
SENSE
is thdesired maximum slew rate, in
peres/cond.
di
• ǒdtǓ
X
V
ISENS
to its internal reference. Once the voltage at the
For emple, if e desired slew rate for the typical
applicatioshown is 1500 mA/ms, the calculated value for
IRAMP pin exceeds approximately 4 V, this limit is the
clamp voltage, V . Therefore, a maximum sense
REF_K
C
IRAMP
is aout 3.7 nF. Selecting the next larger standard
resistor value can be determined from Equation 1.
vue of 3.9 nF (as shown in the diagram) provides some
margin or capacitor and sense resistor tolerances.
Adescribed earlier in this section, the TPS2398 and
TPS2399 initiate ramp capacitor charging, and
consequently, load current di/dt at a reduced rate. This
reduced rate applies until the voltage on the IRAMP pin is
about 0.5 V. The maximum di/dt rate, as set by Equation 2,
is efective once the vice has switched to the 10 mA
charging source.
VREF_K(MIN)
R
R
SNS(MAX) v
(eq. 1)
IMAX
33 mV
IMAX
SNS(MAX) v
Where:
• R
is the sense resistor value,
is the minimum refclamp voltnd
is the desired current lim
SNS
• V
REF_K(MIN)
• I
MAX
Setting the Fault Timing Capacitor
When setting the sense resir value, it iimportant to
consider two factors, the um current that may be
imposed by the TPS2398 9, and the maximum
load under normal operatiomodule. For he first
factor, the speciinimm clamp value is used,
seen in Equatiothod accounts for the tolerance
in the sourced cubelow the typical level expected
The fault timeout period is established by the value of the
capacitor connected to the FLTTIME pin, C . The
FLTTM
timeout period permits riding out spurious current glitches
and surges that may occur during operation of the system,
and prevents indefinite sourcing into faulted loads swapped
into a live system. However, to ensure smooth voltage
ramping under all conditions of load capacitance and input
supply potential, the minimum timeout should be set to
accommodate these system variables. To do this, a rough
estimate of the maximum voltage ramp time for a
completely discharged plug−in card provides a good basis
for setting the minimum timer delay.
Due to the three−phase nature of the load current at
turn−on, the load voltage ramp potentially has three distinct
phases (compare Figures 3 and 4). This profile depends on
the relative values of load capacitance, input dc potential,
maximum current limit and other factors. The first two
phases are characterized by the two different slopes of the
current ramp; the third phase, if required for bulk
capacitance charging, is the constant−current charging at
(40 mV / R ). (The clamp measurement includes LCA
SNS
input offset voltage; therefore, this offset does not have to be
factored into the current limit again.) Second, if the load
current varies over a range of values uner norml operating
conditions, then the maximum load level mut be allowed
for by the value of R . One example of this is when the
SNS
load is a switching converter, or brick, which draws higher
input current, for a given power output, when the
distribution bus is at the low end of its operating range, with
decreasing draw at higher supply voltages. To avoid
current−limit operation under normal loading, some margin
should be designed in between this maximum anticipated
load and the minimum current limit level, or
I
> I , for Equation 1.
LOAD(MAX)
MAX
I
. Considering the two current ramp phases to be one
MAX
For example, using a 20 mW sense resistor for a nominal
period at an average di/dt simplifies calculation of the
required timing capacitor.
1 A load application provides a minimum of 650 mA of
overhead for load variance/margin. Typical bulk capacitor
charging current during turn−on is 2 A (40 mV / 20 mW).
www.onsemi.com
12
TPS2398, TPS2399
For the TPS2398 and TPS2399, the typical duration of the
soft−start ramp period, t , is given by Equation 3.
With this information, the minimum recommended value
timing capacitor C can be determined. The delay time
SS
FLTTM
needed will be either a time t
or the sum of t
and t
,
SS2
SS2
CC
(eq. 3)
t
SS + 1183 @ CIRAMP
according to the estimated time to charge the load. The
quantity t is the duration of the normal rate current ramp
Where:
• t is the soft−start period in ms, and
SS2
period, and is given by Equation 6.
SS
• C
is given in mF
(eq. 6)
t
SS2 + 0.35 @ CRAMP
IRAMP
During this current ramp period, the load voltage magnitude
which is attained is estimated by Equation 4.
Where:
• C
is given in microfarads
RAMP
iAVG
2
(eq. 4)
Since fault timing is generated by the constant−current
charging of C , the capacitor value is determined from
VLSS
+
@ tSS
2 @ CLOAD @ CRAMP @ 100 @ RSNS
FLTTM
either Equation or 8, as appropriate.
Where:
• V
is the load voltage reached during soft−start,
is 3.38 mA for the TPS2398 and TPS2399,
is the amount of the load capacitance, and
55 @ tSS2
3.75
LSS
(eq. 7)
(eq. 8)
FLTTM(MIN)
+
• i
AVG
• C
55 @ ǒt
Ǔ
LOAD
SS2 ) tCC
CFLTTM(MIN)
+
• t is the soft−start period, in seconds
SS
3.75
The quantity i
two charge currents applied to C
considering the typical output values.
If the result of Equation 4 is larger than the maximum
input supply value, then the load can be expected to arge
completely during the inrush slewing portion of the insern
event. However, if this voltage is less than imum
in Equation 4 is a weighted average of the
AVG
Where:
during turn−on,
IRAMP
• C
is the recommended capacitor value, in
FLTTM(MIN)
miofarads,
• is the result of Equation 6, in conds, and
SS2
• t is the result of Equation 5, in seconds.
CC
Continuing e typical application example, using a 100 mF
supply input, V , the HSPM trathe
IN(MAX)
input capacitor (C
)Equations 3 and 4 estimate the
LOAD
constant−current charging of the load. Ting
load voltage ramping approximately −46 V during the
soft−start period. If the module should operate down to
−72 V input supply, approximately another 1.58 ms of
constant−current charging may be required. Therefore,
amount of time required at I
Equation 5.
is determfrom
MA
ǒ
Ǔ
C
LOAD @ MAX) * VS
Equations and 8 are used to determine C
, and
FLTTM(MIN)
(eq. 5)
tCC
+
)
the result of 43 nF suggests the 47 nF standard value.
Where:
• t is the cont voltage ramp time, in
CC
seconds, and
• V
is the minimum clamp voltage, 33 mV.
REF_K(MIN)
www.onsemi.com
13
TPS2398, TPS2399
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.05
0.75
0.22
0.13
.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E1
E
e
3.00
0.65 BSC
0.60
L
0.40
0.80
L2
θ
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A2
A
DETAIL A
A1
b
c
E VIEW
END VIEW
q
L2
Notes:
L
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
www.onsemi.com
14
TPS2398, TPS2399
ORDERING INFORMATION
Device
Marking
2398
Fault Operation
Latch off
Package
Shipping†
TPS2398DMT7G
TPS2399DMT7G
MSOP−8
(Pb−Free)
3000 / Tape & Reel
2399
Periodically retry
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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