Q68000A8505 [OSRAM]
Lead (Pb) Free Product - RoHS Compliant;
| 型号： | Q68000A8505 |
| 厂家： | 
OSRAM GMBH |
| 描述： | Lead (Pb) Free Product - RoHS Compliant |
| 文件： | 总14页 (文件大小：712K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5.10 mm (0.200") 8-Character 5x7 Dot Matrix Parallel Input
Alphanumeric Intelligent Display® Devices
Lead (Pb) Free Product - RoHS Compliant
Red
PDSP2110
PDSP2111
PDSP2112
PDSP2113
Yellow
Super-red
Green
High Efficiency Green PDSP2114
DESCRIPTION
FEATURES
•
Eight 5.10 mm (0.200’’) Dot Matrix Characters in Red,
Yellow, Super-red, Green, High
Efficiency Green
Built-in 2 Page, 256 Character ROM,
Both pages are Mask Programmable for
Custom Fonts
Readable from 2.5 meters (8 feet)
Built-in Decoders, Multiplexers and Drivers
Wide Viewing Angle, X Axis ± 55°, Y Axis ± 65°
Programmable Features:
The PDSP2110 (Red), PDSP2111 (Yellow), PDSP2112
(Super-red), PDSP2113 (Green), and PDSP2114 (High
Efficiency Green) are eight digit, 5 x 7 dot matrix, parallel
input, alphanumeric Intelligent Display devices. The
5.10 mm (0.200’’) high digits are packaged in a rugged,
high quality, optically transparent, 15.24 mm (0.6’’) lead
spacing, 28 pin plastic DIP.
•
•
•
•
•
The on-board CMOS has a built-in 256 character ROM.
Both pages are mask programmable for 256 custom
characters.The first page of ROM of a standard product
contains 128 characters including ASCII, selected Euro-
pean and Scientific symbols. The second page contains
Katakana Japanese characters, more European charac-
ters, Avionics, and other graphic symbols.
–
–
–
–
–
Individual Flashing Character
Full Display Blinking
Multi-Level Dimming and Blanking
Clear Function
Lamp Test
The PDSP211X is designed for standard microprocessor
interface techniques, and is fully TTL compatible. The
Clock I/O and Clock Select pins allow the user to cas-
cade multiple display modules.
•
•
Internal or External Clock
End Stackable Dual-In-Line Plastic Package
2006-01-23
1
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Ordering Information
Type
Color of Emission
Character Height
mm (inch)
Ordering Code
PDSP2110
PDSP2111
PDSP2112
PDSP2113
PDSP2114
red
Q68000A8474
Q68000A8503
Q68000A8504
Q68000A8505
Q68000A8533
yellow
super-red
green
5.10 (0.200)
high efficiency green
Package Outlines
Dimensions in mm (inch)
Color Bin
EIA Date
Code
Intensity
Code
Part Number
PDSP211X Z
OSRAM
YYWW
V
Y
0.3 (0.012) typ.
15.24 (0.600)
2.19 (0.086)
0.46 (0.018) typ.
2.54 (0.100) typ.
4.79 (0.189)
42.67 (1.680) max.
5.34 (0.210)
2.67 (0.105)
Pin 1
Indicator
IDOD5020
2006-01-23
2
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Maximum Ratings (TA=25°C)
Parameter
Symbol
Top
Value
Unit
°C
°C
V
Operating temperature range
Storage temperature range
– 40 … + 85
– 40 … + 100
-0.5 to + 7.0
Tstg
DC Supply Voltage, VCC to GND
VCC
(max. voltage with no LEDs on)
Input Voltage Levels Relative to GND
-0.5 to VCC + 0.5
V
Solder Temperature
TS
260
°C
1.59 mm (0.063“) below seating plane, t < 5.0 s
Relative Humidity (non-condensing)
85
%
Optical Characteristics at 25°C
(VCC=5.0 V at 100% brightness level)
Description
Symbol
Values
Unit
Peak Luminous Intensity1)
(min.) IVpeak
(typ.)
70
90
130
210
150
330
150
260
200
510
µcd/dot
µcd/dot
Peak Wavelength
(typ.) λpeak
(typ.) λdom
660
639
583
585
630
626
565
570
568
574
nm
nm
Dominant Wavelength
Note:
1)
Peak luminous intensity is measured at TA=TJ=25°C. No time is allowed for the device to warm up prior to measurement.
2006-01-23
3
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Enlarged Character Font
Dimensions in inch (mm)
Switching Specifications
2.85 (0.112)
(over operating temperature range and VCC=4.5 V)
Symbol Description
Min.
30
130
10
0
Units
ns
C1 C2 C3 C4 C5
Tbw
Tacc
Tas
Time Between Writes
Display Access Time
Address Setup Time
Chip Enable Setup Time
Address Hold Time
Chip Enable Hold Time
Write Active Time
R1
R2
(2)
ns
ns
R3
R4
R5
Tces
Tah
Tceh
Tw
ns
20
0
ns
ns
R6
R7
100
50
ns
Tds
Data Valid Prior to Rising Edge
of Write
ns
Tdh
Data Hold Time
Reset Active Time
Clear Cycle Time
20
ns
ns
µs
0.65 (0.026) typ.
Wait
(1)
IDOD5202
Trc
300
3.0
(3)
Tclr
Notes:
Data
Data
1)
Wait 300 ns min. after the reset function is turned off.
Tacc=Tas+Tw+Tah
2)
3)
The Clear Cycle Time may be shortened by writing a second
Control Word with the Clear Bit disabled, 160 ns after the first
control word that enabled the Clear Bit.
The Flash RAM and Character RAM may not be accessed
until the Clear Cycle is complete.
Write control word - Wait 130 ns
clear bit enabled
Write control word -
clear bit enabled
IDTC5054
Write Cycle Timing Diagram
Tacc
Tas
Tah
see Notes
FL, A3-A0
CE
see Notes
Tces
Tceh
WR
see Notes
Tw
Tbw
see Notes
D7-D0
Tdh
Tds
Notes:
1. All input voltages are VIL=0.8 V, VIH=2.0 V.
2. These wave forms are not edge triggered.
3. Tbw=Tas+Tah
2006-01-23
4
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Electrical Characteristics at 25°C
Parameters
Limits
Min.
4.5
Conditions
Typ.
5.0
Max.
5.5
Units
V
VCC
—
ICC Blank
—
0.5
1.0
mA
mA
VCC=5.0 V, VIN=5.0 V
ICC 8 digits1)
—
200
255
VCC=5.0 V, “V” displayed in
12 dots/character
all eight digits
ICC 8 digits1)
20 dots/character
—
—
300
11
370
18
mA
VCC=5.0 V, “#” displayed in
all eight digits
IIP Current
(with pull-up)
µA
VCC=5.0 V, VIN=0 V to VCC
(WR, CE, FL, RST, CLKSEL)
I, Input Leakage Current
(no pull-up)
—
—
—
—
—
—
—
2.0
25
—
—
±1.0
µA
V
VCC=5.0 V,VIN=0 V to VCC
(Clk I/O, A0–A3, D0–D7)
VIH Input Voltage High
2.0
VCC
+0.3
VCC=4.5 V to 5.5 V
VCC=4.5 V to 5.5 V
VIL Input Voltage Low
GND
–0.3
0.8
0.4
—
V
VOL Output Voltage Low
(Clock Pin)
—
V
VCC=4.5 V to 5.5 V
IOL=1.6 mA
VOH Output Voltage High
(Clock Pin)
2.4
–0.9
1.6
—
V
VCC=4.5 V to 5.5 V
IOH=40 mA
IOH Output Current High
(Clock I/O)
—
mA
mA
°C/W
kHz
kHz
VCC=4.5 V, VOH=–2.4 V
VCC=4.5 V, VOL=–0.4 V
—
IOL Output Current Low
(Clock I/O)
—
θJC Thermal Resistance
—
Junction to Case
FEXT External Clock
Input Frequency2)
28
81.14
81.14
VCC=5.0 V, CLKSEL=0
VCC=5.0 V, CLKSEL=1
FOSC Internal Clock
Output Frequency2)
28
Clock I/O Buss Loading
Clock Out Rise Time
Clock Out Fall Time
—
—
—
—
240
pF
ns
ns
Hz
Hz
—
—
500
VCC=4.5 V, VOH=2.4 V
—
500
VCC=4.5 V, VOL=0.4 V
FM, Digit Multiplex Frequency 125
256
2.0
362.5
2.83
—
—
Blinking Rate
0.98
Notes:
1)
Average ICC measured at full brightness. Peak ICC=2 x IAVG ICC (# displayed).
Internal/external frequency duty factor is 50%.
2)
2006-01-23
5
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Top View
Pin Definitions
28
Pins
15
Pin Function
Definition
1
RST
Used for initialization of a display and
sychronization of blinking for multiple displays
2
3
4
5
6
FL
A0
A1
A2
A3
Low input accesses the Flash RAM
Address input LSB
Address input
0
1
2
3
4
5
6
7
Address input MSB
Mode selector
Digit
Pins
7-9 Substr. bias Used to bias IC substrate, must be connected
to VCC. Can't be used to supply power to
display.
1
14
IDPA5116
10
11
12
13
No connect
CLKSEL
CLK I/O
WR
—
Pin Assignments
Selects internal/external clock source
Pin
1
Function
Pin
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Function
D7
Outputs master clock or inputs external clock
RST
FL
A low will write data into the display if CE is
low
2
D6
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VCC
Positive power supply input
Analog Ground for LED drivers
Digital Ground for internal logic
Enables access to the display
—
3
A0
D5
GND
GND
CE
4
A1
D4
5
A2
D3
6
A3
D2
No Connect
D0
7
Substr. bias
No Pin
Data input LSB
8
D1
Data input
9
D1
No pin
—
10
11
12
13
14
No Connect
CLKSEL
CLK I/O
WR
D0
No Connect
CE
D2
D3
D4
D5
D6
D7
Data input
GND (logic)
VCC
GND (supply)
Data input MSB, selects ROM, page 1 or 2
2006-01-23
6
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Cascading the PDSP211X Displays
RD
WR
FL
RST
VCC
RD WR FL RST CLK CLK
I/O SEL
RD WR FL RST CLK CLK
I/O SEL
Up to 14 more
displays in between
Display
Display
D0-D7 A0-A4
CE
D0-D7 A0-A4
CE
Data I/O
Address
0
A6
A7
A8
A9
Address Decode Chip 1 to 14
Address
Decoder
15
IDCD5031
2006-01-23
7
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Character Set
ROM Page 1 (D7= 0)
D0
D1
D2
D3
0
0
0
0
0
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
ASCII
CODE
D6 D5 D4 HEX
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
IDCS5093
ROM Page 2 (D7=1)
D0
D1
D2
D3
0
0
0
0
0
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
ASC||
CODE
D6 D5 D4 HEX
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
IDCS5094
2006-01-23
8
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Block Diagram
Rows
0 to 13
Display
0
1
2
3
4
5
6
7
Columns 0 to 19
Row Control Logic
& Row Drivers
RST
Blink
Rate
CLK I/O
CLKSEL
32
Counter
7
128
Counter
OSC
Counter
Timing &
Control
Logic
MUX Rate
Master
Slave
Latches
D7
Row Decoder
Column
Drivers
for Digit
0 to 8
Digit
0 to 8
ROM 1
128 x 7 bit 128 x 7 bit
ASCII ASCII
Character Character
Decode Decode
(4.48 kbits) (4.48 kbits)
ROM 2
D6
D5
D4
D3
D2
D1
D0
Control
Display
Memory
8 x 8 bits
Column
Data
Word
Decode
Logic
7-bit
ASCII
Code
Address
Lines
Flash RAM
8 x 1 bit
Address Decoder
A0 A1 A2 A3 WR CE FL
IDBD5068
Functional Description
be an input from another PDSP211X display for the synchroniza-
tion of blinking for multiple displays.
The PDSP211X block diagram is comprised of the following major
blocks and registers.
The Display Multiplexer controls the Row Drivers so no additional
logic is required for a display system.
Display Memory consists of a 8 x 8 bit RAM block. Each of the
eight 8-bit words holds the 7-bit ASCII data (bit D0-D6). The 8th
bit, D7 selects 1 of the 2 pages of character ROM. D7=0 selects
Page 1 of the ROM and D7=1 selects Page 2 of the ROM. A3=1.
The Display has eight digits. Each digit has 35 LEDs clustered
into a 5 x 7 dot matrix.
Theory of Operation
RST can be used to initialize display operation upon power up or
during normal operation. When activated, RST will clear the Flash
RAM and Control Word Register (00H) and reset the internal
counter. All eight display memory locations will be set to 20H to
show blanks in all digits.
The PDSP211X Programmable display is designed to work with all
major microprocessors. Data entry is via an eight bit parallel bus.
Three bits of address route the data to the proper digit location in
the RAM. Standard control signals like WR and CE allow the data
to be written into the display.
FL pin enables access to the Flash RAM. The Flash RAM will set
(D0=0) or reset (D0=0) flashing of the character addressed by
A0-A2.
D0- D7 data bits are used for both ASCII and control word data
input. A3 acts as the mode selector. If A3=0, D0-D7 load the RAM
with control word data. If A3=1, D0-D7 will load the RAM with
ASCII and page select data. In the later mode, D7=0 selects Page
1 of Character ROM and D7=1 selects Page 2 of Character ROM.
The 1 x 8 bit Control Word RAM is loaded with attribute data
if A3=0.
The Control Word Logic decodes attribute data for proper imple-
mentation.
For normal operation FL pin should be held high. When FL is held
low, Flash RAM is accessed to set character blinking.
Character ROM is designed for two pages of 128 characters each.
Both pages of the ROM are Mask Programmable for custom fonts.
On the standard product page one contains standard ASCII,
selected European characters and some scientific symbols. Page
two contains Katakana characters, more European characters, avi-
onics, and other graphic symbols.
The seven bit ASCII code is decoded by the Character ROM to
generate Column data. Twenty columns worth of data is sent out
each display cycle and it takes fourteen display cycles to write into
eight digits.
The rows are being multiplexed in two sets of seven rows each.
The internal timing and control logic synchronizes the turning on of
rows and presentation of column data to assure proper display
operation.
The Clock Source could either be the internal oscillator
(CLKSEL=1) of the device or an external clock (CLKSEL=0) could
2006-01-23
9
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Data Input Commands
Signals
CE
WR
FL
A3
A2
A1
A0
Operation
1
X
X
1
X
X
X
X
X
X
X
X
X
X
No operation
No operation
0
0
1
0
0
0
0
Write Control Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Digit 0 (left)
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7 (right)
Write display data to
user RAM and Page
Select Register
D0–D6=ASCII Data
D7=0 Select ROM 1
D7=1 Select ROM 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Digit 0 (left)
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7 (right)
Write Flash RAM Register
D0=0 Flashing Charac. off
D0=1 Flashing Charac. on
D1–D7=X
X=Don’t care
Power up Sequence
Microprocessor Interface
Upon power up display will come on at random. Thus the display
should be reset on power-up. The reset will clear the Flash RAM,
Control Word Register and reset the internal counter. All the dig-
its will show blanks and display brightness level will be 100%.
The interface to a microprocessor is through the 8-bit data bus
(D0-D7), the 4-bit address bus (A0-A3) and control lines FL, CE
and WR.
To write data (ASCII/Control Word) into the display CE should be
held low, address and data signals stable and WR should be
brought low.
The Control Word is decoded by the Control Word Decode Logic.
Each code has a different function. The code for display brightness
changes the duty cycle for the column drivers. The peak LED cur-
rent stays the same but the average LED current diminishes
depending on the intensity level.
The character Flash Enable causes 2.0 Hz coming out of the
counter to be ANDED with column drive signal and makes the col-
umn driver to cycle at 2.0 Hz. Thus the character flashes at 2.0 Hz.
The display Blink works the same way as the Flash Enable but
causes all twenty column drivers to cycle at 2.0 Hz thereby making
all eight digits to blink at 2.0 Hz.
The Lamp Test causes the column drivers to run at 1/2 duty cycle
thus all the LEDs in all eight digits turn on at 50% intensity.
Clear bit clears the character RAM and writes a blank into the dis-
play memory. It however does not clear the control word.
ASCII Data or Control Word Data can be written into the display at
this point. For multiple display operation, CLK I/O must be properly
selected. CLK I/O will output the internal clock if CLKSEL=1, or will
allow input from an external clock if CLKSEL=0.
2006-01-23
10
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Control Word Format
Display Brightness
The display can be programmed to vary between blank, 13%, 20%, 27%, 40%, 53%, 80% and full brightness.
Bits D0, D1 and D2 control the display brightness.
CE
WR
FL
A3
A2
A1
A0 D7
D6
D5
D4
D3
D2
D1
D0
Display Brightness
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100% Brightness
80% Brightness
53% Brightness
40% Brightness
27% Brightness
20% Brightness
13% Brightness
Blank Display
X=Don’t Care
Flash RAM Function
Character Flash is controlled by FL pin, bit D0 and control word bit D3. Combination of FL being low, proper digit address and D0 being
high will write a flash bit into the Flash RAM Register. In the control word mode when D3 is brought high, the above mentioned character
will flash.
Setting the Flash Bit
CE
WR
FL
A3
A2
A1
A0 D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
0
0
0
0
0
X
X
A
A
A
A
A
A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
Flash RAM Disabled
Flash RAM Enabled
X=Don’t Care A=Selected Address
Character Flash Control Word
CE
WR FL
A3
A2
A1
A0 D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
0
0
0
1
1
0
0
X
X
X
X
X
X
0
0
0
0
X
X
0
0
0
1
B
B
B
B
B
B
Disable Flashing Character
Enable Flashing Character
X=Don’t Care B=Selected Brightness
Display Blinking
Blinking Function is independent of Flash function. When D4 is held high, entire display blinks at 2.0 Hz.
CE
WR FL
A3
A2
A1
A0 D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
0
0
0
1
1
0
0
X
X
X
X
X
X
0
0
0
0
X
X
0
1
0
0
B
B
B
B
B
B
Display Blinking Disabled
Display Blinking Enabled
X=Don’t Care B=Selected Brightness
Lamp Test
Bit D6 when brought high will cause all the LEDs in all eight digits to light up at 53% brightness.
Selecting or de-selecting Lamp Test bit has no effect on the display memory.
CE
WR
FL
A3
A2
A1
A0 D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
0
0
0
1
1
0
0
X
X
X
X
X
X
0
0
0
1
X
X
0
0
X
0
X
X
X
X
X
X
Lamp Test Disabled
Lamp Test Enabled
X=Don’t Care
2006-01-23
11
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Clear Function
Clear function will clear the display. The Flash RAM will be set to all zeros. An ASCII blank code (20H) will be written into the display
memory. The user must wait 3.0 ms or write a new control word to the display with control word bit D7 = 0 to disable clear before writing
any data to the display memory, otherwise all new data to the display memory will remain cleared. See Switching Specifications for clear
function timing.
CE
WR
FL
A3
A2
A1
A0 D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
0
0
0
1
1
0
0
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Clear Disabled
Clear User RAM,
Page RAM, Flash
RAM and Display
X=Don’t Care
Control Word Format
D7
D6
D5
Not Used
D4
D3
D2
D1
Brightness Control
D0
Clear
Enable
Lamp
Test
Blink
Enable
Flash
Enable
D2 D1 D0 Brightness
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100%
80%
53%
40%
27%
20%
13%
0% Blank
D3 Flash Enable
0
1
Disable Flashing Character
Enable Flashing Character
D4 Blinking Display
0
1
Disable Blinking Display
Enable Blinking Display
D6 Lamp Test
0
1
Disable Lamp Test
Enable Lamp Test (all dots on at 53% brightness)
D7 Clear Enable
0
1
Disable Clear
Enable Clear (clear Data RAM, Page RAM, Flash RAM)
IDCW5164
2006-01-23
12
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Electrical and Mechanical Considerations
Voltage Transient Suppression
Albany, IN; and Samtec Electronic Hardward, New Albany, IN.
For further information refer to Appnote 22 at www.osram-os.com
For best results power the display and the components that inter-
face with the display to avoid logic inputs higher than VCC. Addi-
tionally, the LEDs may cause transients in the power supply line
while they change display states. The common practice is to place
a parallel combination of a 0.01 µF and a 22 µF capacitor between
VCC and GND for all display packages.
Optical Considerations
The 5.10 mm (0.200") high character of the PDSP211X gives read-
ability up to eight feet. Proper filter selection enhances readability
over this distance.
Using filters emphasizes the contrast ratio between a lit LED and
the character background. This will increase the discrimination of
different characters. The only limitation is cost. Take into consider-
ation the ambient lighting environment for the best cost/benefit
ratio for filters.
ESD Protection
The input protection structure of the PDSP2110/1/2/3/4 provides
significant protection against ESD damage. It is capable of with-
standing discharges greater than 2.0 kV. Take all the standard pre-
cautions, normal for CMOS components. These include properly
grounding personnel, tools, tables, and transport carriers that come
in contact with unshielded parts. If these conditions are not, or can-
not be met, keep the leads of the device shorted together or the
parts in anti-static packaging.
Incandescent (with almost no green) or fluorescent (with almost no
red) lights do not have the flat spectral response of sunlight. Plas-
tic band-pass filters are an inexpensive and effective way to
strengthen contrast ratios. The PDSP2110/2112 are red/super-red
displays and should be matched with long wavelength pass filter in
the 570 nm to 590 nm range. The PDSP2111/2113/2114 should
be matched with a yellow-green band-pass filter that peaks at
565 nm. For displays of multiple colors, neutral density grey filters
offer the best compromise.
Soldering Considerations
The PDSP2110/1/2/3/4 can be hand soldered with SN63 solder
using a grounded iron set to 260°C.
Additional contrast enhancement is gained by shading the dis-
plays. Plastic band-pass filters with built-in louvers offer the next
step up in contrast improvement. Plastic filters can be improved
further with anti-reflective coatings to reduce glare. The trade-off is
fuzzy characters. Mounting the filters close to the display reduces
this effect. Take care not to overheat the plastic filter by allowing for
proper air flow.
Wave soldering is also possible following these conditions: Pre-
heat that does not exceed 93°C on the solder side of the PC board
or a package surface temperature of 85°C. Water soluble organic
acid flux (except carboxylic acid) or rosin-based RMA flux without
alcohol can be used.
Wave temperature of 245°C ± 5°C with a dwell between 1.5 sec. to
3.0 sec. Exposure to the wave should not exceed temperatures
above 260°C for five seconds at 1.59 mm (0.063") below the seating
plane. The packages should not be immersed in the wave.
Optimal filter enhancements are gained by using circular polar-
ized, anti-reflective, band-pass filters. The circular polarizing fur-
ther enhances contrast by reducing the light that travels through
the filter and reflects back off the display to less than 1%.
Post Solder Cleaning Procedures
Several filter manufacturers supply quality filter materials. Some of
them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homa-
lite, Wilmington, DE; 3M Company, Visual Products Division, St.
Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge,
MA; Marks Polarized Corporation, Deer Park, NY, Hoya Optics,
Inc., Fremont, CA.
The least offensive cleaning solution is hot D.I. water (60°C) for
less than 15 minutes. Addition of mild saponifiers is acceptable.
Do not use commercial dishwasher detergents.
For faster cleaning, solvents may be used. Exercise care in choos-
ing solvents as some may chemically attack the nylon package.
Maximum exposure should not exceed two minutes at elevated
temperatures. Acceptable solvents are TF (trichorotrifluorethane),
TA, 111 Trichloroethane, and unheated acetone.(1)
One last note on mounting filters: recessing displays and bezel
assemblies is an inexpensive way to provide a shading effect in
overhead lighting situations. Several bezel manufacturers are:
R.M.F. Products, Batavia, IL; Nobex Components, Griffith Plastic
Corp., Burlingame, CA; Photo Chemical Products of California,
Santa Monica, CA; I.E.E.–Atlas, Van Nuys, CA.
Note:
1)
Acceptable commercial solvents are: Basic TF, Arklone, P.
Genesolv, D. Genesolv DA, Blaco-Tron TF and Blaco-Tron TA.
Unacceptable solvents contain alcohol, methanol, methylene
chloride, ethanol, TP35, TCM, TMC, TMS+, TE, or TES. Since
many commercial mixtures exist, contact a solvent vendor for
chemical composition information. Some major solvent manufac-
turers are: Allied Chemical Corporation, Specialty Chemical Divi-
sion, Morristown, NJ; Baron-Blakeslee, Chicago, IL; Dow
Chemical, Midland, MI; E.I. DuPont de Nemours & Co., Wilming-
ton, DE.
For further information refer to Appnotes 18 and 19 at
www.osram-os.com
An alternative to soldering and cleaning the display modules is to
use sockets. Naturally, 28 pin DIP sockets 15.24 mm (0.600") wide
with 2.54 mm (0.100") centers work well for single displays.
Multiple display assemblies are best handled by longer SIP sock-
ets or DIP sockets when available for uniform package alignment.
Socket manufacturers are Aries Electronics, Inc., Frenchtown, NJ;
Garry Manufacturing, New Brunswick, NJ; Robinson-Nugent, New
2006-01-23
13
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Revision History: 2006-01-23
Previous Version: 2005-01-10
Page
Subjects (major changes since last revision)
Lead free device
Date of change
all
2006-01-23
Published by
OSRAM Opto Semiconductors GmbH
Wernerwerkstrasse 2, D-93049 Regensburg
www.osram-os.com
© All Rights Reserved.
Attention please!
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved. Due to technical requirements components may contain
dangerous substances. For information on the types in question please contact our Sales Organization.
If printed or downloaded, please find the latest version in the Internet.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.
By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing
material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs
incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose! Critical
components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS.
1)
A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system.
Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain
2)
human life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.
2006-01-23
14
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