PMS132B-4N10 [PADAUK]
8bit OTP MCU with 12-bit ADC;
| 型号： | PMS132B-4N10 |
| 厂家： | 
PADAUK Technology |
| 描述： | 8bit OTP MCU with 12-bit ADC |
| 文件： | 总100页 (文件大小：1870K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Datasheet
Version 1.04 – June 2, 2020
Copyright 2020 by PADAUK Technology Co., Ltd., all rights reserved
6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.
TEL: 886-3-572-8688 www.padauk.com.tw
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those which may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,
customers should design a product with adequate operating safeguards.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 2 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Table of content
1. Features.................................................................................................................................9
1.1.
1.2.
1.3.
1.4.
Special Features.....................................................................................................................9
System Features.....................................................................................................................9
CPU Features.........................................................................................................................9
Package Information ...............................................................................................................9
2. General Description and Block Diagram..........................................................................10
3. Pin Assignment and Description ......................................................................................11
4. Device Characteristics.......................................................................................................18
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
AC/DC Device Characteristics ..............................................................................................18
Absolute Maximum Ratings...................................................................................................20
Typical ILRC frequency vs. VDD and temperature................................................................20
Typical IHRC frequency deviation vs. VDD(calibrated to 16MHz)..........................................21
Typical ILRC Frequency vs. Temperature.............................................................................21
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)..........................................22
Typical operating current vs. VDD @ system clock = ILRC/n................................................22
Typical operating current vs. VDD @ system clock = IHRC/n ...............................................23
Typical operating current vs. VDD @ system clock = 4MHz EOSC / n..................................23
4.10. Typical operating current vs. VDD @ system clock = 32KHz EOSC / n.................................24
4.11. Typical operating current vs. VDD @ system clock = 1MHz EOSC / n..................................24
4.12. Typical IO driving current (IOH) and sink current (IOL) .............................................................25
4.13. Typical IO input high/low threshold voltage (VIH/VIL) ..............................................................27
4.14. Typical resistance of IO pull high device ...............................................................................27
4.15. Typical power down current (IPD) and power save current (IPS)..............................................28
5. Functional Description.......................................................................................................29
5.1.
5.2.
Program Memory - OTP........................................................................................................29
Boot Procedure.....................................................................................................................29
5.2.1. Timing charts for reset conditions.................................................................................30
Data Memory - SRAM...........................................................................................................31
Oscillator and clock...............................................................................................................31
5.4.1. Internal High RC oscillator and Internal Low RC oscillator.........................................31
5.4.2. Chip calibration..........................................................................................................31
5.4.3. IHRC Frequency Calibration and System Clock ........................................................32
5.4.4. External Crystal Oscillator .........................................................................................33
5.3.
5.4.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 3 of 100
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PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.4.5. System Clock and LVR level .....................................................................................35
5.4.6. System Clock Switching ............................................................................................36
Comparator...........................................................................................................................37
5.5.1 Internal reference voltage (Vinternal R)...........................................................................38
5.5.2 Using the comparator ................................................................................................40
5.5.3 Using the comparator and band-gap 1.20V ...............................................................41
16-bit Timer (Timer16) ..........................................................................................................42
8-bit Timer (Timer2/Timer3) with PWM generation................................................................44
5.7.1 Using the Timer2 to generate periodical waveform....................................................45
5.7.2 Using the Timer2 to generate 8-bit PWM waveform...................................................47
5.7.3 Using the Timer2 to generate 6-bit PWM waveform...................................................48
11-bit PWM Generator ..........................................................................................................49
5.8.1 PWM Waveform ........................................................................................................49
5.8.2 Hardware and Timing Diagram..................................................................................50
5.8.3 Equations for 11-bit PWM Generator.........................................................................51
5.8.4 Complementary PWM with Dead Zones....................................................................51
WatchDog Timer...................................................................................................................53
5.5.
5.6
5.7
5.8
5.9
5.10 Interrupt ................................................................................................................................54
5.11 Power-Save and Power-Down ..............................................................................................57
5.11.1 Power-Save mode (“stopexe”)...................................................................................57
5.11.2 Power-Down mode (“stopsys”) ..................................................................................58
5.11.3 Wake-up....................................................................................................................58
5.12 IO Pins..................................................................................................................................59
5.13 Reset and LVR......................................................................................................................60
5.13.1 Reset.........................................................................................................................60
5.13.2 LVR reset ..................................................................................................................60
5.14 Analog-to-Digital Conversion (ADC) module .........................................................................61
5.14.1 The input requirement for AD conversion ..................................................................62
5.14.2 Select the reference high voltage ..............................................................................63
5.14.3 ADC clock selection...................................................................................................63
5.14.4 Configure the analog pins..........................................................................................63
5.14.5 Using the ADC...........................................................................................................63
5.15 Multiplier ...............................................................................................................................64
6. IO Registers ........................................................................................................................65
6.1.
6.2.
6.3.
6.4.
6.5.
ACC Status Flag Register (flag), IO address = 0x00 .............................................................65
Stack Pointer Register (sp), IO address = 0x02 ....................................................................65
Clock Mode Register (clkmd), IO address = 0x03 .................................................................65
Interrupt Enable Register (inten), IO address = 0x04 ............................................................66
Interrupt Request Register (intrq), IO address = 0x05...........................................................66
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.6.
6.7.
6.8.
6.9.
Multiplier Operand Register (mulop), IO address = 0x08.......................................................66
Multiplier Result High Byte Register (mulrh), IO address = 0x09...........................................66
Timer16 mode Register (t16m), IO address = 0x06...............................................................67
External Oscillator setting Register (eoscr), IO address = 0x0a.............................................67
6.10. Interrupt Edge Select Register (integs), IO address = 0x0c...................................................68
6.11. Port A Digital Input Enable Register (padier), IO address = 0x0d..........................................68
6.12. Port B Digital Input Enable Register (pbdier), IO address = 0x0e..........................................69
6.13. Port A Data Register (pa), IO address = 0x10.......................................................................69
6.14. Port A Control Register (pac), IO address = 0x11 .................................................................69
6.15. Port A Pull-High Register (paph), IO address = 0x12 ............................................................69
6.16. Port B Data Register (pb), IO address = 0x14.......................................................................69
6.17. Port B Control Register (pbc), IO address = 0x15 .................................................................69
6.18. Port B Pull-High Register (pbph), IO address = 0x16 ............................................................70
6.19. Miscellaneous Register (misc), IO address = 0x17................................................................70
6.20. Comparator Control Register (gpcc), IO address = 0x18.......................................................70
6.21. Comparator Selection Register (gpcs), IO address = 0x19....................................................71
6.22. Reset Status Register (rstst), IO address = 0x1b ..................................................................71
6.23. Timer2 Control Register (tm2c), IO address = 0x1c ..............................................................72
6.24. Timer2 Counter Register (tm2ct), IO address = 0x1d............................................................72
6.25. Timer2 Scalar Register (tm2s), IO address = 0x1e................................................................72
6.26. Timer2 Bound Register (tm2b), IO address = 0x09 ...............................................................73
6.27. PWMG0 control Register (pwmg0c), IO address = 0x20 .......................................................73
6.28. PWMG0 Scalar Register (pwmg0s), IO address = 0x21........................................................73
6.29. PWMG0 Counter Upper Bound High Register (pwmg0cubh), IO address = 0x24 .................73
6.30. PWMG0 Counter Upper Bound Low Register (pwmg0cubl), IO address = 0x25 ...................74
6.31. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22 .....................................74
6.32. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23 .......................................74
6.33. Timer3 Control Register (tm3c), IO address = 0x32 ..............................................................74
6.34. Timer3 Counter Register (tm3ct), IO address = 0x33............................................................75
6.35. Timer3 Scalar Register (tm3s), IO address = 0x34................................................................75
6.36. Timer3 Bound Register (tm3b), IO address = 0x3f ................................................................75
6.37. ADC Control Register (adcc), IO address = 0x3b..................................................................75
6.38. ADC Mode Register (adcm), IO address = 0x3c....................................................................76
6.39. ADC Regulator Control Register (adcrgc), IO address = 0x3d...............................................76
6.40. ADC Result High Register (adcrh), IO address = 0x3e..........................................................76
6.41. ADC Result Low Register (adcrl), IO address = 0x3f.............................................................76
6.42. PWMG1 control Register (pwmg1c), IO address = 0x26 .......................................................77
6.43. PWMG1 Scalar Register (pwmg1s), IO address = 0x27........................................................77
6.44. PWMG1 Counter Upper Bound High Register (pwmg1cubh), IO address = 0x2A.................77
6.45. PWMG1 Counter Upper Bound Low Register (pwmg1cubl), IO address = 0x2B...................77
©Copyright 2020, PADAUK Technology Co. Ltd
Page 5 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.46. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28 .....................................78
6.47. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29.......................................78
6.48. PWMG2 control Register (pwmg2c), IO address = 0x2C.......................................................78
6.49. PWMG2 Scalar Register (pwmg2s), IO address = 0x2D .......................................................78
6.50. PWMG2 Counter Upper Bound High Register (pwmg2cubh), IO address = 0x30 .................79
6.51. PWMG2 Counter Upper Bound Low Register (pwmg2cubl), IO address = 0x31 ...................79
6.52. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2E.....................................79
6.53. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2F.......................................79
7. Instructions.........................................................................................................................80
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
Data Transfer Instructions.....................................................................................................81
Arithmetic Operation Instructions ..........................................................................................83
Shift Operation Instructions...................................................................................................85
Logic Operation Instructions..................................................................................................86
Bit Operation Instructions......................................................................................................88
Conditional Operation Instructions ........................................................................................90
System control Instructions ...................................................................................................91
Summary of Instructions Execution Cycle .............................................................................93
Summary of affected flags by Instructions.............................................................................93
7.10. BIT definition.........................................................................................................................93
8. Code Options......................................................................................................................94
9. Special Notes......................................................................................................................95
9.1.
9.2.
Warning ................................................................................................................................95
Using IC................................................................................................................................95
9.2.1 IO pin usage and setting...............................................................................................95
9.2.2 Interrupt.....................................................................................................................96
9.2.3 System clock switching..............................................................................................96
9.2.4 Watchdog..................................................................................................................97
9.2.5 TIMER time out .........................................................................................................97
9.2.6 IHRC .........................................................................................................................98
9.2.7 LVR...........................................................................................................................98
9.2.8 The result of Comparator controls the PWM output pins............................................98
9.2.9 Programming the PMS132/PMS132B........................................................................99
Using ICE............................................................................................................................100
9.3
©Copyright 2020, PADAUK Technology Co. Ltd
Page 6 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Revision History:
Revision
Date
2016/08/08 Preliminary version
1. Revise Chapter 3: Pin Assignment and Description
Description
0.00
2. Revise Section 5.8.2: Hardware and Timing Diagram
2016/12/01 3. Revise Section 5.8.3: Frequency of PWM Output
4. Add Section 5.8: 11-bit PWM Generator Functional Description
5. Add Section 6.43~6.51: IO Registers
0.01
1. Revise Section 1.2 System Features
2. Add Section 1.4 Package Information
3. Revise Chapter 2 General Description and Block Diagram
4. Add Chapter
3
Pin Assignment and Description:PMS132/PMS132B-S08,
PMS132/PMS132B-U06
5. Revise Section 4.1 AC/DC Device Characteristics: “VIL” and “VIH”
6. Revise Section 4.3 Typical ILRC frequency vs. VDD and temperature
7. Revise Section 4.4 Typical IHRC frequency deviation vs. VDD
8. Revise Section 4.5 Typical ILRC Frequency vs. Temperature
9. Revise Section 4.6 Typical IHRC Frequency vs. Temperature
10. Revise Section 4.7 Typical operating current vs. VDD @ system clock = ILRC/n
11. Revise Section 4.8 Typical operating current vs. VDD @ system clock = IHRC/n
12. Revise Section 4.9 Typical operating current vs.VDD@system clock=4MHz EOSC / n
13. Revise Section 4.10 Typical operating current vs.VDD@system clock=32KHz EOSC / n
14. Revise Section 4.11 Typical operating current vs.VDD@system clock=1MHz EOSC / n
15. Revise Section 4.12 Typical IO driving current (IOH) and sink current (IOL)
16. Revise Section 4.13 Typical IO input high/low threshold voltage (VIH/VIL)
17. Revise Section 4.14 Typical resistance of IO pull high device
18. Add Section 4.15 Typical power down current (IPD) and power save current (IPS)
19. Revise Section 5.1 Program Memory - OTP
20. Revise Table 2: Three oscillation circuits
21. Revise Section 5.4.3 IHRC Frequency Calibration and System Clock
22. Revise Section 5.4.4 External Crystal Oscillator
0.02
2017/11/23 23. Revise Fig. 3: Options of System Clock
24. Revise Section 5.5.2 Using the comparator
25. Revise Section 5.6 16-bit Timer
26. Revise Section 5.8 11-bit PWM Generator
27. Revise Section 5.11.1 Power-Save mode
28. Revise Fig. 20: ADC Block Diagram
29. Revise Section 5.14.4 Configure the analog pin
30. Revise Section 5.14.5 Using the ADC
31. Revise Section 6.3 Clock Mode Register
32. Revise Section 6.4 Interrupt Enable Register
33. Revise Section 6.5 Interrupt Request Register
34. Revise Section 6.11 Port A Digital Input Enable Register
35. Revise Section 6.12 Port B Digital Input Enable Register
36. Delete Section 6.13 MISC2 Register
37. Revise Section 6.21 Comparator Control Register
38. Revise Section 6.28 PWMG0 control Register
39. Revise Section 6.29 PWMG0 Counter Upper Bound High Register
40. Revise Section 6.30 PWMG0 Counter Upper Bound Low Register
41. Revise Section 6.31 PWMG0 Duty Value High Register
42. Revise Section 6.32 PWMG0 Duty Value Low Register
43. Revise Section 6.38 ADC Control Register
44. Revise Section 6.40 ADC Regulator Control Register
45. Revise Section 6.43 PWMG1 control Register
46. Revise Section 6.49 PWMG2 control Register
©Copyright 2020, PADAUK Technology Co. Ltd
Page 7 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
47. Delete Chapter 7: Instructions symbol “word” and “pc0”
48. Revise Section 7.5 “swapc IO.n” Bit Operation Instruction
49. Add Chapter 8 Code Options
50. Revise Section 9.2.1 IO pin usage and setting
51. Revise Section 9.2.3 System clock switching
52. Add Section 9.2.6 IHRC
53. Revise Section 9.2.7 LVR
54. Revise Section 9.2.8 The result of Comparator controls the PWM output pins
55. Revise Section 9.2.10 BIT definition
56. Revise Section 9.2.11 Programming the PMS132/PMS132B
57. Revise Section 9.3 Using ICE
58. Revise all PWMG registers from ” R/W” to “WO”
1. Add PMS132B
2. Update company address & Tel No.
3. Open 32KHz EOSC mode
4. Revise Section 1.1, 1.2 and 1.3
5. Revise Chapter 3 Pin Assignment and Description (add AVDD and AGND)
6. Revise Section 4.1 AC/DC Device Characteristics
7. Update Section 4.3, 4.4, 4.5, 4.6, 4.12, 4.13, 4.14 and 4.15
8. Revise Section 5.4.1, 5.4.4 and 5.4.5
9. Revise Chapter 5 Comparator
10. Revise Fig.4: Hardware diagram of comparator
11. Revise Section 5.5.2 and 5.5.3
12. Revise Section 5.7 8-bit Timer (Timer2/Timer3) with PWM generation
13. Add Fig. 12: Comparator controls the output of PWM waveform
14. Revise Section 5.8.2 and 5.8.3
15. Revise Fig. 14: Hardware Diagram of 11-bit PWM Generator
1.03
2018/11/28 16. Revise Section 5.10 Interrupt
17. Revise Section 5.11.1 and 5.11.2
18. Revise Table 6: Differences in wake-up sources between Power-Save mode and
Power-Down mode
19. Revise Section 5.13.2 LVR reset
20. Revise Fig. 20: Analog Input Model
21. Revise Section 5.14.5 Using the ADC
22. Revise Section 6.2, 6.19, 6.28, 6.30, 6.45, 6.51,
23. Revise Section 7.8 Summary of Instructions Execution Cycle (Delete Section 9.2.9)
24. Add Section 7.10 BIT definition (Delete Section 9.2.10)
25. Revise Chapter 8 Code Options
26. Updated the link in Section 9.1
27. Revise Section 9.2.1 IO pin usage and setting
28. Revise Section 9.2.5: TIMER time out
29. Revise Section 9.2.9 Programming the PMS132/PMS132B
30. Revise Section 9.3 Using ICE
1. Revise Chapter 3, Chapter 8
2. Update 4.1 AC/DC Device Characteristics: IOL, IOH
3. Revise Section 4.12, 5.4.6, 5.7.1, 5.7.2, 5.7.3, 5.8, 5.8.3, 5.11.1, 5.11.3, 5.14.5, 6.3, 6.11,
6.12, 6.22, 6.48, 9.2.4, 9.2.9, 9.3
1.04
2020/06/02
4. Delete Section 4.16 and add Section 5.2.1
5. Add Section 5.8.4, Fig. 16, Table 5
©Copyright 2020, PADAUK Technology Co. Ltd
Page 8 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
1. Features
1.1. Special Features
General purpose series
Not supposed to use in AC RC step-down powered or high EFT requirement applications.
PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.
Operating temperature range: -20°C ~ 70°C
1.2. System Features
2KW OTP program memory
128 Bytes data RAM
One hardware 16-bit timer
Two hardware 8-bit timers with PWM generation
Three hardware 11-bit PWM generators (PWMG0, PWMG1 & PWMG2)
Provide one hardware comparator
Provide 1T 8x8 hardware multiplier
14 IO pins with optional pull-high resistor
Every IO pin can be configured to enable wake-up function
Band-gap circuit to provide 1.20V reference voltage
Up to 12-channel 12-bit resolution ADC with one channel comes from internal band-gap reference voltage
or 0.25*VDD
Provide ADC reference high voltage: external input, internal VDD, Band-gap(1.20V), 4V, 3V, 2V
Clock sources: internal high RC oscillator, internal low RC oscillator and external crystal oscillator
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast
Eight levels of LVR reset: 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V
Four selectable external interrupt pins
1.3. CPU Features
One processing unit operating mode
87 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer to provide adjustable stack level
Direct and indirect addressing modes for data access. Data memories are available for use as an index
pointer of Indirect addressing mode
IO space and memory space are independent
1.4. Package Information
PMS132/PMS132B-U06: SOT23-6 (60mil);
PMS132/PMS132B-S16A: SOP16A (150mil);
PMS132/PMS132B-S16B: SOP16B (150mil);
PMS132/PMS132B-2J16A: QFN4*4-16P
(0.65pitch);
PMS132/PMS132B-S08: SOP8 (150mil);
PMS132/PMS132B-M10: MSOP10 (118mil);
PMS132/PMS132B-4N10: DFN3*3-10P
(0.5pitch);
PMS132/PMS132B-1J16A: QFN3*3-16P
(0.5pitch)
PMS132/PMS132B-S14: SOP14 (150mil);
©Copyright 2020, PADAUK Technology Co. Ltd
Page 9 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
2. General Description and Block Diagram
The PMS132/PMS132B family is an ADC-Type, fully static, OTP-based CMOS 8-bit microcontroller. It employs
RISC architecture and all the instructions are executed in one cycle except that some instructions are two cycles
that handle indirect memory access.
2KW bits OTP program memory and 128 bytes data SRAM are inside, one up to 12 channels 12-bit ADC is built
inside the chip with one channel for internal band-gap reference voltage or 0.25*VDD. PMS132/PMS132B also
provides six hardware timers: one is 16-bit timer, two are 8-bit timers with PWM generation, and three hardware
11-bit timers with PWM generation are also included.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 10 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
3. Pin Assignment and Description
GND/AGND
VDD/AVDD
PA7/X1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PA0/AD10/CO/INT0/PG0PWM
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA3/AD8/CIN0-/TM2PWM/PG2PWM
PA6/X2
PA5/PRSTB/PG2PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
PB3/AD3/PG2PWM
PB1/AD1/Vref
PB4/AD4/TM2PWM/PG0PWM
PB0/AD0/INT1
PB5/AD5/INT0A/TM3PWM/PG0PWM
PB2/AD2/TM2PWM/PG2PWM
PB6/AD6/CIN4-/TM3PWM/PG1PWM
PMS132/PMS132B-S16A (SOP16A-150mil)
VDD/AVDD
GND/AGND
PA7/X1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PA0/AD10/CO/INT0/PG0PWM
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA6/X2
PA3/AD8/CIN0-/TM2PWM/PG2PWM
PB3/AD3/PG2PWM
PA5/PRSTB/PG2PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
PB4/AD4/TM2PWM/PG0PWM
PB1/AD1/Vref
PB0/AD0/INT1
PB5/AD5/INT0A/TM3PWM/PG0PWM
PB6/AD6/CIN4-/TM3PWM/PG1PWM
PB2/AD2/TM2PWM/PG2PWM
PMS132/PMS132B-S16B (SOP16B-150mil)
GND/AGND
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD/AVDD
PA7/X1
PA0/AD10/CO/INT0/PG0PWM
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA6/X2
PA5/PRSTB/PG2PWM
PA3/AD8/CIN0-/TM2PWM/PG2PWM
PB3/AD3/PG2PWM
PB1/AD1/Vref
PB7/AD7/CIN5-/TM3PWM/PG1PWM
PB4/AD4/TM2PWM/PG0PWM
PB5/AD5/INT0A/TM3PWM/PG0PWM
PB0/AD0/INT1
8
PMS132/PMS132B-S14 (SOP14-150mil)
©Copyright 2020, PADAUK Technology Co. Ltd
Page 11 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
16
14
15
13
VDD/AVDD
1
2
3
4
12 PB3/AD3/PG2PWM
PB1/AD1/Vref
PA7/X1
PA6/X2
11
10 PB0/AD0/INT1
PB2/AD2/TM2PWM/PG2PWM
PA5/PRSTB/PG2PWM
9
5
6
7
8
PMS132/PMS132B-2J16A(QFN4*4-16P-0.65pitch)
PMS132/PMS132B-1J16A(QFN3*3-16P-0.5pitch)
VDD/AVDD
PA6/X2
GND/AGND
1
2
3
4
5
10
9
PA0/AD10/CO/INT0/PG0PWM
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA3/AD8/CIN0-/TM2PWM/PG2PWM
PB1/AD1/Vref
PA5/PRSTB/PG2PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
PB4/AD4/TM2PWM/PG0PWM
8
7
6
PMS132/PMS132B-M10 (MSOP10-118mil)
1
2
3
4
5
10
9
VDD/AVDD
PA6/X2
GND/AGND
PA0/AD10/CO/INT0/PG0PWM
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA3/AD8/CIN0-/TM2PWM/PG2PWM
PB1/AD1/Vref
8
PA5/PRSTB/PG2PWM
7
PB7/AD7/CIN5-/TM3PWM/PG1PWM
PB4/AD4/TM2PWM/PG0PWM
6
PMS132/PMS132B-4N10 (DFN3*3-10P-0.5pitch)
©Copyright 2020, PADAUK Technology Co. Ltd
Page 12 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
VDD/AVDD
PA6/X2
GND/AGND
1
2
3
4
8
7
6
5
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA3/AD8/CIN0-/TM2PWM/PG2PWM
PB1/AD1/Vref
PA5/PRSTB/PG2PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
PMS132/PMS132B-S08 (SOP8-150mil)
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
1
6
5
4
PA3/AD8/CIN0-/TM2PWM/PG2PWM
VDD/AVDD
GND/AGND
PA6/X2
2
3
PA5/PRSTB/PG2PWM
PMS132/PMS132B-U06 (SOT23-6 60mil)
Pin Description
Pin Type &
Pin Name
Description
Buffer Type
The functions of this pin can be:
(1) Bit 7 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
IO
PA7 /
X1
ST /
(2) X1 when crystal oscillator is used.
CMOS
If this pin is used for crystal oscillator, bit 7 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 7 of padier register is “0”.
The functions of this pin can be:
(1) Bit 6 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
IO
PA6 /
X2
ST /
(2) X2 when crystal oscillator is used.
CMOS
If this pin is used for crystal oscillator, bit 6 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 6 of padier register is “0”.
The functions of this pin can be:
(1) Bit 5 of port A. It can be configured as digital input or open-drain output, with
pull-high resistor.
PA5 /
IO (OD)
ST /
PRSTB /
PG2PWM
(2) Hardware reset.
(3) Output of 11-bit PWM generator PWMG2. (ICE Does NOT support. )
This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”. Please put 33Ω resistor in
series to have high noise immunity when this pin is in input mode.
CMOS
©Copyright 2020, PADAUK Technology Co. Ltd
Page 13 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 4 of port A. It can be configured as digital input or two-state output, with
pull-high resistor by software independently
PA4 /
AD9 /
(2) Channel 9 of ADC analog input
(3) Plus input source of comparator
CIN+ /
IO
(4) Minus input source 1 of comparator
CIN1- /
INT1A /
PG1PWM
ST /
(5) External interrupt line 1A. It can be used as an external interrupt line 1. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting
CMOS /
Analog
(6) Output of 11-bit PWM generator PWMG1
When this pin is configured as analog input, please use bit 4 of register padier to
disable the digital input to prevent current leakage. The bit 4 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 3 of port A. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
PA3 /
AD8 /
(2) Channel 8 of ADC analog input
IO
(3) Minus input source 0 of comparator
ST /
CIN0- /
(4) PWM output from Timer2
CMOS /
Analog
TM2PWM /
PG2PWM
(5) Output of 11-bit PWM generator PWMG2
When this pin is configured as analog input, please use bit 3 of register padier to
disable the digital input to prevent current leakage. The bit 3 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
PA0 /
AD10 /
CO /
(2) Channel 10 of ADC analog input
IO
(3) Output of comparator
ST /
(4) Output of 11-bit PWM generator PWMG0
CMOS /
Analog
PG0PWM /
INT0
(5) External interrupt line 0. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting
The bit 0 of padier register can be set to “0” to disable wake-up from power-down by
toggling this pin.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 14 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 7 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
PB7 /
AD7 /
(2) Channel 7 of ADC analog input
IO
(3) Minus input source 5 of comparator
ST /
CIN5- /
(4) PWM output from Timer3
CMOS /
Analog
TM3PWM/
PG1PWM
(5) Output of 11-bit PWM generator PWMG1
When this pin is configured as analog input, please use bit 7 of register pbdier to
disable the digital input to prevent current leakage. The bit 7 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 6 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
PB6 /
AD6 /
(2) Channel 6 of ADC analog input
IO
(3) Minus input source 4 of comparator.
CIN4- /
ST /
(4) PWM output from Timer3
TM3PWM/
PG1PWM
CMOS /
Analog
(5) Output of 11-bit PWM generator PWMG1
When this pin is configured as analog input, please use bit 6 of register pbdier to
disable the digital input to prevent current leakage. The bit 6 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 5 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
(2) Channel 5 of ADC analog input
PB5 /
AD5 /
(3) PWM output from Timer3
IO
(4) Output of 11-bit PWM generator PWMG0.
ST /
TM3PWM /
PG0PWM /
INT0A
(5) External interrupt line 0A. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
CMOS /
Analog
When this pin is configured as analog input, please use bit 5 of register pbdier to
disable the digital input to prevent current leakage. The bit 5 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 15 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 4 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
PB4 /
AD4 /
IO
(2) Channel 4 of ADC analog input
ST /
(3) PWM output from Timer2
TM2PWM /
PG0PWM
CMOS /
Analog
(4) Output of 11-bit PWM generator PWMG0.
When this pin is configured as analog input, please use bit 4 of register pbdier to
disable the digital input to prevent current leakage. The bit 4 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 3 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
PB3 /
AD3 /
IO
(2) Channel 3 of ADC analog input
ST /
(3) Output of 11-bit PWM generator PWMG2
PG2PWM
CMOS /
Analog
When this pin is configured as analog input, please use bit 3 of register pbdier to
disable the digital input to prevent current leakage. The bit 3 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 2 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
PB2 /
AD2 /
IO
(2) Channel 2 of ADC analog input
ST /
(3) PWM output from Timer2
TM2PWM /
PG2PWM
CMOS /
Analog
(4) Output of 11-bit PWM generator PWMG2
When this pin is configured as analog input, please use bit 2 of register pbdier to
disable the digital input to prevent current leakage. The bit 2 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 1 of port B. It can be configured as digital input or two-state output, with
pull-high resistor independently by software
IO
PB1 /
AD1 /
Vref
(2) Channel 1 of ADC analog input
ST /
(3) External reference high voltage for ADC.
CMOS /
Analog
When this pin is configured as analog input, please use bit 1 of register pbdier to
disable the digital input to prevent current leakage. The bit 1 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 16 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 0 of port B. It can be configured as analog input, digital input or two-state
output, with pull-high resistor independently by software.
IO
(2) Channel 0 of ADC analog input.
PB0 /
AD0 /
INT1
ST /
(3) External interrupt line 1. It can be used as an external interrupt line 1. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
CMOS /
Analog
When this pin acts as analog input, please use bit 0 of register pbdier to disable the
digital input to prevent current leakage. If bit 0 of pbdier register is set to “0” to
disable digital input, wake-up from power-down by toggling this pin is also disabled.
VDD: digital positive power
VDD/
VDD /
AVDD
AVDD: Analog positive power
AVDD
VDD is the IC power supply while AVDD is the ADC power supply. AVDD and VDD
are double bonding internally and they have the same external pin.
GND: digital negative power
GND /
AGND
GND /
AGND
AGND: Analog negative power
GND is the IC ground pin while AGND is the ADC ground pin. AGND and GND are
double bonding internally and they have the same external pin.
Notes: IO: Input/Output; ST: Schmitt Trigger input; OD: Open Drain; Analog: Analog input pin
CMOS: CMOS voltage level
©Copyright 2020, PADAUK Technology Co. Ltd
Page 17 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
4. Device Characteristics
4.1. AC/DC Device Characteristics
All data are acquired under the conditions of VDD=5.0V, fSYS =2MHz unless noted.
Symbol
Description
Operating Voltage
Min
2.2
-5
Typ
Max
5.5
5
Unit
V
Conditions (Ta=25oC)
VDD
5.0
* Subject to LVR tolerance
LVR% Low Voltage Reset Tolerance
System clock (CLK)* =
IHRC/2
%
0
0
0
8M
4M
2M
V
V
V
DD ≧ 3.5V
DD ≧ 2.5V
DD ≧ 2.2V
fSYS
IHRC/4
IHRC/8
ILRC
Hz
55K
1
VDD =5.0V
mA fSYS=IHRC/16=1MIPS@5.0V
uA fSYS=ILRC=55KHz@3.3V
uA fSYS= 0Hz, VDD =5.0V
Operating Current
IOP
IPD
IPS
15
1
Power Down Current
(by stopsys command)
Power Save Current
(by stopexe command)
0.6
uA fSYS= 0Hz, VDD =3.3V
V
DD =5.0V; fSYS= ILRC
5
uA
V
Only ILRC module is enabled.
0
0.1 VDD
0.2 VDD
VDD
PA5
VIL
VIH
Input low voltage for IO lines
Input high voltage for IO lines
0
Others IO
PA5
0.8 VDD
0.7 VDD
V
VDD
Others IO
IO lines sink current
PA0, PA3, PA4,PB2,PB5,PB6
PB4, PB7 (Strong)
PB4, PB7 (Normal)
Others IO
20
38
20
13
IOL
mA VDD=5.0V, VOL=0.5V
IO lines drive current
PA5
0
IOH
PB4, PB7 (Strong)
PB4, PB7 (Normal)
Others IO
-32
-14
-12
mA VDD=5.0V, VOH=4.5V
VIN
Input voltage
-0.3
VDD +0.3
V
VDD +0.3≧VIN≧ -0.3
IINJ (PIN) Injected current on pin
mA
1
100
200
450
VDD =5.0V
RPH
Pull-high Resistance
KΩ
VDD =3.3V
VDD =2.2V
V
DD =2.2V ~ 5.5V
VBG
Band-gap Reference Voltage
1.145*
15.76*
15.20*
30
1.20*
16*
1.255*
16.24*
16.80*
V
-20oC <Ta<70oC*
25oC, VDD =2.2V~5.5V
Frequency of IHRC after
fIHRC
tINT
MHz
ns
V
DD =2.2V~5.5V,
calibration *
16*
0oC <Ta<70oC*
Interrupt pulse width
VDD = 5.0V
©Copyright 2020, PADAUK Technology Co. Ltd
Page 18 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Symbol
VADC
Description
Supply voltage for workable ADC
AD Input Voltage
Min
2.2
0
Typ
Max
VDD
VDD
Unit
V
Conditions (Ta=25oC)
VAD
V
ADrs
ADC resolution
12
0.9
0.8
2
bit
mA
@5V
ADcs
ADclk
ADC current consumption
@3V
ADC clock period
ADC conversion time
(TADCLK is the period of the
selected AD conversion clock)
ADC Differential NonLinearity
ADC Integral NonLinearity
ADC offset*
us
2.2V ~ 5.5V
tADCONV
16
TADCLK 12-bit resolution
AD DNL
AD INL
ADos
±2*
±4*
2
LSB
LSB
mV
@ VDD =3V
ADC reference high voltage
4V
3.90
2.93
1.95
1.5
4
3
2
4.10
3.07
2.05
VREFH
@ VDD =5V, 25 oC
3V
2V
VDR
RAM data retention voltage*
V
in stop mode
8k
misc[1:0]=00 (default)
misc[1:0]=01
16k
tWDT
Watchdog timeout period
TILRC
64k
misc[1:0]=10
misc[1:0]=11
256k
Wake-up time period for fast
wake-up
45
Where TILRC is the time
period of ILRC
tWUP
TILRC
Wake-up time period for normal
wake-up
3000
System boot-up period from
power-on for Normal boot-up
System boot-up period from
power-on for Fast boot-up
External reset pulse width
60
ms
us
VDD =5V
tSBP
600
VDD =5V
tRST
120
us
mV
V
@ VDD =5V
CPos
CPcm
CPspt
Comparator offset*
-
±10
±20
VDD -1.5
500
Comparator input common mode*
Comparator response time**
Stable time to change comparator
mode
0
100
2.5
20
ns
Both Rising and Falling
VDD = 3.3V
CPmc
CPcs
7.5
us
Comparator current consumption
uA
*These parameters are for design reference, not tested for each chip.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 19 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
4.2. Absolute Maximum Ratings
Supply Voltage ……………………………...... 2.2V ~ 5.5V
Input Voltage ………………………………….. -0.3V ~ VDD + 0.3V
Operating Temperature ................................. -20oC ~ 70oC
Junction Temperature ………………………… 150°C
Storage Temperature ………………………… -50°C ~ 125°C
4.3. Typical ILRC frequency vs. VDD and temperature
©Copyright 2020, PADAUK Technology Co. Ltd
Page 20 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
4.4. Typical IHRC frequency deviation vs. VDD(calibrated to 16MHz)
4.5. Typical ILRC Frequency vs. Temperature
©Copyright 2020, PADAUK Technology Co. Ltd
Page 21 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
4.6. Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)
4.7. Typical operating current vs. VDD @ system clock = ILRC/n
Conditions:
ON: ILRC, Band-gap, LVR; OFF: IHRC, EOSC, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
ILRC/n vs. VDD
60
50
40
30
ILRC/1
ILRC/4
20
10
0
ILRC/16
2
2.5
3
3.5
VDD (V)
4
4.5
5
5.5
©Copyright 2020, PADAUK Technology Co. Ltd
Page 22 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
4.8. Typical operating current vs. VDD @ system clock = IHRC/n
Conditions:
ON: Band-gap, LVR, IHRC; OFF: ILRC, EOSC, LVR, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
IHRC/n vs. VDD
1.8
IHRC/2
1.6
IHRC/4
1.4
1.2
1
IHRC/8
IHRC/16
IHRC/32
IHRC/64
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
VDD (V)
4
4.5
5
5.5
4.9. Typical operating current vs. VDD @ system clock = 4MHz EOSC / n
Conditions:
ON: EOSC, MISC.6 = 1, Band-gap, LVR; OFF: IHRC, ILRC, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
EOSC(4MHz)/n vs. VDD
2
1.8
EOSC/1
1.6
EOSC/2
1.4
EOSC/4
1.2
EOSC/8
1
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
©Copyright 2020, PADAUK Technology Co. Ltd
Page 23 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
4.10.Typical operating current vs. VDD @ system clock = 32KHz EOSC / n
Conditions:
ON: EOSC, MISC.6 = 1, Band-gap, LVR; OFF: IHRC, ILRC, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
EOSC(32KHz)/n vs. VDD
70
65
EOSC/1
EOSC/2
60
55
50
45
40
35
30
25
EOSC/4
EOSC/8
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
4.11.Typical operating current vs. VDD @ system clock = 1MHz EOSC / n
Conditions:
ON: EOSC, MISC.6 = 1, Band-gap, LVR; OFF: IHRC, ILRC, T16, TM2, TM3, ADC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
EOSC(1MHz)/n vs. VDD
1.2
EOSC/1
1
EOSC/2
EOSC/4
0.8
EOSC/8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
©Copyright 2020, PADAUK Technology Co. Ltd
Page 24 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
4.12.Typical IO driving current (IOH) and sink current (IOL)
©Copyright 2020, PADAUK Technology Co. Ltd
Page 25 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
©Copyright 2020, PADAUK Technology Co. Ltd
Page 26 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
4.13. Typical IO input high/low threshold voltage (VIH/VIL)
4.14. Typical resistance of IO pull high device
©Copyright 2020, PADAUK Technology Co. Ltd
Page 27 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
4.15. Typical power down current (IPD) and power save current (IPS)
©Copyright 2020, PADAUK Technology Co. Ltd
Page 28 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5. Functional Description
5.1. Program Memory - OTP
The OTP (One Time Programmable) program memory is used to store the program instructions to be executed.
The OTP program memory may contains the data, tables and interrupt entry. After reset, the initial address
0x000 is reserved for system using, so the program will start from 0x001 which is GOTO FPPA0 instruction
usually. The interrupt entry is 0x10 if used, the last 16 addresses are reserved for system using, like checksum,
serial number, etc. The OTP program memory for PMS132/PMS132B is a 2Kx14 bit that is partitioned as
Table 1. The OTP memory from address ‘0x7E8 to 0x7FF is for system using, address space from0x002 to
0x00F and from 0x011 to 0x7E7 are user program spaces.
Address
0x000
0x001
0x002
•
Function
System Using
GOTO FPPA0 instruction
User program
•
0x00F
0x010
0x011
•
User program
Interrupt entry address
User program
•
0x7E7
0x7E8
•
User program
System Using
•
0x7FF
System Using
Table 1: Program Memory Organization
5.2. Boot Procedure
POR (Power-On-Reset) is used to reset PMS132/PMS132B when power up. The boot up time can be optional
fast or normal. Time for fast boot-up is about 45 ILRC clock cycles whereas 3000 ILRC clock cycles for normal
boot-up. Customer must ensure the stability of supply voltage after power up no matter which option is chosen,
the power up sequence is shown in the Fig. 1 and tSBP is the boot-up time.
VDD
t
SBP
POR
Program
Execution
Boot up from Power-On Reset
Fig.1: Power-Up Sequence
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.2.1. Timing charts for reset conditions
LVR level
VDD
LVR
SBP
t
Program
Execution
Boot up from LVR detection
VDD
t
SBP
WD
Time Out
Program
Execution
Boot up from Watch Dog Time Out
VDD
Reset#
t
SBP
Program
Execution
Boot up from Reset Pad reset
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.3. Data Memory - SRAM
The access of data memory can be byte or bit operation. Besides data storage, the SRAM data memory is also
served as data pointer of indirect access method and the stack memory.
The stack memory is defined in the data memory. The stack pointer is defined in the stack pointer register; the
depth of stack memory of each processing unit is defined by the user. The arrangement of stack memory fully
flexible and can be dynamically adjusted by the user.
For indirect memory access mechanism, the data memory is used as the data pointer to address the data byte.
All the data memory could be the data pointer; it’s quite flexible and useful to do the indirect memory access.
Since the data width is 8-bit, all the 128 bytes data memory of PMS132/PMS132B can be accessed by indirect
access mechanism.
5.4. Oscillator and clock
There are three oscillator circuits provided by PMS132/PMS132B: external crystal oscillator (EOSC), internal
high RC oscillator (IHRC) and internal low RC oscillator (ILRC), and these three oscillators are enabled or
disabled by registers eoscr.7, clkmd.4 and clkmd.2 independently. User can choose one of these three
oscillators as system clock source and use clkmd register to target the desired frequency as system clock to
meet different applications.
Oscillator Module
EOSC
Enable/Disable
eoscr.7
IHRC
clkmd.4
ILRC
clkmd.2
Table 2: Three oscillation circuits
5.4.1. Internal High RC oscillator and Internal Low RC oscillator
After boot-up, the IHRC and ILRC oscillators are enabled. The frequency of IHRC can be calibrated to
eliminate process variation by ihrcr register; normally it is calibrated to 16MHz. Please refer to the
measurement chart for IHRC frequency verse VDD and IHRC frequency verse temperature.
The frequency of ILRC will vary by process, supply voltage and temperature, please refer to DC specification
and do not use for accurate timing application.
5.4.2. Chip calibration
The IHRC frequency and band-gap reference voltage may be different chip by chip due to manufacturing
variation, PMS132/PMS132B provide the IHRC frequency calibration to eliminate this variation, and this
function can be selected when compiling user’s program and the command will be inserted into user’s program
automatically. The calibration command is shown as below:
.ADJUST_IC SYSCLK=IHRC/(p1), IHRC=(p2)MHz, VDD=(p3)V;
Where, p1=2, 4, 8, 16, 32; In order to provide different system clock.
p2=14 ~ 18; In order to calibrate the chip to different frequency, 16MHz is the usually one.
p3=2.5 ~ 5.5; In order to calibrate the chip under different supply voltage.
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.4.3. IHRC Frequency Calibration and System Clock
During compiling the user program, the options for IHRC calibration and system clock are shown as Table 3:
SYSCLK
○ Set IHRC / 2
○ Set IHRC / 4
○ Set IHRC / 8
○ Set IHRC / 16
○ Set IHRC / 32
○ Set ILRC
CLKMD
IHRCR
Description
= 34h (IHRC / 2)
= 14h (IHRC / 4)
= 3Ch (IHRC / 8)
= 1Ch (IHRC / 16)
= 7Ch (IHRC / 32)
= E4h (ILRC / 1)
No change
Calibrated IHRC calibrated to 16MHz, CLK=8MHz (IHRC/2)
Calibrated IHRC calibrated to 16MHz, CLK=4MHz (IHRC/4)
Calibrated IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)
Calibrated IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)
Calibrated IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)
Calibrated IHRC calibrated to 16MHz, CLK=ILRC
○ Disable
No Change IHRC not calibrated, CLK not changed
Table 3: Options for IHRC Frequency Calibration
Usually, .ADJUST_IC will be the first command after boot up, in order to set the target operating frequency
whenever starting the system. The program code for IHRC frequency calibration is executed only one time that
occurs in writing the codes into OTP memory; after then, it will not be executed again. If the different option for
IHRC calibration is chosen, the system status is also different after boot. The following shows the status of
PMS132/PMS132B for different option:
(1) .ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0x34：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/2 = 8MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(2) .ADJUST_IC
SYSCLK=IHRC/4, IHRC=16MHz, VDD=3.3V
After boot up, CLKMD = 0x14：
IHRC frequency is calibrated to 16MHz@VDD=3.3V and IHRC module is enabled
System CLK = IHRC/4 = 4MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(3) .ADJUST_IC
SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V
After boot up, CLKMD = 0x3C：
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/8 = 2MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(4) .ADJUST_IC
SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.5V
After boot up, CLKMD = 0x1C：
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/16 = 1MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(5) .ADJUST_IC
SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0x7C：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/32 = 500KHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
(6) .ADJUST_IC
SYSCLK=ILRC, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0XE4：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is disabled
System CLK = ILRC
Watchdog timer is enabled, ILRC is enabled, PA5 is input mode
(7) .ADJUST_IC
DISABLE
After boot up, CLKMD is not changed (Do nothing)：
IHRC is not calibrated and IHRC module is to be enabled or disabled by Boot-up Time.
System CLK = ILRC or IHRC/64 (by Boot-up_Time)
Watchdog timer is enabled, ILRC is enabled, PA5 is in input mode.
5.4.4. External Crystal Oscillator
If crystal oscillator is used, a crystal or resonator is required between X1 and X2. Fig.2 shows the hardware
connection under this application; the range of operating frequency of crystal oscillator can be from 32 KHz to
4MHz, depending on the crystal placed on; higher frequency oscillator than 4MHz is NOT supported.
(Select driving current for oscillator)
eoscr[6:5]
(Enable crystal oscillator)
eoscr.7
C1
PA7/X1
System clock = EOSC
PA6/X2
C2
The values of C1 and C2 should depend on
the specification of crystal.
Fig.2: Connection of crystal oscillator
Besides crystal, external capacitor and options of PMS132/PMS132B should be fine tuned in eoscr (0x0a)
register to have good sinusoidal waveform. The eoscr.7 is used to enable crystal oscillator module, eoscr.6 and
eoscr.5 are used to set the different driving current to meet the requirement of different frequency of crystal
oscillator:
eoscr.[6:5]=01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
eoscr.[6:5]=10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
eoscr.[6:5]=11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
Table 4 shows the recommended values of C1 and C2 for different crystal oscillator; the measured start-up
time under its corresponding conditions is also shown. Since the crystal or resonator had its own characteristic,
the capacitors and start-up time may be slightly different for different type of crystal or resonator, please refer to
its specification for proper values of C1 and C2.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 33 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Measured
Frequency
C1
C2
Conditions
Start-up time
6ms
4MHz
1MHz
32KHz
4.7pF
10pF
22pF
4.7pF
10pF
22pF
(eoscr[6:5]=11, misc.6=0)
(eoscr[6:5]=10, misc.6=0)
(eoscr[6:5]=01, misc.6=0)
11ms
450ms
Table 4: Recommend values of C1 and C2 for crystal and resonator oscillators
When using the crystal oscillator, user must pay attention to the stable time of oscillator after enabling it, the
stable time of oscillator will depend on frequency, crystal type, external capacitor and supply voltage. Before
switching the system to the crystal oscillator, user must make sure the oscillator is stable; the reference
program is shown as below:
void
{
FPPA0 (void)
. ADJUST_IC SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V
$
EOSCR
Enable, 4MHz;
// EOSCR = 0b110_00000;
$ T16M
EOSC， /1， BIT13;
// while T16.Bit13 0 => 1, Intrq.T16 => 1
// suppose crystal EOSC is stable
WORD
stt16
count =
count;
0;
Intrq.T16
=
0;
while (! Intrq.T16) NULL;
// count from 0x0000 to 0x2000, then trigger INTRQ.T16
// switch system clock to EOSC;
//disable IHRC
clkmd=
0xb4;
clkmd.4 = 0;
...
Please notice that the crystal oscillator should be fully turned off before entering the power-down mode, in
order to avoid unexpected wakeup event.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 34 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.4.5. System Clock and LVR level
The clock source of system clock comes from EOSC, IHRC and ILRC, the hardware diagram of system clock
in the PMS132/PMS132B is shown as Fig.3.
clkmd[7:5]
÷2, ÷4, ÷8,
IHRC
clock
÷16, ÷32, ÷64
System
clock
CLK
M
U
X
EOSC
clock
÷1, ÷2, ÷4, ÷8
ILRC
÷1, ÷4, ÷16
clock
Fig.3: Options of System Clock
User can choose different operating system clock depends on its requirement; the selected operating system
clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be
selected during compilation, and the lowest LVR levels can be chosen for different operating frequencies.
Please refer to Section 4.1.
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.4.6. System Clock Switching
After IHRC calibration, user may want to switch system clock to a new frequency or may switch system clock at
any time to optimize the system performance and power consumption. Basically, the system clock of
PMS132/PMS132B can be switched among IHRC, ILRC and EOSC by setting the clkmd register at any time;
system clock will be the new one after writing to clkmd register immediately. Please notice that the original
clock module can NOT be turned off at the same time as writing command to clkmd register. The examples are
shown as below and more information about clock switching, please refer to the “Help” -> “Application Note” ->
“IC Introduction” -> “Register Introduction” -> CLKMD”.
Case 1: Switching system clock from ILRC to IHRC/2
…
//
//
//
//
system clock is ILRC
CLKMD.4
CLKMD
// CLKMD.2
…
=
=
=
1;
turn on IHRC first to improve anti-interference ability
switch to IHRC/2, ILRC CAN NOT be disabled here
if need, ILRC CAN be disabled at this time
0x34；
0；
Case 2: Switching system clock from ILRC to EOSC
…
//
//
//
system clock is ILRC
CLKMD
CLKMD.2
…
=
=
0xA6；
0；
switch to IHRC, ILRC CAN NOT be disabled here
ILRC CAN be disabled at this time
Case 3: Switching system clock from IHRC/2 to ILRC
…
//
//
//
system clock is IHRC/2
CLKMD
CLKMD.4
…
=
=
0xF4；
0；
switch to ILRC, IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
Case 4: Switching system clock from IHRC/2 to EOSC
…
//
//
//
system clock is IHRC/2
CLKMD
CLKMD.4
…
=
=
0XB0；
0；
switch to EOSC, IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
Case 5: Switching system clock from IHRC/2 to IHRC/4
…
//
//
system clock is IHRC/2, ILRC is enabled here
CLKMD
…
=
0X14；
switch to IHRC/4
Case 6: System may hang if it is to switch clock and turn off original oscillator at the same time
…
//
system clock is ILRC
CLKMD
=
0x30；
//
CAN NOT switch clock from ILRC to IHRC/2 and
turn off ILRC oscillator at the same time
©Copyright 2020, PADAUK Technology Co. Ltd
Page 36 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.5. Comparator
One hardware comparator is built inside the PMS132/PMS132B; Fig.4 shows its hardware diagram. It can
compare signals between two pins or with either internal reference voltage Vinternal R or internal band-gap
reference voltage. The two signals to be compared, one is the plus input and the other one is the minus input.
For the minus input of comparator can be PA3, PA4, Internal band-gap 1.20 volt, PB6, PB7 or Vinternal R selected
by bit [3:1] of gpcc register, and the plus input of comparator can be PA4 or Vinternal R selected by bit 0 of gpcc
register.
The comparator result can be selected through gpcs.7 to forcibly output to PA0 whatever input or output state.
It can be a direct output or sampled by Timer2 clock (TM2_CLK) which comes from Timer2 module. The output
polarity can be also inverted by setting gpcc.4 register, the comparator output can be used to request interrupt
service or read through gpcc.6.
16 stages
VDD
gpcs.5=1
gpcs.4=0
gpcs.4=1
gpcs.5=0
MUX
gpcs[3:0]
Vinternal R
gpcc[3:1]
PA3/CIN0-
PA4/CIN1-
Band-gap
000
001 M
gpcc.4
To request interrupt
gpcc.6
010 U
011 X
100
X
O
R
-
PB6/CIN4-
PB7/CIN5-
M
U
X
101
+
D
F
F
To
PA0
0
Timer 2
clock
MUX
1
PA4/CIN+
gpcc.0
TM2_CLK
gpcc.5
gpcs.7
Fig.4: Hardware diagram of comparator
©Copyright 2020, PADAUK Technology Co. Ltd
Page 37 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.5.1 Internal reference voltage (Vinternal R
)
The internal reference voltage Vinternal R is built by series resistance to provide different level of reference
voltage, bit 4 and bit 5 of gpcs register are used to select the maximum and minimum values of Vinternal R
and bit [3:0] of gpcs register are used to select one of the voltage level which is deivided-by-16 from the
defined maximum level to minimum level. Fig.5 to Fig.8 shows four conditions to have different reference
voltage Vinternal R. By setting the gpcs register, the internal reference voltage Vinternal R can be ranged from
(1/32)*VDD to (3/4)*VDD.
Case 1 : gpcs.5=0 & gpcs.4=0
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/4) VDD ~ (1/4) VDD + (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
4
(n+1)
32
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig.5: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=0
Case 2 : gpcs.5=0 & gpcs.4= 1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (2/3) VDD ~ (1/24) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
24
Fig.6: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=1
©Copyright 2020, PADAUK Technology Co. Ltd
Page 38 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Case 3 : gpcs.5=1 & gpcs.4= 0
16 stages
VDD
8R
8R
8R
gpcs.5=1
gpcs.4=0
gpcs.4=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/5) VDD ~ (1/5) VDD + (1/40) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
5
(n+1)
40
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig.7: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=0
Case 4 : gpcs.5=1 & gpcs.4=1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (1/2) VDD ~ (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
32
Fig.8: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=1
©Copyright 2020, PADAUK Technology Co. Ltd
Page 39 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.5.2
Using the comparator
Case I:
Choosing PA3 as minus input and Vinternal R with (18/32)*VDD voltage level as plus input. Vinternal R is
configured as he above Figure “gpcs[5:4] = 2b’00” and gpcs [3:0] = 4b’1001 (n=9) to have Vinternal R
(1/4)*VDD + [(9+1)/32]*VDD = [(9+9)/32]*VDD = (18/32)*VDD.
=
gpcs = 0b0_0_00_1001;
// Vinternal R = VDD*(18/32)
gpcc = 0b1_0_0_0_000_0;
padier = 0bxxxx_0_xxx;
// enable comp, - input: PA3, + input: Vinternal R
// disable PA3 digital input to prevent leakage current
or
$ GPCS
$ GPCC
V
DD*18/32;
Enable, N_PA3, P_R;
// - input: N_xx，+ input: P_R(Vinternal R
)
PADIER = 0bxxxx_0_xxx;
Case 2:
Choosing Vinternal R as minus input with (22/40)*VDD voltage level and PA4 as plus input, the comparator
result will be inversed and then output to PA0. Vinternal R is configured as the above Figure “gpcs[5:4] =
2b’10” and gpcs [3:0] = 4b’1101 (n=13) to have Vinternal R = (1/5)*VDD + [(13+1)/40]*VDD = [(13+9)/40]*VDD
(22/40)*VDD.
=
gpcs = 0b1_0_10_1101;
gpcc = 0b1_0_0_1_011_1;
padier = 0bxxx_0_xxxx;
// output to PA0, Vinternal R = VDD*(22/40)
// Inverse output, - input: Vinternal R, + input: PA4
// disable PA4 digital input to prevent leakage current
or
$ GPCS
$ GPCC
Output, VDD*22/40;
Enable, Inverse, N_R, P_PA4; // - input: N_R(Vinternal R)，+ input: P_xx
PADIER = 0bxxx_0_xxxx;
Note: When selecting output to PA0 output, GPCS will affect the PA3 output function in ICE. Though the IC is
fine, be careful to avoid this error during emulation.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 40 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.5.3 Using the comparator and band-gap 1.20V
The internal band-gap module can provide 1.20 volt, it can measure the external supply voltage level. The
band-gap 1.20 volt is selected as minus input of comparator and Vinternal R is selected as plus input, the
supply voltage of Vinternal R is VDD, the VDD voltage level can be detected by adjusting the voltage level of
Vinternal R to compare with band-gap. If N (gpcs[3:0] in decimal) is the number to let Vinternal R closest to
band-gap 1.20 volt, the supply voltage VDD can be calculated by using the following equations:
For using Case 1: VDD = [ 32 / (N+9) ] * 1.20 volt ;
For using Case 2: VDD = [ 24 / (N+1) ] * 1.20 volt ;
For using Case 3: VDD = [ 40 / (N+9) ] * 1.20 volt ;
For using Case 4: VDD = [ 32 / (N+1) ] * 1.20 volt ;
Case 1:
$ GPCS VDD*12/40;
// 4.0V * 12/40 = 1.2V
$ GPCC Enable, BANDGAP, P_R; // - input: BANDGAP, + input: P_R(Vinternal R
)
….
if (GPC_Out)
// or GPCC.6
{
//
//
when VDD﹥4V
}
else
{
}
when VDD﹤4V
©Copyright 2020, PADAUK Technology Co. Ltd
Page 41 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.6 16-bit Timer (Timer16)
A 16-bit hardware timer (Timer16) is implemented in the PMS132/PMS132B, the clock sources of Timer16
may come from system clock (CLK), clock of external crystal oscillator (EOSC), internal high RC oscillator
(IHRC), internal low RC oscillator (ILRC), PA4 and PA0, a multiplex is used to select clock output for the clock
source. Before sending clock to the counter16, a pre-scaling logic with divided-by-1, 4, 16, and 64 is used for
wide range counting. The 16-bit counter performs up-counting operation only, the counter initial values can be
stored from memory by stt16 instruction and the counting values can be loaded to memory by ldt16 instruction.
A selector is used to select the interrupt condition of Timer16, whenever overflow occurs, the Timer16 interrupt
can be triggered. The hardware diagram of Timer16 is shown as Fig.9. The interrupt source of Timer16 comes
from one of bit 8 to 15 of 16-bit counter, and the interrupt type can be rising edge trigger or falling edge trigger
which is specified in the bit 5 of integs register (IO address 0x0C).
PA4
Fig.9: Hardware diagram of Timer16
When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three parameters
to define the Timer16; 1st parameter is used to define the clock source of Timer16, 2nd parameter is used to
define the pre-scalar and the last one is to define the interrupt source. The detail description is shown as
below:
T16M
IO_RW
0x06
$ 7~5:STOP, SYSCLK, X, PA4_F, IHRC, EOSC, ILRC, PA0_F
$ 4~3:/1, /4, /16, /64
// 1st par.
// 2nd par.
// 3rd par.
$ 2~0:BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15
©Copyright 2020, PADAUK Technology Co. Ltd
Page 42 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
User can define the parameters of T16M based on system requirement, some examples are shown below and
more examples please refer to “Help Application Note IC Introduction Register Introduction T16M” in
IDE utility.
$ T16M SYSCLK, /64, BIT15;
// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1
// if using System Clock = IHRC / 2 = 8 MHz
// SYSCLK/64 = 8 MHz/64 = 125KHz, about every 512 mS to generate INTRQ.2=1
$ T16M EOSC, /1, BIT13;
// choose (EOSC/1) as clock source, every 2^14 clocks to generate INTRQ.2=1
// if EOSC=32768 Hz, 32768 Hz/(2^14) = 2Hz, every 0.5S to generate INTRQ.2=1
$ T16M PA0_F, /1, BIT8;
// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1
// receiving every 512 times PA0 to generate INTRQ.2=1
$ T16M STOP;
// stop Timer16 counting
If Timer16 is operated at free running, the frequency of interrupt can be described as below:
FINTRQ_T16M = Fclock source ÷ P ÷ 2n+1
Where, F is the frequency of selected clock source to Timer16;
P is the selection of t16m [4:3]; (1, 4, 16, 64)
N is the nth bit selected to request interrupt service, for example: n=10 if bit 10 is selected.
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.7 8-bit Timer (Timer2/Timer3) with PWM generation
Two 8-bit hardware timers (Timer2 and Timer3) with PWM generation are implemented in the
PMS132/PMS132B. The following descriptions thereinafter are for Timer2 only. It is because Timer3 have same
structure with Timer2. Please refer to Fig.10 shown the hardware diagram of Timer2, the clock sources of
Timer2 may come from system clock, internal high RC oscillator (IHRC), internal low RC oscillator (ILRC),
external crystal oscillator (EOSC), PA0, PB0,PA4 and comparator. Bit [7:4] of register tm2c are used to select
the clock of Timer2. If IHRC is selected for Timer2 clock source, the clock sent to Timer2 will keep running when
using ICE in halt state. According to the setting of register tm2c[3:2], Timer2 output can be selectively output to
PB2, PA3 or PB4(Timer3 count output can be selected as PB5, PB6 or PB7). At this point, regardless of
whether PX.x is the input or output state, Timer2( or Timer3) signal will be forced to output. A clock pre-scaling
module is provided with divided-by- 1, 4, 16, and 64 options, controlled by bit [6:5] of tm2s register; one scaling
module with divided-by-1~31 is also provided and controlled by bit [4:0] of tm2s register. In conjunction of
pre-scaling function and scaling function, the frequency of Timer2 clock (TM2_CLK) can be wide range and
flexible.
The Timer2 counter performs 8-bit up-counting operation only; the counter values can be set or read back by
tm2ct register. The 8-bit counter will be clear to zero automatically when its values reach for upper bound
register, the upper bound register is used to define the period of timer or duty of PWM. There are two operating
modes for Timer2: period mode and PWM mode; period mode is used to generate periodical output waveform
or interrupt event; PWM mode is used to generate PWM output waveform with optional 6-bit to 8-bit PWM
resolution, Fig.11 shows the timing diagram of Timer2 for both period mode and PWM mode.
Fig.10: Timer2 hardware diagram
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Time out and
Time out and
Time out and
Interrupt request
Interrupt request
Interrupt request
Counter
0xFF
bound
Counter
0xFF
Counter
0x3F
bound
bound
Time
Time
Time
Time
Time
Event Trigger
Event Trigger
Event Trigger
Output-pin
Output-pin
Output-pin
Time
Mode 0 – Period Mode
Mode 1 – 8-bit PWM Mode
Mode 1 – 6-bit PWM Mode
Fig.11: Timing diagram of Timer2 in period mode and PWM mode (tm2c.1=1)
A Code Option GPC_PWM is for the applications which need the generated PWM waveform to be controlled
by the comparator result. If the Code Option GPC_PWM is selected, the PWM output stops while the
comparator output is 1 and then the PWM output turns on while the comparator output goes back to 0, as
shown in Fig. 12.
PWM Output
Comparator
Output
Fig.12：Comparator controls the output of PWM waveform
5.7.1 Using the Timer2 to generate periodical waveform
If periodical mode is selected, the duty cycle of output is always 50%; its frequency can be summarized as
below:
Frequency of Output = Y ÷ [2 × (K+1) × S1 × (S2+1) ]
Where,
Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1 = tm2s[6:5] : pre-scalar (S1= 1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2= 0 ~ 31)
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Example 1:
Example 2:
Example 3:
Example 4:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ [ 2 × (127＋1) × 1 × (0＋1) ] = 31.25KHz
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s[7:0] = 0b0111_11111, S1=64 , S2 = 31
frequency = 8MHz ÷ ( 2 × (127＋1) × 64 × (31＋1) ) =15.25Hz
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_1111, K=15
tm2s = 0b0000_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (15＋1) × 1 × (0＋1) ) = 250KHz
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_0001, K=1
tm2s = 0b0000_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (1＋1) × 1 × (0＋1) ) =2MHz
The sample program for using the Timer2 to generate periodical waveform from PA3 is shown as below:
Void FPPA0 (void)
{
. ADJUST_IC SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
…
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, period mode
tm2c = 0b0001_10_0_0;
while(1)
{
nop;
}
}
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.7.2 Using the Timer2 to generate 8-bit PWM waveform
If 8-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=0, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [256 × S1 × (S2+1) ]
Duty of Output = [( K＋1 ) ÷ 256]×100%
Where, Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1= tm2s[6:5] : pre-scalar (S1= 1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2= 0 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0111_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 256 × 64 × (31+1) ) = 15.25Hz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b1111_1111, K=255
tm2s = 0b0000_00000, S1=1, S2=0
PWM output keep high
duty of output = [(255+1) ÷ 256] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_1001, K = 9
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(9+1) ÷ 256] × 100% = 3.9%
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
The sample program for using the Timer2 to generate PWM waveform from PA3 is shown as below:
void
{
FPPA0 (void)
.ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
wdreset;
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, PWM mode
tm2c = 0b0001_10_1_0;
while(1)
{
nop;
}
}
5.7.3 Using the Timer2 to generate 6-bit PWM waveform
If 6-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=1, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [64 × S1 × (S2+1) ]
Duty of Output = [( K＋1 ) ÷ 64] × 100%
Where, tm2c[7:4] = Y : frequency of selected clock source
tm2b[7:0] = K : bound register in decimal
tm2s[6:5] = S1 : pre-scalar (S1= 1, 4, 16, 64)
tm2s[4:0] = S2 : scalar register in decimal (S2= 0 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(31+1) ÷ 64] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1111_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 64 × 64 × (31+1) ) = 61.03 Hz
duty of output = [(31+1) ÷ 64] × 100% = 50%
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Page 48 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0011_1111, K=63
tm2s = 0b1000_00000, S1=1, S2=0
PWM output keep high
duty of output = [(63+1) ÷ 64] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_0000, K=0
tm2s = 0b1000_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(0+1) ÷ 64] × 100% =1.5%
5.8 11-bit PWM Generator
Three 11-bit hardware PWM generators (PWMG0, PWMG1 & PWMG2) are implemented in the
PMS132/PMS132B. The following descriptions thereinafter are for PWMG0 only. It is because PWMG1 &
PWMG2 have the same structures and functions with PWMG0.
Their individual outputs are listed as below:
PWMG0 – PA0, PB4, PB5
PWMG1 – PA4, PB6, PB7
PWMG2 – PA3, PA5, PB2, PB3 (Note: PA5 open drain output only, user need to enable the internal pull-high
resistor or add an external pull-high resistor when using, and ICE does not support PA5 PWM function.)
5.8.1 PWM Waveform
A PWM output waveform (Fig.13) has a time-base (TPeriod = Time of Period) and a time with output high level
(Duty Cycle). The frequency of the PWM output is the inverse of the period (fPWM = 1/TPeriod), the resolution of the
PWM is the clock count numbers for one period (N bits resolution, 2N × Tclock = TPeriod).
Period
Duty Cycle
‧‧‧‧‧‧‧
clock
N bit resolution
Fig.13: PWM Output Waveform
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.8.2 Hardware and Timing Diagram
Three 11-bit hardware PWM generators are built inside the PMS132/PMS132B; Fig.14 shows the hardware
diagram PWMG0 as an example. The clock source can be IHRC or system clock. Depending on the setting of
register PWMC, PWM can be optionally output to PA0, PB4 or PB5. At this point, PWM signal will be forced to
output regardless of whether PX.x is the input or output state. The period of PWM waveform is defined in the
PWM upper bond high and low registers, the duty cycle of PWM waveform is defined in the PWM duty high and
low registers. Users can also use the comparator result to control the output of the PWM waveform by using the
GPC_PWM code option.
Fig.14: Hardware Diagram of 11-bit PWM Generator
0x7FF
Counter_Bound[10:0]
11 bit
Counter
Duty[10:0]
Time
Time
Output
bit PWM generation
Output Timing Diagram for 11-
Fig.15: Output Timing Diagram of 11-bit PWM Generator
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.8.3 Equations for 11-bit PWM Generator
PWM Frequency FPWM = F clock source ÷ [ P × (K + 1) × (CB10_1 + 1) ]
PWM Duty(in time) = (1 / FPWM) × ( DB10_1 + DB0 × 0.5 + 0.5) ÷ (CB10_1 + 1)
PWM Duty(in percentage) = ( DB10_1 + DB0 × 0.5 + 0.5) ÷ (CB10_1 + 1) × 100%
Where,
P = PWMGxS [6:5] : pre-scalar (P = 1, 4, 16, 64)
K = PWMGxS [4:0] : scalar in decimal (K =0 ~ 31)
DB10_1 = Duty_Bound[10:1] = {PWMGxDTH[7:0], PWMGxDTL[7:6]}, duty bound
DB0 = Duty_Bound[0] = PWMGxDTL[5]
CB10_1 = Counter_Bound[10:1] = {PWMGxCUBH[7:0], PWMGxCUBL[7:6]}, counter bound
5.8.4 Complementary PWM with Dead Zones
Users can use two 11bit PWM generators to output two complementary PWM waveforms with dead zones.
Take PWMG0 output PWM0, PWMG1 output PWM1 as an example, the program reference is as follows.
In addition, Timer2 and Timer3 can also output 8-bit PWM waveforms with complementary dead zones of
two bands. The principle is similar to this, and it will not be described in detail.
#definedead_zone_R
#definedead_zone_F
2
3
//
//
Control dead-time before rising edge of PWM1
Control dead-time after falling edge of PWM1
void
{
FPPA0 (void)
SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V;
.ADJUST_IC
//......
Byte duty
Byte _duty =
=
60;
//
Represents the duty cycle of PWM0
100 - duty; //
Represents the duty cycle of PWM1
//************** Set the counter upper bound and duty cycle **************
PWMG0DTL
PWMG0DTH
PWMG0CUBL
PWMG0CUBH
=
=
=
=
0x00;
_duty;
0x00;
100;
PWMG1DTL
PWMG1DTH
=
=
0x00;
_duty - dead_zone_F;
//
Use duty cycle to adjust the dead-time after the falling edge of PWM1
PWMG1CUBL
PWMG1CUBH
=
=
0x00;
100; // The above values are assigned before enable PWM output
//******************** PWM out control *********************
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
$ PWMG0C Enable,Inverse,PA0,SYSCLK;
$ PWMG0S INTR_AT_DUTY,/1,/1;
//PWMG0 output the PWM0 waveform to PA0
.delay
dead_zone_R;
// Use delay to adjust the dead-time before the rising edge of PWM1
$ PWMG1C Enable, PA4, SYSCLK; //PWMG1 output the PWM1 waveform to PA4
$ PWMG1S INTR_AT_DUTY, /1, /1;
//***** Note: for the output control part of the program, the code sequence can not be moved ******//
While(1)
{nop; }
}
The PWM0 / PWM1 waveform obtained by the above program is shown in Fig. 16.
Dead-Time
PWM1
Fig. 16: Two complementary PWM waveforms with dead zones
Users can modify the dead_zone_R and dead_zone_F values in the program to adjust the dead-time.
Table 5 provides data corresponding to different dead-time for users' reference. Where, if dead-time = 4us,
then there are dead zones of 4us before and after PWM1 high level.
dead-time (us)
dead_zone_R
dead_zone_F
4 (minimum)
0
2
2
3
4
5
6
7
6
8
4
10
12
14
6
8
10
Table 5: The value of dead-time for reference
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Dead_zone_R and dead_zone_F need to work together to get an ideal dead-time. If user wants to adjust
other dead-time, please note that dead_zone_R and dead_zone_F need to meet the following criteria:
dead_zone_R
1 / 2 / 3
4 / 5 / 6 / 7
8 / 9
dead_zone_F
> 1
> 2
> 3
...
...
5.9 WatchDog Timer
The watchdog timer (WDT) is a counter with clock coming from ILRC. WDT can be cleared by power-on-reset
or by command wdreset at any time. There are four different timeout periods of watchdog timer to be chosen
by setting the misc register, it is:
8k ILRC clocks period if register misc[1:0]=00 (default)
16k ILRC clocks period if register misc[1:0]=01
64k ILRC clocks period if register misc[1:0]=10
256k ILRC clocks period if register misc[1:0]=11
The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user
should reserve guard band for save operation. Besides, the watchdog period will also be shorter than expected
after Reset or Wakeup events. It is suggested to clear WDT by wdreset command after these events to ensure
enough clock periods before WDT timeout.
When WDT is timeout, PMS132/PMS132B will be reset to restart the program execution. The relative timing
diagram of watchdog timer is shown as Fig.17.
VDD
t
SBP
WD
Time Out
Program
Execution
Watch Dog Time Out Sequence
Fig.17: Sequence of Watch Dog Time Out
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.10 Interrupt
There are eight interrupt lines for PMS132/PMS132B:
External interrupt PA0/PB5
External interrupt PB0/PA4
ADC interrupt
Timer16 interrupt
GPC interrupt
PWMG0 interrupt
Timer2 interrupt
Timer3 interrupt
Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware
diagram of interrupt function is shown as Fig.18. All the interrupt request flags are set by hardware and cleared
by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending
on the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable
global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it.
The stack memory for interrupt is shared with data memory and its address is specified by stack register sp.
Since the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can
use pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack memory.
Since the stack memory is shared with data memory, the stack position and level are arranged by the compiler
in Mini-C project. When defining the stack level in ASM project, users should arrange their locations carefully to
prevent address conflicts.
Fig.18: Hardware diagram of interrupt controller
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
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8bit OTP MCU with 12-bit ADC
Once the interrupt occurs, its operation will be:
The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x010.
During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
Note: Even if INTEN=0, INTRQ will be still triggered by the interrupt source.
After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will be:
The program counter will be restored automatically from the stack memory specified by register sp.
New sp will be updated to sp-2.
Global interrupt will be enabled automatically.
The next instruction will be the original one before interrupt.
User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and four
bytes for two levels interrupt. For interrupt operation, the following sample program shows how to handle the
interrupt, noticing that it needs four bytes stack memory to handle interrupt and pushaf.
void
{
FPPA0
(void)
...
$
INTEN PA0;
// INTEN =1; interrupt request when PA0 level changed
// clear INTRQ
INTRQ
ENGINT
...
=
0;
// global interrupt enable
DISGINT
...
// global interrupt disable
}
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
void
{
Interrupt (void)
PUSHAF
// interrupt service routine
// store ALU and FLAG register
// If INTEN.PA0 will be opened and closed dynamically,
// user can judge whether INTEN.PA0 =1 or not.
// Example: If (INTEN.PA0 && INTRQ.PA0) {…}
// If INTEN.PA0 is always enable,
// user can omit the INTEN.PA0 judgement to speed up interrupt service routine.
If (INTRQ.PA0)
{
}
// Here for PA0 interrupt service routine
INTRQ.PA0 = 0;
...
// Delete corresponding bit (take PA0 for example)
...
// X : INTRQ = 0;
// It is not recommended to use INTRQ = 0 to clear all at the end of the
// interrupt service routine.
// It may accidentally clear out the interrupts that have just occurred
// and are not yet processed.
POPAF
// restore ALU and FLAG register
}
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.11 Power-Save and Power-Down
There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down
modes. ON mode is the state of normal operation with all functions ON, Power-Save mode (“stopexe”) is the
state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is used to
save power deeply. Therefore, Power-Save mode is used in the system which needs low operating power with
wake-up occasionally and Power-Down mode is used in the system which needs power down deeply with
seldom wake-up. Table 6 shows the differences in oscillator modules between Power-Save mode (“stopexe”)
and Power-Down mode (“stopsys”).
Differences in oscillator modules between STOPSYS and STOPEXE
IHRC
Stop
ILRC
Stop
EOSC
Stop
STOPSYS
STOPEXE
No Change
No Change
No Change
Table 6: Differences in oscillator modules between STOPSYS and STOPEXE
5.11.1 Power-Save mode (“stopexe”)
Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all
the oscillator modules active. For CPU, it stops executing; however, for Timer16, counter keep counting if
its clock source is not the system clock. The wake-up sources for “stopexe” can be IO-toggle or Timer16
counts to set values when the clock source of Timer16 is IHRC or ILRC modules,or wakeup by
comparator when setting GPCC.7=1 and GPCS.6=1 to enable the comparator wakeup function at the
same time. Wake-up from input pins can be considered as a continuation of normal execution, the detail
information for Power-Save mode shows below:
IHRC and EOSC oscillator modules: No change, keep active if it was enabled
ILRC oscillator modules: must remain enabled, need to start with ILRC when be wakening up
System clock: Disable, therefore, CPU stops execution
OTP memory is turned off
Timer counter: Stop counting if system clock is selected or the corresponding oscillator module is
disabled; otherwise, it keeps counting. (The Timer contains TM16, TM2, TM3, PWMG0, PWMG1, and
PWMG2.)
Wake-up sources:
a. IO toggle wake-up: IO toggling in digital input mode (PxC bit is 1 and PxDIER bit is 1).
b. Timer wake-up: If the clock source of Timer is not the SYSCLK, the system will be awakened when
the Timer counter reaches the set value.
c. Comparator wake-up: It need setting GPCC.7=1 and GPCS.6=1 to enable the comparator wake-up
function at the same time.
An example shows how to use Timer16 to wake-up from “stopexe”:
$ T16M
…
ILRC, /1, BIT8
// Timer16 setting
WORD
STT16
stopexe;
…
count =
count;
0;
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PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
The initial counting value of Timer16 is zero and the system will be woken up after the Timer16 counts 256
ILRC clocks.
5.11.2 Power-Down mode (“stopsys”)
Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using
the “stopsys” instruction, this chip will be put on Power-Down mode directly. It is recommend to set
GPCC.7=0 to disable the comparator before the command “stopsys”. The following shows the internal
status of PMS132/PMS132B detail when “stopsys” command is issued:
All the oscillator modules are turned off
OTP memory is turned off
The contents of SRAM and registers remain unchanged
Wake-up sources: IO toggle in digital mode (PxDIER bit is 1).
Wake-up from input pins can be considered as a continuation of normal execution. To minimize power
consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The
reference sample program for power down is shown as below:
CLKMD
CLKMD.4
…
=
=
0xF4;
0;
//
//
Change clock from IHRC to ILRC
disable IHRC
while (1)
{
STOPSYS;
if (…) break;
//
//
//
enter power-down
if wakeup happen and check OK, then return to high speed
else stay in power-down mode again
}
CLKMD=
0x34;
//
Change clock from ILRC to IHRC/2
5.11.3 Wake-up
After entering the Power-Down or Power-Save modes, the PMS132/PMS132B can be resumed to normal
operation by toggling IO pins, Timer16 interrupt is available for Power-Save mode ONLY. Table 7 shows
the differences in wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
Yes
Timer Interrupt
STOPSYS
STOPEXE
No
Yes
Yes
Table 7: Differences in wake-up sources between Power-Save mode and Power-Down mode
When using the IO pins to wake-up the PMS132/PMS132B, registers pxdier should be properly set to
enable the wake-up function for every corresponding pin. The time for normal wake-up is about 3000 ILRC
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PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
clocks counting from wake-up event; fast wake-up can be selected to reduce the wake-up time by misc
register, and the time for fast wake-up is about 45 ILRC clocks from IO toggling.
Suspend mode
STOPEXE suspend
or
Wake-up mode
Wake-up time (tWUP) from IO toggle
45 * TILRC,
Where TILRC is the time period of ILRC
Fast wake-up
STOPSYS suspend
STOPEXE suspend
or
3000 * TILRC
,
Normal wake-up
Where TILRC is the clock period of ILRC
STOPSYS suspend
Please notice that when Fast boot-up is selected, no matter which wake-up mode is selected in misc.5, the
wake-up mode will be forced to be FAST. If Normal boot-up is selected, the wake-up mode is determined by
misc.5.
5.12 IO Pins
All the pins can be independently set into two states output or input by configuring the data registers (pa, pb),
control registers (pac, pbc) and pull-high registers (paph, pbph). All these pins have Schmitt-trigger input
buffer and output driver with CMOS level. When it is set to output low, the pull-high resistor is turned off
automatically. If user wants to read the pin state, please notice that it should be set to input mode before
reading the data port; if user reads the data port when it is set to output mode, the reading data comes from
data register, NOT from IO pad. As an example, Table 8 shows the configuration table of bit 0 of port A. The
hardware diagram of IO buffer is also shown as Fig.19.
pa.0 pac.0 paph.0
Description
X
X
0
1
1
0
0
1
1
1
0
1
X
0
1
Input without pull-high resistor
Input with pull- high resistor
Output low without pull- high resistor
Output high without pull- high resistor
Output high with pull- high resistor
Table 8: PA0 Configuration Table
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
RD pull-high latch
WR pull-high latch
D
D
D
Q
(weak P -MOS)
pull-high
latch
Q
Q1
Data
latch
PAD
WR data latch
RD control latch
Q
WR control latch
Control
latch
M
U
X
RD Port
Data Bus
padier.x or pbdier.x
Wakeup module
Interrupt module
Analog Module
(
Fig.19: Hardware diagram of IO buffer
Other than PA5, all the IO pins have the same structure; PA5 can be open-drain ONLY when setting to output
mode (without Q1). The corresponding bits in registers padier / pbdier should be set to low to prevent leakage
current for those pins are selected to be analog function. When PMS132/PMS132B is put in power-down or
power-save mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins
needed to wake-up system must be set to input mode and set the corresponding bits of registers padier and
pbdier to high. The same reason, padier.0 should be set high when PA0 is used as external interrupt pin,
pbdier.0 for PB0, padier.4 for PA4 and pbdier.5 for PB5.
5.13 Reset and LVR
5.13.1 Reset
There are many causes to reset the PMS132/PMS132B, once reset is asserted, most of all the registers in
PMS132/PMS132B will be set to default values, system should be restarted once abnormal cases happen,
or by jumping program counter to address 0x0. The data memory is in uncertain state when reset comes
from power-up and LVR; however, the content will be kept when reset comes from PRSTB pin or WDT
timeout.
5.13.2 LVR reset
By code option, there are many different levels of LVR for reset; usually, user selects LVR reset level to be
in conjunction with operating frequency and supply voltage.
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.14 Analog-to-Digital Conversion (ADC) module
Fig.20: ADC Block Diagram
There are seven registers when using the ADC module, which are:
ADC Control Register (adcc)
ADC Regulator Control Register (adcrgc)
ADC Mode Register (adcm)
ADC Result High/Low Register (adcrh, adcrl)
Port A/B Digital Input Enable Register (padier, pbdier)
The following steps are required to do the AD conversion procedure:
(1) Configure the voltage reference high by adcrgc register
(2) Configure the AD conversion clock by adcm register
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
(3) Configure the pin as analog input by padier, pbdier register
(4) Select the ADC input channel by adcc register
(5) Enable the ADC module by adcc register
(6) Delay a certain amount of time after enabling the ADC module
Condition 1: using the internal voltage reference high which are 2V, 3V, 4V or the input channel is bandgap
It must delay more than 1 ms when the time of 200 AD clocks is less than 1ms. Or it must delay
200 AD clocks when the time of 200 AD clocks is larger than 1ms
Condition 2: without using any internal 2V, 3V, 4V, bandgap voltage
It needs to delay 200 AD clocks only.
(7) Execute the AD conversion and check if ADC data is ready
set ‘1’ to addc.6 to start the conversion and check whether addc.6 is ‘1’
(8) Read the ADC result registers:
First read the adcrh register and then read the adcrl register.
If user power down the ADC and enable the ADC again, be sure to go to step 6 to confirm the ADC becomes
ready before the conversion.
5.14.1 The input requirement for AD conversion
For the AD conversion to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed
to fully charge to the voltage reference high level and discharge to the voltage reference low level. The
analog input model is shown as Fig.21, the signal driving source impedance (Rs) and the internal sampling
switch impedance (Rss) will affect the required time to charge the capacitor CHOLD directly. The internal
sampling switch impedance may vary with ADC supply voltage; the signal driving source impedance will
affect accuracy of analog input signal. User must ensure the measured signal is stable before sampling;
therefore, the maximum signal driving source impedance is highly dependent on the frequency of signal to
be measured. The recommended maximum impedance for analog driving source is about 10KΩ under
500KHz input frequency.
Fig.21: Analog Input Model
Before starting the AD conversion, the minimum signal acquisition time should be met for the selected
analog input signal, the selection of ADCLK must be met the minimum signal acquisition time.
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
5.14.2 Select the reference high voltage
The ADC reference high voltage can be selected via bit[7:5] of register adcrgc and its option can be VDD,
4V, 3V, 2V, band-gap (1.20V) reference voltage or PB1 from external pin.
5.14.3 ADC clock selection
The clock of ADC module (ADCLK) can be selected by adcm register; there are 8 possible options for
ADCLK from CLK÷1 to CLK÷128 (CLK is the system clock). Due to the signal acquisition time TACQ is one
clock period of ADCLK, the ADCLK must meet that requirement. The recommended ADC clock is to
operate at 2us.
5.14.4 Configure the analog pins
There are 12 analog signals can be selected for AD conversion, 11 analog input signals come from
external pins and one is from internal band-gap reference voltage or 0.25*VDD. There are 4 voltage levels
selectable for the internal band-gap reference, they are 1.2V, 2V, 3V and 4V. For external pins, the analog
signals are shared with Port A[0], Port A[3], Port A[4], and Port B[7:0]. To avoid leakage current at the
digital circuit, those pins defined for analog input should disable the digital input function (set the
corresponding bit of padier or pbdier register to be 0).
The measurement signals of ADC belong to small signal; it should avoid the measured signal to be
interfered during the measurement period, the selected pin should (1) be set to input mode (2) turn off
weak pull-high resistor (3) set the corresponding pin to analog input by port A/B digital input disable register
(padier / pbdier).
5.14.5 Using the ADC
The following example shows how to use ADC with PB0~PB3.
First, defining the selected pins:
PBC
PBPH
PBDIER
=
=
=
0B_XXXX_0000;
0B_XXXX_0000;
0B_XXXX_0000;
//
//
//
PB0 ~ PB3 as Input
PB0 ~ PB3 without pull-high
PB0 ~ PB3 digital input is disabled
Next, setting ADCC register, example as below:
$
$
$
ADCC Enable, PB3;
ADCC Enable, PB2;
ADCC Enable, PB0;
//
//
//
set PB3 as ADC input
set PB2 as ADC input
set PB0 as ADC input
Next, setting ADCM and ADCRGC register, example as below:
$
$
$
ADCM 12BIT, /16;
ADCM 12BIT, /8;
ADCRGC VDD;
//
//
recommend /16 @System Clock=8MHz
recommend /8 @System Clock=4MHz
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PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Next, delay 400us, example as below:
.Delay 8*400;
.Delay 4*400;
// System Clock=8MHz
// System Clock=4MHz
Then, start the ADC conversion:
AD_START =
while (! AD_DONE) NULL;
1;
//
//
start ADC conversion
wait ADC conversion result
Finally, it can read ADC result when AD_DONE is high:
WORD
Data$1
Data$0
Data
Data;
//
two bytes result: ADCRH and ADCRL
=
=
=
ADCRH
ADCRL;
Data >> 4;
The ADC can be disabled by using the following method:
ADCC Disable;
$
or
ADCC
=
0;
5.15 Multiplier
There is an 8x8 multiplier on-chip to enhance hardware capability in arithmetic function, its multiplication is an
8 x8 unsigned operation and can be finished in one clock cycle. Before issuing the mul command, both
multiplicand and multiplicator must be put on ACC and register mulop (0x08); After mul command, the high
byte result will be put on register mulrh (0x09) and low byte result on ACC. The hardware diagram of this
multiplier is shown as Fig.22.
8-bit
ACC
8-bit
mulop (0x08)
mulrh
Bit[15~8]
ACC
Bit[7~0]
Fig.22: Block diagram of hardware multiplier
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6. IO Registers
6.1. ACC Status Flag Register (flag), IO address = 0x00
Bit
7 - 4
3
Reset R/W
Description
-
-
Reserved. Please do not use.
0
R/W
OV (Overflow Flag). This bit is set to be 1 whenever the sign operation is overflow.
AC (Auxiliary Carry Flag). There are two conditions to set this bit, the first one is carry out
of low nibble in addition operation and the other one is borrow from the high nibble into low
nibble in subtraction operation.
2
0
R/W
C (Carry Flag). There are two conditions to set this bit, the first one is carry out in addition
operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
1
0
0
0
R/W
R/W
Z (Zero Flag). This bit will be set when the result of arithmetic or logic operation is zero;
Otherwise, it is cleared.
6.2. Stack Pointer Register (sp), IO address = 0x02
Bit Reset R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer. Please notice that bit 0 should be kept 0 due to program counter is 16 bits.
7 - 0 R/W
-
6.3. Clock Mode Register (clkmd), IO address = 0x03
Bit Reset R/W
Description
System clock (CLK) selection:
Type 0, clkmd[3]=0 Type 1, clkmd[3]=1
000: IHRC÷4
001: IHRC÷2
010: reserved
011: EOSC÷4
100: EOSC÷2
101: EOSC
000: IHRC÷16
001: IHRC÷8
010: ILRC÷16 (ICE does NOT Support.)
011: IHRC÷32
7 - 5
111
R/W
100: IHRC÷64
101: EOSC÷8
110: ILRC÷4
11x: reserved.
111: ILRC (default)
4
3
1
0
R/W Internal High RC Enable. 0 / 1: disable / enable
Clock Type Select. This bit is used to select the clock type in bit [7:5].
0 / 1: Type 0 / Type 1
R/W
R/W
Internal Low RC Enable. 0 / 1: disable / enable
If ILRC is disabled, watchdog timer is also disabled.
2
1
1
0
1
0
R/W Watch Dog Enable. 0 / 1: disable / enable
R/W Pin PA5/PRSTB function. 0 / 1: PA5 / PRSTB
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PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.4. Interrupt Enable Register (inten), IO address = 0x04
Bit
7
Reset
R/W
Description
0
0
0
0
0
0
0
0
R/W
Enable interrupt from Timer3. 0 / 1: disable / enable.
6
R/W Enable interrupt from Timer2. 0 / 1: disable / enable.
R/W Enable interrupt from PWMG0. 0 / 1: disable / enable.
5
4
R/W
Enable interrupt from comparator. 0 / 1: disable / enable.
3
R/W Enable interrupt from ADC. 0 / 1: disable / enable.
R/W Enable interrupt from Timer16 overflow. 0 / 1: disable / enable.
R/W Enable interrupt from PB0/PA4. 0 / 1: disable / enable.
R/W Enable interrupt from PA0/PB5. 0 / 1: disable / enable.
2
1
0
6.5. Interrupt Request Register (intrq), IO address = 0x05
Bit
Reset
R/W
Description
Interrupt Request from Timer3, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
7
-
R/W
Interrupt Request from Timer2, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
6
5
4
3
2
1
0
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt Request from PWMG0, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from comparator, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from ADC, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from Timer16, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PB0/PA4, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PA0/PB5, this bit is set by hardware and cleared by software.
0 / 1: No Request / request
6.6. Multiplier Operand Register (mulop), IO address = 0x08
Bit
Reset
R/W
Description
7 - 0
-
R/W Operand for hardware multiplication operation.
6.7. Multiplier Result High Byte Register (mulrh), IO address = 0x09
Bit
Reset
R/W
Description
7 - 0
-
RO
High byte result of multiplication operation (read only).
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.8. Timer16 mode Register (t16m), IO address = 0x06
Bit
Reset R/W
Description
Timer16 Clock source selection.
000: disable
001: CLK (system clock)
010: reserved
7 - 5
000
R/W 011: PA4 falling edge (from external pin)
100: IHRC
101: EOSC
110: ILRC
111: PA0 falling edge (from external pin)
Timer16 clock pre-divider.
00: ÷1
4 - 3
00
R/W 01: ÷4
10: ÷16
11: ÷64
Interrupt source selection. Interrupt event happens when the selected bit status is changed.
0 : bit 8 of Timer16
1 : bit 9 of Timer16
2 : bit 10 of Timer16
R/W 3 : bit 11 of Timer16
4 : bit 12 of Timer16
5 : bit 13 of Timer16
6 : bit 14 of Timer16
7 : bit 15 of Timer16
2 - 0
000
6.9. External Oscillator setting Register (eoscr), IO address = 0x0a
Bit
Reset R/W
Description
7
0
WO Enable external crystal oscillator. 0 / 1 : Disable / Enable
External crystal oscillator selection.
00 : reserved
6 - 5
00
WO 01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
4 - 1
0
-
-
Reserved. Please keep 0 for future compatibility.
0
WO Power-down the Band-gap and LVR hardware modules. 0 / 1: normal / power-down.
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PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.10. Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
Reset
R/W
Description
7 - 5
-
-
Reserved.
Timer16 edge selection.
4
0
WO 0 : rising edge of the selected bit to trigger interrupt
1 : falling edge of the selected bit to trigger interrupt
PB0/PA4 edge selection.
00 : both rising edge and falling edge of the selected bit to trigger interrupt
WO 01 : rising edge of the selected bit to trigger interrupt
10 : falling edge of the selected bit to trigger interrupt
11 : reserved.
3 - 2
00
PA0/PB5 edge selection.
00 : both rising edge and falling edge of the selected bit to trigger interrupt
WO 01 : rising edge of the selected bit to trigger interrupt
10 : falling edge of the selected bit to trigger interrupt
11 reserved.
1 - 0
00
6.11. Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset
R/W
Description
Enable PA7 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA7 can NOT be used to wake-up the system.
Enable PA6 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA6 can NOT be used to wake-up the system.
Enable PA5 digital input and wake-up event. 1 / 0 : enable / disable.
This bit can be set to low to disable wake-up from PA5 toggling.
7
1
WO
6
5
4
1
1
1
WO
WO
WO
Enable PA4 digital input, wake-up event and interrupt request. 1 / 0 : enable / disable.
This bit can be set to low to prevent leakage current when PA4 is assigned as AD input,
and to disable wake-up from PA4 toggling and interrupt request from this pin.
Enable PA3 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PA3 is assigned as AD input to prevent leakage current.
If this bit is set to low, PA3 can NOT be used to wake-up the system.
3
2 - 1
0
1
1
1
WO
WO
WO
Reserved
Enable PA0 digital input, wake-up event and interrupt request. 1 /0: enable / disable.
This bit can be set to low to prevent leakage current when PA0 is assigned as AD input,
and to disable wake-up from PA0 toggling and interrupt request from this pin.
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8bit OTP MCU with 12-bit ADC
6.12. Port B Digital Input Enable Register (pbdier), IO address = 0x0e
Bit
Reset R/W
Description
Enable PB7~PB6 digital input and wake-up event. 1 /0: enable / disable.
7 - 6
11
1
WO These bits should be set to low when PB7~PB6 assigned as AD input to prevent leakage
current. If set to low, PB7~PB6 can NOT be used to wake-up the system.
Enable PB5 digital input, wake-up event and interrupt request. 1 /0: enable / disable.
This bit can be set to low to prevent leakage current when PB5 is assigned as AD input, and
to disable wake-up from PB5 toggling and interrupt request from this pin.
Enable PB4~PB1 digital input and wake-up event. 1 /0: enable / disable.
5
4 - 1
0
WO
1111
1
WO These bits should be set to low when PB4~PB1 assigned as AD input to prevent leakage
current. If set to low, PB4~PB1 can NOT be used to wake-up the system.
Enable PB0 digital input, wake-up event and interrupt request. 1 /0: enable / disable.
This bit can be set to low to prevent leakage current when PB0 is assigned as AD input, and
to disable wake-up from PB0 toggling and interrupt request from this pin.
WO
6.13. Port A Data Register (pa), IO address = 0x10
Bit
Reset
R/W
Description
7 - 0
0x00
R/W Data register for Port A.
6.14. Port A Control Register (pac), IO address = 0x11
Bit
Reset
R/W
Description
Port A control registers. This register is used to define input mode or output mode for each
corresponding pin of port A. 0 / 1: input / output
7 - 0
0x00
R/W
Please note that PA5 can be INPUT or OUTPUT LOW ONLY, the output state will be
tri-state when PA5 is programmed into output mode with data 1.
6.15. Port A Pull-High Register (paph), IO address = 0x12
Bit
Reset
R/W
Description
Port A pull-high register. This register is used to enable the internal pull-high device on
7 - 0
0x00
R/W each corresponding pin of port A and this pull high function is active only for input mode.
0 / 1 : disable / enable
6.16. Port B Data Register (pb), IO address = 0x14
Bit
Reset
R/W
Description
7 - 0
0x00
R/W Data register for Port B.
6.17. Port B Control Register (pbc), IO address = 0x15
Bit
Reset
R/W
Description
Port B control register. This register is used to define input mode or output mode for each
corresponding pin of port B. 0 / 1: input / output
7 - 0
0x00
R/W
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PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.18. Port B Pull-High Register (pbph), IO address = 0x16
Bit
Reset
R/W
Description
Port B pull-high register. This register is used to enable the internal pull-high device on
7 - 0
0x00
R/W each corresponding pin of port B and this pull high function is active only for input mode.
0 / 1 : disable / enable
6.19. Miscellaneous Register (misc), IO address = 0x17
Bit
Reset
R/W
Description
Reserved. (keep 0 for future compatibility)
7 - 6
-
-
Enable fast Wake-up. Fast wake-up is NOT supported when EOSC is enabled.
0: Normal wake-up.
5
0
WO
The wake-up time is 3000 ILRC clocks (Not for fast boot-up)
1: Fast wake-up.
The wake-up time is 45 ILRC clocks
Reserved. (keep 0 for future compatibility)
Disable LVR function.
4 - 3
2
-
-
0
WO
0 / 1 : Enable / Disable
Watch dog time out period.
00: 8k ILRC clock period
1 - 0
00
WO 01: 16k ILRC clock period
10: 64k ILRC clock period
11: 256k ILRC clock period
6.20. Comparator Control Register (gpcc), IO address = 0x18
Bit
Reset
R/W
Description
Enable comparator.
0 / 1 : disable / enable
7
0
R/W
When this bit is set to enable, please also set the corresponding analog input pins to be
digital disable to prevent IO leakage.
Comparator result of comparator.
6
5
4
-
RO
0: plus input < minus input
1: plus input > minus input
Select whether the comparator result output will be sampled by TM2_CLK?
0
0
R/W 0: result output NOT sampled by TM2_CLK
1: result output sampled by TM2_CLK
Inverse the polarity of result output of comparator.
R/W 0: polarity is NOT inversed.
1: polarity is inversed.
Selection the minus input (-) of comparator.
000 : PA3
001 : PA4
010 : Internal 1.20 volt band-gap reference voltage
011 : Vinternal R
3 - 1
000
R/W
100 : PB6
101 : PB7
11X: reserved
Selection the plus input (+) of comparator.
R/W 0 : Vinternal R
1 : PA4
0
0
©Copyright 2020, PADAUK Technology Co. Ltd
Page 70 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.21. Comparator Selection Register (gpcs), IO address = 0x19
Bit
Reset
R/W
WO
-
Description
Comparator output enable (to PA0).
0 / 1 : disable / enable
Reserved
7
0
6
5
4
0
0
0
WO Selection of high range of comparator.
WO Selection of low range of comparator.
Selection the voltage level of comparator.
0000 (lowest) ~ 1111 (highest)
3 - 0
0000
WO
6.22. Reset Status Register (rstst), IO address = 0x1b
Reset
Bit
R/W
Description
(POR only)
The reset flag for the Watch-Dog time-out. This bit is 1 when Watch-Dog reset occurs.
Write 0 to clear this flag or POR clear.
7
0
R/W
The reset flag for the invalid code. This bit is 1 when invalid code reset occurs.
Write 0 to clear this flag or POR clear.
6
0
R/W
5
4
0
-
-
-
Reserved. Please keep 0.
Reserved. Please keep 1.
The reset flag for the external reset pin (PA5). This bit is 1 when PA5 reset occurs.
3
-
R/W
Write 0 to clear this flag.
VDD below 4V flag. This bit is 1 when the VDD voltage is lower than 4V.
Write 0 to clear this flag.
2
-
R/W
Please note that this bit will be 1 automatically when VDD is powered slowly. If
necessary, it is recommended to clear this flag during the program initialization.
VDD below 3V flag. This bit is 1 when the VDD voltage is lower than 3V.
Write 0 to clear this flag.
1
0
-
-
R/W
R/W
Please note that this bit will be 1 automatically when VDD is powered slowly. If
necessary, it is recommended to clear this flag during the program initialization.
VDD below 2V flag. This bit is 1 when the VDD voltage is lower than 2V.
Write 0 to clear this flag.
Please note that this bit will be 1 automatically when VDD is powered slowly. If
necessary, it is recommended to clear this flag during the program initialization.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 71 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.23. Timer2 Control Register (tm2c), IO address = 0x1c
Bit
Reset
R/W
Description
Timer2 clock selection.
0000 : disable
0001 : CLK (system clock)
0010 : IHRC
0011 : EOSC
0100 : ILRC
0101 : comparator output
011x : reserved
7 - 4
0000
R/W
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does
NOT be stopped, Timer2 will keep counting when ICE is in halt state.
Timer2 output selection.
00 : disable
3 - 2
00
R/W 01 : PB2
10 : PA3
11 : PB4
Timer2 mode selection.
1
0
0
0
R/W
R/W
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer2 output.
0 / 1: disable / enable.
6.24. Timer2 Counter Register (tm2ct), IO address = 0x1d
Bit Reset
7–0 0x00
R/W
Description
R/W Bit [7:0] of Timer2 counter register.
6.25. Timer2 Scalar Register (tm2s), IO address = 0x1e
Bit Reset
R/W
Description
PWM resolution selection.
0 : 8-bit
7
0
WO
1 : 6-bit
Timer2 clock pre-scalar.
00 : ÷ 1
6 - 5
00
WO
WO
01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4 - 0 00000
Timer2 clock scalar.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 72 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.26. Timer2 Bound Register (tm2b), IO address = 0x09
Bit Reset
7 - 0 0x00
R/W
Description
WO Timer2 bound register.
6.27. PWMG0 control Register (pwmg0c), IO address = 0x20
Bit
Reset
R/W
WO Enable PWMG0 generator. 0 / 1 : disable / enable.
RO Output status of PWMG0 generator.
Description
7
0
6
5
-
0
WO Enable to inverse the polarity of PWMG0 generator output. 0 / 1 : disable / enable.
PWMG0 counter reset.
4
0
0
WO
Writing “1” to clear PWMG0 counter and this bit will be self clear to 0 after counter reset.
Select PWM output pin for PWMG0.
000: none
001: PB5
WO
3 - 1
011: PA0
100: PB4
Others: reserved
Clock source of PWMG0 generator.
0 : SYSCLK
0
0
WO
1 : IHRC or IHRC * 2 (by Code Option: PWM_Source)
6.28. PWMG0 Scalar Register (pwmg0s), IO address = 0x21
Bit
Reset
R/W
Description
PWMG0 interrupt mode.
7
0
WO 0: Generate interrupt when counter matches the duty value
1: Generate interrupt when counter is 0.
PWMG0 clock pre-scalar.
00 : ÷1
WO 01 : ÷4
10 : ÷16
6 - 5
4 - 0
0
0
11 : ÷64
WO PWMG0 clock divider.
6.29. PWMG0 Counter Upper Bound High Register (pwmg0cubh), IO address = 0x24
Bit
Reset
R/W
Description
7 - 0
-
WO Bit[10:3] of PWMG0 counter upper bound.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 73 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.30. PWMG0 Counter Upper Bound Low Register (pwmg0cubl), IO address = 0x25
Bit
Reset
R/W
Description
7 - 6
5 - 0
-
-
WO Bit[2:1] of PWMG0 counter upper bound.
Reserved
-
6.31. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22
Bit
Reset
R/W
Description
7 - 0
-
WO Duty values bit[10:3] of PWMG0.
6.32. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23
Bit
Reset
R/W
Description
7 - 5
4 - 0
-
-
WO Duty values bit [2:0] of PWMG0.
-
Reserved
Note: It’s necessary to write PWMG0 Duty_Value Low Register before writing PWMG0 Duty_Value High Register.
6.33. Timer3 Control Register (tm3c), IO address = 0x32
Bit
Reset
R/W
Description
Timer3 clock selection.
0000 : disable
0001 : CLK (system clock)
0010 : IHRC
0011 : EOSC
0100 : ILRC
0101 : comparator output
011x : reserved
7 - 4
0000
R/W
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer3 clock, the clock sent to Timer3
does NOT be stopped, Timer3 will keep counting when ICE is in halt state.
Timer3 output selection.
00 : disable
3 - 2
00
R/W 01 : PB5
10 : PB6
11 : PB7
Timer3 mode selection.
1
0
0
0
R/W
R/W
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer3 output.
0 / 1: disable / enable
©Copyright 2020, PADAUK Technology Co. Ltd
Page 74 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.34. Timer3 Counter Register (tm3ct), IO address = 0x33
Bit Reset
7 - 0 0x00
R/W
Description
R/W Bit [7:0] of Timer3 counter register.
6.35. Timer3 Scalar Register (tm3s), IO address = 0x34
Bit
Reset
R/W
Description
PWM resolution selection.
0 : 8-bit
7
0
WO
1 : 6-bit
Timer3 clock pre-scalar.
00 : ÷ 1
6 - 5
4 - 0
00
WO
WO
01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
00000
Timer3 clock scalar.
6.36. Timer3 Bound Register (tm3b), IO address = 0x3f
Bit
Reset
R/W
Description
7 - 0
0x00
WO
Timer3 bound register.
6.37. ADC Control Register (adcc), IO address = 0x3b
Bit
Reset
R/W
Description
7
0
R/W Enable ADC function. 0/1: Disable/Enable.
ADC process control bit.
R/W
6
0
Read “1” to indicate the ADC is ready.
Channel selector. These four bits are used to select input signal for AD conversion.
0000: PB0/AD0,
0001: PB1/AD1,
0010: PB2/AD2,
0011: PB3/AD3,
0100: PB4/AD4,
0101: PB5/AD5,
R/W
5 - 2
0000
0110: PB6/AD6,
0111: PB7/AD7,
1000: PA3/AD8,
1001: PA4/AD9,
1010: PA0/AD10,
1111: (Channel F) Band-gap reference voltage or 0.25*VDD
Others: reserved
0 - 1
-
-
Reserved. (keep 0 for future compatibility)
©Copyright 2020, PADAUK Technology Co. Ltd
Page 75 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.38. ADC Mode Register (adcm), IO address = 0x3c
Bit Reset
R/W
Description
Reserved (keep 0 for future compatibility)
7 - 4
3 - 1
0
-
000
-
-
ADC clock source selection.
000: CLK (system clock) ÷ 1,
001: CLK (system clock) ÷ 2,
010: CLK (system clock) ÷ 4,
011: CLK (system clock) ÷ 8,
100: CLK (system clock) ÷ 16,
101: CLK (system clock) ÷ 32,
110: CLK (system clock) ÷ 64,
111: CLK (system clock) ÷ 128,
Reserved
WO
-
6.39. ADC Regulator Control Register (adcrgc), IO address = 0x3d
Bit
Reset
R/W
Description
These three bits are used to select input signal for ADC reference high voltage.
000: VDD,
001: 2V,
010: 3V,
7 - 5
000
WO
011: 4V,
100: PB1,
101: Band-gap 1.20 volt reference voltage
Others: reserved
ADC channel F selector:
4
0
WO
0: Band-gap reference voltage
1: 0.25*VDD. The deviation is within ±0.01*VDD mostly.
Band-gap reference voltage selector for ADC channel F:
00: 1.2V
3 - 2
1 - 0
00
-
WO
-
01: 2V
10: 3V
11: 4V
Reserved. Please keep 0.
6.40. ADC Result High Register (adcrh), IO address = 0x3e
Bit
Reset
R/W
Description
These eight read-only bits will be the bit [11:4] of AD conversion result. The bit 7 of this
register is the MSB of ADC result for any resolution.
7 - 0
-
RO
6.41. ADC Result Low Register (adcrl), IO address = 0x3f
Bit
Reset
R/W
RO
-
Description
These four bits will be the bit [3:0] of AD conversion result.
Reserved
7 - 4
3 - 0
-
-
©Copyright 2020, PADAUK Technology Co. Ltd
Page 76 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.42. PWMG1 control Register (pwmg1c), IO address = 0x26
Bit
Reset
R/W
WO
RO
Description
7
0
-
Enable PWMG1. 0 / 1 : disable / enable.
6
Output of PWMG1.
5
0
WO
Enable to inverse the polarity of PWMG1 output. 0 / 1 : disable / enable.
PWMG1 counter reset.
4
0
0
WO
WO
Writing “1” to clear PWMG1 counter.
Select PWMG1 output pin.
000: none
001: PB6
3 - 1
011: PA4
100: PB7
Others: reserved
Clock source of PWMG1.
0 : SYSCLK
0
0
WO
1 : IHRC or IHRC * 2 (by Code Option : PWM_Source)
6.43. PWMG1 Scalar Register (pwmg1s), IO address = 0x27
Bit
Reset
R/W
Description
PWMG1 interrupt mode.
7
0
WO
0: Generate interrupt when counter matches the duty value.
1: Generate interrupt when counter is 0.
PWMG1 clock pre-scalar.
00 : ÷1
6 - 5
4 - 0
0
0
WO
WO
01 : ÷4
10 : ÷16
11 : ÷64
PWMG1 clock divider.
6.44. PWMG1 Counter Upper Bound High Register (pwmg1cubh), IO address = 0x2A
Bit
Reset
R/W
Description
7 - 0
8’h00
WO
Bit[10:3] of PWMG1 counter upper bound.
6.45. PWMG1 Counter Upper Bound Low Register (pwmg1cubl), IO address = 0x2B
Bit
Reset
000
-
R/W
WO
-
Description
7 - 6
5 - 0
Bit[2:1] of PWMG1 counter upper bound.
Reserved
©Copyright 2020, PADAUK Technology Co. Ltd
Page 77 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.46. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28
Bit
Reset
R/W
Description
7 - 0
8’h00
WO
Duty values bit[10:3] of PWMG1.
6.47. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29
Bit
Reset
000
-
R/W
WO
-
Description
7 - 5
4 - 0
Duty values bit[2:0] of PWMG1.
Reserved
Note: It’s necessary to write PWMG1 Duty_Value Low Register before writing PWMG1 Duty_Value High Register.
6.48. PWMG2 control Register (pwmg2c), IO address = 0x2C
Bit
Reset
R/W
Description
7
0
WO
Enable PWMG2. 0 / 1 : disable / enable.
6
5
-
RO
Output of PWMG2.
0
WO
Enable to inverse the polarity of PWMG2 output. 0 / 1 : disable / enable.
PWMG2 counter reset.
4
0
WO
Writing “1” to clear PWMG2 counter.
Select PWMG2 output pin.
000: disable
001: PB3
3 - 1
0
0
WO
WO
011: PA3
100: PB2
101: PA5 ( ICE does NOT support )
Others: reserved
0
Clock source of PWMG2.
0 : SYSCLK
1 : IHRC or IHRC * 2 (by Code Option : PWM_Source)
6.49. PWMG2 Scalar Register (pwmg2s), IO address = 0x2D
Bit
Reset
R/W
Description
PWMG2 interrupt mode.
7
0
WO
0: Generate interrupt when counter matches the duty value.
1: Generate interrupt when counter is 0.
PWMG2 clock pre-scalar.
00 : ÷1
6 - 5
4 - 0
0
0
WO
WO
01 : ÷4
10 : ÷16
11 : ÷64
PWMG2 clock divider.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 78 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
6.50. PWMG2 Counter Upper Bound High Register (pwmg2cubh), IO address = 0x30
Bit
Reset
R/W
Description
7 - 0
8’h00
WO Bit[10:3] of PWMG2 counter upper bound.
6.51. PWMG2 Counter Upper Bound Low Register (pwmg2cubl), IO address = 0x31
Bit
Reset
R/W
WO Bit[2:1] of PWMG2 counter upper bound.
Reserved
Description
7 – 6
000
5 - 0
-
-
6.52. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2E
Bit
Reset
R/W
Description
7 - 0
8’h00
WO Duty values bit[10:3] of PWMG2.
6.53. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2F
Bit
Reset
R/W
Description
7 - 5
000
WO Duty values bit[2:0] of PWMG2.
4 - 0
-
-
Reserved
Note: It’s necessary to write PWMG2 Duty_Value Low Register before writing PWMG2 Duty_Value High Register.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 79 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
7. Instructions
Symbol
Description
ACC
a
Accumulator (Abbreviation of accumulator)
Accumulator (symbol of accumulator in program)
sp
flag
I
Stack pointer
ACC status flag register
Immediate data
&
Logical AND
|
Logical OR
←
^
Movement
Exclusive logic OR
+
Add
－
〜
〒
OV
Z
Subtraction
NOT (logical complement, 1’s complement)
NEG (2’s complement)
Overflow (The operational result is out of range in signed 2’s complement number system)
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction in
unsigned number system)
C
Auxiliary Carry
AC
(If there is a carry out from low nibble after the result of ALU operation, this bit is set to 1)
IO.n
M.n
The bit of register
Only addressed in 0~0x3F (0~63) is allowed
©Copyright 2020, PADAUK Technology Co. Ltd
Page 80 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
7.1. Data Transfer Instructions
mov
mov
mov
mov
mov
a, I
Move immediate data into ACC.
Example: mov a, 0x0f;
Result: a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
M, a
a, M
Move data from ACC into memory
Example: mov
MEM, a;
Result: MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
a, MEM ;
Result: a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, IO
Move data from IO into ACC
Example: mov
a, pa ;
Result: a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
Move data from ACC into IO
Example: mov
Result: pb ← a
pb, a;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
ldt16 word
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
clear
clear
stt16
…
lb@ T16val ;
hb@ T16val ;
T16val ;
// clear T16val (LSB)
// clear T16val (MSB)
// initial T16 with 0
set1
…
t16m.5 ;
// enable Timer16
set0
ldt16
….
t16m.5 ;
T16val ;
// disable Timer 16
// save the T16 counting value to T16val
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
Page 81 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
stt16 word
Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
mov
mov
mov
mov
stt16
…
a, 0x34 ;
lb@ T16val , a ; // move 0x34 to T16val (LSB)
a, 0x12 ;
hb@ T16val , a ; // move 0x12 to T16val (MSB)
T16val ;
// initial T16 with 0x1234
----------------------------------------------------------------------------------------------------------------------
idxm a, index Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
idxm
a, RAMIndex ; // mov memory data in address 0x5B to ACC
------------------------------------------------------------------------------------------------------------------------
Idxm index, a Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
mov
idxm
a, 0xA5 ;
RAMIndex, a ;
// mov 0xA5 to memory in address 0x5B
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
Page 82 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
xch
M
Exchange data between ACC and memory
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
pushaf
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
.romadr 0x10 ;
// ISR entry address
pushaf ;
…
// put ACC and flag into stack memory
// ISR program
…
// ISR program
popaf ;
reti ;
// restore ACC and flag from stack memory
------------------------------------------------------------------------------------------------------------------------
Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
popaf
Result:
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sp ← sp - 2
;
7.2. Arithmetic Operation Instructions
add
add
add
a, I
Add immediate data with ACC, then put result into ACC
Example: add a, 0x0f ;
Result: a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
M, a
Add data in memory with ACC, then put result into ACC
Example: add
a, MEM ;
Result: a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into memory
Example: add
MEM, a;
Result: MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc a, M
addc M, a
Add data in memory with ACC and carry bit, then put result into ACC
Example: addc
a, MEM ;
Result: a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into memory
Example: addc
Result: MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
MEM, a ;
©Copyright 2020, PADAUK Technology Co. Ltd
Page 83 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
addc
addc
a
Add carry with ACC, then put result into ACC
Example: addc a ;
Result: a ← a + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Add carry with memory, then put result into memory
Example: addc
MEM ;
Result: MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
nadd a, M
nadd M, a
Add negative logic (2’s complement) of ACC with memory
Example: nadd
a, MEM ;
Result: a ← 〒a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add negative logic (2’s complement) of memory with ACC
Example: nadd
MEM, a ;
Result: MEM ← 〒MEM + a
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sub
sub
sub
a, I
Subtraction immediate data from ACC, then put result into ACC.
Example: sub
a, 0x0f;
Result: a ← a - 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
M, a
Subtraction data in memory from ACC, then put result into ACC
Example: sub
a, MEM ;
Result: a ← a - MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction data in ACC from memory, then put result into memory
Example: sub
MEM, a;
Result: MEM ← MEM - a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc a, M
subc M, a
Subtraction data in memory and carry from ACC, then put result into ACC
Example: subc
a, MEM;
Result: a ← a – MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction ACC and carry bit from memory, then put result into memory
Example: subc
MEM, a ;
Result: MEM ← MEM – a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc
subc
a
Subtraction carry from ACC, then put result into ACC
Example: subc
a;
Result: a ← a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Subtraction carry from the content of memory, then put result into memory
Example: subc
Result: MEM ← MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
MEM;
©Copyright 2020, PADAUK Technology Co. Ltd
Page 84 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
inc
M
Increment the content of memory
Example: inc MEM ;
Result: MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dec
clear
mul
M
Decrement the content of memory
Example: dec
MEM;
Result: MEM ← MEM - 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Clear the content of memory
Example: clear
MEM ;
Result: MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Multiplication operation, 8x8 unsigned multiplications will be executed.
Example: mul
;
Result: {MulRH,ACC} ← ACC * MulOp
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example :
---------------------------------------------------------------------------------------------------------------------
…
mov
mov
mov
mul
mov
mov
…
a, 0x5a ;
mulop, a ;
a, 0xa5 ;
// 0x5A * 0xA5 = 3A02 (mulrh + ACC)
// LSB, ram0=0x02
ram0, a ;
a, mulrh ;
// MSB, ACC=0X3A
---------------------------------------------------------------------------------------------------------------------
7.3. Shift Operation Instructions
sr
a
Shift right of ACC, shift 0 to bit 7
Example: sr a ;
Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of ACC with carry bit 7 to flag
src
sr
a
Example: src a ;
Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory, shift 0 to bit 7
M
Example: sr MEM ;
Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of memory with carry bit 7 to flag
src
M
Example: src MEM ;
Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 85 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
sl
a
Shift left of ACC shift 0 to bit 0
Example: sl a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC with carry bit 0 to flag
slc
sl
a
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory, shift 0 to bit 0
M
Example: sl MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry bit 0 to flag
slc
M
Example: slc MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC
swap
a
Example: swap
Result: a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
a ;
7.4. Logic Operation Instructions
and
and
and
or
a, I
a, M
M, a
a, I
Perform logic AND on ACC and immediate data, then put result into ACC
Example: and a, 0x0f ;
Result: a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC
Example: and
a, RAM10 ;
Result: a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory
Example: and
MEM, a ;
Result: MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and immediate data, then put result into ACC
Example: or
a, 0x0f ;
Result: a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
a, M
Perform logic OR on ACC and memory, then put result into ACC
Example: or
a, MEM ;
Result: a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
M, a
Perform logic OR on ACC and memory, then put result into memory
Example: or
Result: MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
MEM, a ;
©Copyright 2020, PADAUK Technology Co. Ltd
Page 86 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
xor
xor
xor
xor
not
a, I
Perform logic XOR on ACC and immediate data, then put result into ACC
Example: xor
a, 0x0f ;
Result: a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
a, M
M, a
a
Perform logic XOR on ACC and IO register, then put result into IO register
Example: xor
pa, a ;
Result: pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into ACC
Example: xor
a, MEM ;
Result: a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform 1’s complement (logical complement) of ACC
Example: not
a ;
Result: a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
not
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC7
------------------------------------------------------------------------------------------------------------------------
Perform 1’s complement (logical complement) of memory
not
M
Example: not
MEM ;
Result: MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC7
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of ACC
neg
a
Example: neg
a;
Result: a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
neg
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC8
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
Page 87 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
neg
M
Perform 2’s complement of memory
Example: neg MEM;
Result: MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC8
------------------------------------------------------------------------------------------------------------------------
Compare ACC with the content of memory
comp
a, M
Example: comp
a, MEM;
Result: Flag will be changed by regarding as ( a - MEM )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
comp
mov
mov
mov
comp
a, 0x38 ;
mem, a ;
a, mem ; // Z flag is set as 1
a, 0x42 ;
mem, a ;
a, 0x38 ;
a, mem ; // C flag is set as 1
------------------------------------------------------------------------------------------------------------------------
Compare ACC with the content of memory
comp
M, a
Example: comp
MEM, a;
Result: Flag will be changed by regarding as ( MEM - a )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
7.5. Bit Operation Instructions
set0 IO.n
Set bit n of IO port to low
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of IO port to high
set1 IO.n
Example: set1 pb.5 ;
Result: set bit 5 of port B to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 88 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
swapc IO.n
Swap the nth bit of IO port with carry bit
Example: swapc IO.0;
Result: C ← IO.0 , IO.0 ← C
When IO.0 is a port to output pin, carry C will be sent to IO.0;
When IO.0 is a port from input pin, IO.0 will be sent to carry C;
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Application Example1 (serial output) :
------------------------------------------------------------------------------------------------------------------------
...
set1
...
pac.0 ;
// set PA.0 as output
set0
swapc
set1
swapc
...
flag.1 ;
pa.0 ;
// C=0
// move C to PA.0 (bit operation), PA.0=0
// C=1
flag.1 ;
pa.0 ;
// move C to PA.0 (bit operation), PA.0=1
------------------------------------------------------------------------------------------------------------------------
Application Example2 (serial input) :
------------------------------------------------------------------------------------------------------------------------
...
set0
...
pac.0 ;
// set PA.0 as input
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift C to bit 7 of ACC
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift new C to bit 7, old C
...
------------------------------------------------------------------------------------------------------------------------
Set bit n of memory to low
set0 M.n
set1 M.n
Example: set0 MEM.5 ;
Result: set bit 5 of MEM to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to high
Example: set1 MEM.5 ;
Result: set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 89 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
7.6. Conditional Operation Instructions
ceqsn a, I
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a – I)
Example: ceqsn
a, 0x55 ;
MEM ;
error ;
inc
goto
Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
ceqsn a, M
cneqsn a, M
Example: ceqsn
a, MEM;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are not equal.
Flag will be changed like as (a ← a - M)
Example: cneqsn
a, MEM;
Result: If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
cneqsn a, I
Compare ACC with immediate data and skip next instruction if both are no equal.
Flag will be changed like as (a ← a - I)
Example: cneqsn
a,0x55 ;
MEM ;
error ;
inc
goto
Result: If a≠0x55, then “goto error”; Otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Check IO bit and skip next instruction if it’s low
t0sn IO.n
t1sn IO.n
t0sn M.n
t1sn M.n
Example: t0sn
pa.5;
Result: If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check IO bit and skip next instruction if it’s high
Example: t1sn
pa.5 ;
Result: If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s low
Example: t0sn MEM.5 ;
Result: If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high
EX: t1sn MEM.5 ;
Result: If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Increment ACC and skip next instruction if ACC is zero
izsn
a
Example: izsn
Result:
a;
a
←
a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 90 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
dzsn
izsn
a
Decrement ACC and skip next instruction if ACC is zero
Example: dzsn a;
Result: A - 1,skip next instruction if a = 0
A
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment memory and skip next instruction if memory is zero
Example: izsn
Result: MEM
MEM;
MEM + 1, skip next instruction if MEM= 0
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dzsn
M
Decrement memory and skip next instruction if memory is zero
Example: dzsn
Result: MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
MEM;
←
MEM - 1, skip next instruction if MEM = 0
7.7. System control Instructions
call
label
Function call, address can be full range address space
Example: call function1;
Result:
[sp]
pc
←
pc + 1
function1
sp + 2
←
←
sp
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
goto label
Go to specific address which can be full range address space
Example: goto
error;
Result: Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Place immediate data to ACC, then return
Example: ret 0x55;
ret
ret
I
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program which had function call
Example: ret;
Result:
sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
reti
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
No operation
nop
Example: nop;
Result: nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 91 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
pcadd
a
Next program counter is current program counter plus ACC.
Example: pcadd a;
Result: pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
…
mov
pcadd
goto
goto
goto
goto
…
a, 0x02 ;
a ;
// PC <- PC+2
// jump here
err1 ;
correct ;
err2 ;
err3 ;
correct:
…
// jump here
------------------------------------------------------------------------------------------------------------------------
Enable global interrupt enable
engint
Example: engint;
Result: Interrupt request can be sent to CPU
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Disable global interrupt enable
disgint
stopsys
stopexe
Example: disgint ;
Result: Interrupt request is blocked from CPU
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
System halt.
Example: stopsys;
Result: Stop the system clocks and halt the system
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
CPU halt. The oscillator module is still active to output clock, however, system clock is disabled
to save power.
Example: stopexe;
Result: Stop the system clocks and keep oscillator modules active.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset the whole chip, its operation will be same as hardware reset.
Example: reset;
reset
Result: Reset the whole chip.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset Watchdog timer.
wdreset
Example: wdreset ;
Result: Reset Watchdog timer.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 92 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
7.8. Summary of Instructions Execution Cycle
2T
2T
1T
1T
goto, call, idxm, pcadd, ret, reti,
ceqsn, cneqsn, t0sn, t1sn, dzsn, izsn
Others
Condition is fulfilled.
Condition is not fulfilled.
7.9. Summary of affected flags by Instructions
Instruction
mov a, I
Z
-
C
-
AC OV Instruction
Z
-
C
-
AC OV Instruction
Z
Y
-
C
-
AC OV
-
-
-
-
mov M, a
mov IO, a
idxm a, index
pushaf
-
-
-
-
mov a, M
ldt16 word
idxm index, a
popaf
-
-
-
-
mov a, IO
stt16 word
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
xch
M
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
-
add a, I
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, M
addc M, a
nadd a, M
sub a, M
subc M, a
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add M, a
addc a, M
addc
a
addc
M
nadd M, a
sub a, I
sub M, a
subc a, M
subc
dec
sr a
src
a
subc
clear
src
M
M
inc
mul
sr
M
M
a
-
Y
Y
Y
-
-
-
M
-
Y
Y
-
-
-
M
-
-
-
sl
a
-
-
-
slc
a
-
-
-
sl
M
-
-
-
slc
and
M
-
-
-
swap
and
a
-
-
-
and
a, I
Y
Y
Y
Y
Y
Y
-
-
-
a, M
Y
Y
-
-
-
M, a
Y
Y
Y
Y
Y
-
-
-
-
or a, I
-
-
-
or a, M
-
-
-
or M, a
-
-
-
xor
xor
neg
a, I
-
-
-
xor
not
neg
IO, a
-
-
-
xor
not
a, M
-
-
-
M, a
a
-
-
-
a
Y
Y
-
-
-
-
M
-
-
-
-
-
-
M
-
-
-
comp a, M
set1 IO.n
Y
-
Y
-
Y
-
comp M, a
set0 M.n
Y
-
Y
-
Y
-
set0 IO.n
set1 M.n
ceqsn a, M
t0sn IO.n
t1sn M.n
-
-
-
-
-
-
-
swapc IO.n
cneqsn a,M
t1sn IO.n
-
Y
Y
-
-
-
ceqsn a, I
cneqsn a, I
t0sn M.n
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
-
-
-
-
izsn
dzsn
ret
a
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
dzsn
call
a
Y
-
Y
-
Y
-
Y
-
izsn
M
Y
-
Y
-
Y
-
Y
-
M
label
goto label
reti
I
ret
-
-
-
-
-
-
-
-
nop
-
-
-
-
pcadd
a
-
-
-
-
engint
-
-
-
-
disgint
reset
-
-
-
-
stopsys
wdreset
-
-
-
-
stopexe
-
-
-
-
-
-
-
-
-
-
-
-
7.10.BIT definition
Bit defined: Only addressed at 0x00 ~ 0x3F.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 93 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
8. Code Options
Option
Selection
Enable
Disable
4.0V
Description
OTP content is protected and program cannot be read back
OTP content is not protected so program can be read back
Security
Select LVR = 4.0V
Select LVR = 3.5V
Select LVR = 3.0V
Select LVR = 2.75V
Select LVR = 2.5V
Select LVR = 2.2V
Select LVR = 2.0V
Select LVR = 1.8V
3.5V
3.0V
2.75V
2.5V
LVR
2.2V
2.0V
1.8V
Please refer to tWUP and tSBP in Section 4.1
Slow
Fast
Boot-up_Time
PWM_Source
Please refer to tWUP and tSBP in Section 4.1
When pwmg0c.0= 1, PWMG0 clock source = IHRC = 16MHZ
16MHZ
When pwmg1c.0= 1, PWMG1 clock source = IHRC = 16MHZ
When pwmg2c.0= 1, PWMG2 clock source = IHRC = 16MHZ
When pwmg0c.0= 1, PWMG0 clock source = IHRC*2 = 32MHZ
When pwmg1c.0= 1, PWMG1 clock source = IHRC*2 = 32MHZ
When pwmg2c.0= 1, PWMG2 clock source = IHRC*2 = 32MHZ
(ICE does NOT Support.)
32MHZ
Disable
Enable
PA.0
GPC/ PWM are independent
GPC_PWM
Interrupt Src0
Interrupt Src1
PB4_PB7_Drive
GPC output control PWM output (ICE does NOT Support.)
INTEN/ INTRQ.Bit0 is from PA.0
PB.5
INTEN/ INTRQ.Bit0 is from PB.5
PB.0
INTEN/ INTRQ.Bit1 is from PB.0
PA.4
INTEN/ INTRQ.Bit1 is from PA.4
Normal
Strong
PB4 & PB7 Drive/ Sink Current is Normal
PB4 & PB7 Drive/ Sink Current is Strong
©Copyright 2020, PADAUK Technology Co. Ltd
Page 94 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
9. Special Notes
This chapter is to remind user who use PMS132/PMS132B series IC in order to avoid frequent errors upon
operation.
9.1. Warning
User must read all application notes of the IC by detail before using it. Please download the related application
notes from the following link:
http://www.padauk.com.tw/tw/technical/index.aspx
9.2. Using IC
9.2.1 IO pin usage and setting
(1) IO pin as digital input
When IO is set as digital input, the level of Vih and Vil would changes with the voltage and temperature.
Please follow the minimum value of Vih and the maximum value of Vil.
The value of internal pull high resistor would also changes with the voltage, temperature and pin voltage.
It is not the fixed value.
(2) IO pin as digital input and enable wakeup function
Configure IO pin as input
Set PADIER and PBDIER registers to set the corresponding bit to 1.
(3) PA5 is set to be output pin
PA5 can be set to be Open-Drain output pin only, output high requires adding pull-high resistor.
(4) PA5 is set to be PRSTB input pin
Configure PA5 as input
Set CLKMD.0=1 to enable PA5 as PRSTB input pin
(5) PA5 is set to be input pin and to connect with a push button or a switch by a long wire
Needs to put a >33Ω resistor in between PA5 and the long wire
Avoid using PA5 as input in such application.
(6) PA7 and PA6 as external crystal oscillator
Configure PA7 and PA6 as input
Disable PA7 and PA6 internal pull-high resistor
Configure PADIER register to set PA6 and PA7 as analog input
EOSCR register bit [6:5] selects corresponding crystal oscillator frequency :
01 : for lower frequency, ex : 32KHz
10 : for middle frequency, ex : 455KHz, 1MHz
11 : for higher frequency, ex : 4MHz
Program EOSCR.7 =1 to enable crystal oscillator
Ensure EOSC working well before switching from IHRC or ILRC to EOSC
©Copyright 2020, PADAUK Technology Co. Ltd
Page 95 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Note: Please be sure to read the contents of PMC-APN013 carefully. According to this, the crystal oscillator
should be used reasonably. If the following situations happen to cause IC start-up slowly or non-startup,
PADAUK Technology is not responsible for this: the quality of the user's crystal oscillator is not good, the
usage conditions are unreasonable, the PCB cleaner leakage current, or the PCB layouts are
unreasonable.
9.2.2 Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit
Step2: Clear INTRQ register
Step3: In the main program, using ENGINT to enable CPU interrupt function
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine
Step5: After the Interrupt Service Routine being executed, return to the main program
*Use DISGINT in the main program to disable all interrupts
*When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG register.
POPAF instruction is to restore ALU and FLAG register before RETI as below:
void Interrupt (void)
// Once the interrupt occurs, jump to interrupt service routine
{
// enter DISGINT status automatically, no more interrupt is accepted
PUSHAF;
…
POPAF;
}
// RETI will be added automatically. After RETI being executed, ENGINT status will be
restored
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function
(3) PA4 and PB5 can be used as external interrupt pins. When using the PA4 as external interrupt pin, the
setting method of inten/intrq/integs registers are same as that of PB0, the only difference is to choose PB0
or PA4 as source of interrupt_Src1 in PADAUK_CODE_OPTION. Similarly, when using the PB5 as external
interrupt pin, the setting method of inten/intrq/integs registers are same as that of PA0, the only difference
is to choose PA0 or PB5 as source of interrupt_Src0 in PADAUK_CODE_OPTION.
9.2.3 System clock switching
(1) System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock
and turn off the original clock source at the same time. For example: When switching from clock A to clock B,
please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Case 1 : Switch system clock from ILRC to IHRC/2
CLKMD
=
0x36;
0;
// switch to IHRC, ILRC can not be disabled here
CLKMD.2 =
// ILRC can be disabled at this time
©Copyright 2020, PADAUK Technology Co. Ltd
Page 96 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
Case 2 : Switch system clock from ILRC to EOSC
CLKMD
=
0xA6;
0;
// switch to EOSC, ILRC can not be disabled here
CLKMD.2 =
// ILRC can be disabled at this time
ERROR. Switch ILRC to IHRC and turn off ILRC simultaneously
CLKMD 0x50; // MCU will hang
=
(2) Please ensure the EOSC oscillation has established before switching from ILRC or IHRC to EOSC. MCU
will not check its status. Please wait for a while after enabling EOSC. System clock can be switched to
EOSC afterwards. Otherwise, MCU will hang. The example for switching system clock from ILRC to 4MHz
EOSC after boot up is as below:
.ADJUST_IC
EOSCR
SYSCLK=ILRC;
Enable, 4MHz;
$
// 4MHz EOSC start to oscillate.
// delay time to wait crystal oscillator stable
$ T16M EOSC, /1, BIT10
Word Count = 0;
Stt16 Count;
Intrq.T16 = 0;
do
{ nop; }while(!Intrq.T16);
CLKMD = 0xA4;
CLKMD.2 = 0;
// ILRC -> EOSC;
// turn off ILRC only if necessary
The delay duration should be adjusted in accordance with the characteristic of the crystal and PCB. To
measure the oscillator signal by the oscilloscope, please select (x10) on the probe and measure through
PA6(X2) pin to avoid the interference on the oscillator.
9.2.4 Watchdog
Watchdog will be inactive once ILRC is disabled.
9.2.5 TIMER time out
When select $ INTEGS BIT_R (default value) and T16M counter BIT8 to generate interrupt, if T16M counts
from 0, the first interrupt will occur when the counter reaches to 0x100 (BIT8 from 0 to 1) and the second
interrupt will occur when the counter reaches 0x300 (BIT8 from 0 to 1). Therefore, selecting BIT8 as 1 to
generate interrupt means that the interrupt occurs every 512 counts. Please notice that if T16M counter is
restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
If select $ INTEGS BIT_F(BIT triggers from 1 to 0) and T16M counter BIT8 to generate interrupt, the T16M
counter changes to an interrupt every 0x200/0x400/0x600/. Please pay attention to two differences with setting
INTEGS methods.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 97 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
9.2.6 IHRC
(1) The IHRC frequency calibration is performed when IC is programmed by the writer.
(2) Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the
IHRC frequency (either for package or COB), if the calibration is done before molding process, the actual
IHRC frequency after molding may be deviated or becomes out of spec. Normally , the frequency is getting
slower a bit.
(3) It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not
take any responsibility for this situation.
(4) Users can make some compensatory adjustments according to their own experiences. For example, users
can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
9.2.7 LVR
(1)VDD must reach or above 2.0V for successful power-on process; otherwise IC will be inactive.
(2)The setting of LVR (1.8V, 2.0V, 2.2V etc.) will be valid just after successful power-on process.
(3)User can set MISC.2 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest working
voltage of chip; Otherwise IC may work abnormally.
9.2.8 The result of Comparator controls the PWM output pins
The special function of GPC_PWM in PADAUK_CODE_OPTION is used to control the output pins of PWM
modules including TM2, TM3 and PWMG0 / PWMG1 / PWMG2 according to the status of gpcc.6. Any output
pins of those PWM modules will go to 0 when gpcc.6 is 1 and go back to normal PWM function when gpcc.6 is
0.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 98 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
9.2.9 Programming the PMS132/PMS132B
There are 6 pins for using the writer to program: PA3, PA4, PA5, PA6, VDD, and GND.
Please use PDK3S-P-002 to program and put the PMS132/PMS132B-S16A /S14 to move down three spaces
over the CN38. Other packages could be programmed by user’s way. All the left signs behind the jumper are
the same (there are VDD, PA0(not required), PA3, PA4, PA5, PA6, PA7(not required), and GND).The following
picture is shown:
If user uses PDK5S-P-002 or above to program, please follow the instruction.
Please use the following way when using the PMS132/PMS132B-S08:
Special notes about voltage and current while Multi-Chip-Package(MCP) or On-Board Programming
(1) PA5 (VPP) may be higher than 11V.
(2) VDD may be higher than 6.5V, and its maximum current may reach about 20mA.
(3) All other signal pins level (except GND) are the same as VDD..
User should confirm when using this product in MCP or On-Board Programming, the peripheral circuit or
components will not be destroyed or limit the above voltages.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 99 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
PMS132/PMS132B
8bit OTP MCU with 12-bit ADC
9.3 Using ICE
(1) It is recommended to use PDK5S-I-S01/2(B) for emulation of PMS132/PMS132B. PDK5S-I-S01/2(B)
supports PMS132/PMS132B 1-FPPA MCU emulation work, the following items should be noted when using
PDK5S-I-S01/2(B) to emulate PMS132/PMS132B:
PDK5S-I-S01/2(B) doesn’t support the instruction NADD/COMP of PMS132/PMS132B.
PDK5S-I-S01/2(B) doesn’t support SYSCLK=ILRC/16 of PMS132/PMS132B.
PDK5S-I-S01/2(B) doesn’t support the function TM2.GPCRS/TM3.GPCRS of PMS132/PMS132B.
PDK5S-I-S01/2(B) doesn’t support the function PWMG2C.PA5.
PDK5S-I-S01/2(B) doesn’t support the function ADCRGC.BG_2V/BG_3V/BG_4V, and fix BG_1V2 only.
PDK5S-I-S01/2(B) doesn’t support the code options: GPC_PWM, PWM_Source, and TMx_bit.
The PA3 output function will be affected when GPCS selects output to PA0 output.
When using PB1 in ADCRGC, PA1 must float.
When simulating PWM waveform, please check the waveform during program running. When the ICE is
suspended or single-step running, its waveform may be inconsistent with the reality.
The ILRC frequency of the PDK5S-I-S01/2(B) simulator is different from the actual IC and is
uncalibrated, with a frequency range of about 34K~38KHz.
Fast Wakeup time is different from PDK5S-I-S01/2(B): 128 SYSCLK, PMS132/PMS132B: 45 ILRC
Watch dog time out period is different from PDK5S-I-S01/2(B):
WDT period
PMS132/PMS132B
PDK5S-I-S01/2(B)
2048* TILRC
misc[1:0]=00
8K* TILRC
4096* TILRC
misc[1:0]=01
misc[1:0]=10
misc[1:0]=11
16K* TILRC
64K* TILRC
256K* TILRC
16384* TILRC
256* TILRC
©Copyright 2020, PADAUK Technology Co. Ltd
Page 100 of 100
PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020
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