PMS152-S14 [PADAUK]
8bit OTP Type SuLED IO Controller;
| 型号： | PMS152-S14 |
| 厂家： | 
PADAUK Technology |
| 描述： | 8bit OTP Type SuLED IO Controller |
| 文件： | 总91页 (文件大小：2295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PMS152
8bit OTP Type SuLED IO Controller
Datasheet
Version 1.05 – June 9, 2020
Copyright 2020by PADAUK Technology Co., Ltd., all rights reserved
6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.
TEL: 886-3-572-8688 www.padauk.com.tw
PMS152
8bit OTP Type SuLED IO Controller
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those which may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,
customers should design a product with adequate operating safeguards.
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
Table of content
1. Features.................................................................................................................................9
1.1.
1.2.
1.3.
1.4.
Special Features.....................................................................................................................9
System Features.....................................................................................................................9
CPU Features.........................................................................................................................9
Package Information ...............................................................................................................9
2. General Description and Block Diagram..........................................................................10
3. Pin Definition and Functional Description .......................................................................11
4. Device Characteristics.......................................................................................................17
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
AC/DC Device Characteristics ..............................................................................................17
Absolute Maximum Ratings...................................................................................................18
Typical ILRC frequency vs. VDD...........................................................................................19
Typical IHRC frequency deviation vs. VDD(calibrated to 16MHz)..........................................19
Typical ILRC Frequency vs. Temperature.............................................................................20
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)..........................................20
Typical operating current vs. VDD @ system clock = ILRC/n................................................21
Typical operating current vs. VDD @ system clock = IHRC/n ...............................................21
Typical operating current vs. VDD @ system clock = 4MHz EOSC / n..................................22
4.10. Typical operating current vs. VDD @ system clock = 32KHz EOSC / n.................................22
4.11. Typical operating current vs. VDD @ system clock = 1MHz EOSC / n..................................23
4.12. Typical IO driving current (IOH) and sink current (IOL) .............................................................23
4.13. Typical IO input high/low threshold voltage (VIH/VIL) ..............................................................24
4.14. Typical resistance of IO pull high device ...............................................................................25
4.15. Typical power down current (IPD) and power save current (IPS)..............................................25
5. Functional Description.......................................................................................................27
5.1.
5.2.
Program Memory - OTP........................................................................................................27
Boot Procedure.....................................................................................................................27
5.2.1. Timing charts for reset conditions.................................................................................28
Data Memory - SRAM...........................................................................................................29
Oscillator and Clock ..............................................................................................................29
5.4.1. Internal High RC oscillator and Internal Low RC oscillator.........................................29
5.4.2. Chip calibration..........................................................................................................29
5.4.3. IHRC Frequency Calibration and System Clock ........................................................30
5.3.
5.4.
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8bit OTP Type SuLED IO Controller
5.4.4. External Crystal Oscillator .........................................................................................31
5.4.5. System Clock and LVR level .....................................................................................33
5.4.6. System Clock Switching ............................................................................................34
Comparator...........................................................................................................................35
5.5.1 Internal reference voltage (Vinternal R)...........................................................................36
5.5.2 Using the comparator ................................................................................................38
5.5.3 Using the comparator and band-gap 1.20V ...............................................................39
16-bit Timer (Timer16) ..........................................................................................................40
8-bit Timer (Timer2) with PWM generation............................................................................42
5.7.1 Using the Timer2 to generate periodical waveform....................................................43
5.7.2 Using the Timer2 to generate 8-bit PWM waveform...................................................45
5.7.3 Using the Timer2 to generate 6-bit PWM waveform...................................................46
11-bit PWM Generators ........................................................................................................47
5.8.1 PWM Waveform ........................................................................................................47
5.8.2 Hardware Diagram ....................................................................................................48
5.8.3 Equations for 11-bit PWM Generator.........................................................................49
5.8.4 PWM Waveforms with Complementary Dead Zones .................................................49
WatchDog Timer...................................................................................................................52
5.5.
5.6
5.7
5.8
5.9
5.10 . Interrupt ..............................................................................................................................53
5.11 . Power-Save and Power-Down ............................................................................................55
5.11.1 Power-Save mode (“stopexe”)...................................................................................55
5.11.2 Power-Down mode (“stopsys”) ..................................................................................56
5.11.3 Wake-up....................................................................................................................56
5.12 IO Pins..................................................................................................................................58
5.13 Reset and LVR......................................................................................................................59
5.13.1 Reset.........................................................................................................................59
5.13.2 LVR reset ..................................................................................................................59
6. IO Registers ........................................................................................................................60
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
ACC Status Flag Register (flag), IO address = 0x00 .............................................................60
Stack Pointer Register (sp), IO address = 0x02 ....................................................................60
Clock Mode Register (clkmd), IO address = 0x03 .................................................................60
Interrupt Enable Register (inten), IO address = 0x04 ............................................................61
Interrupt Request Register (intrq), IO address = 0x05...........................................................61
Timer16 mode Register (t16m), IO address = 0x06...............................................................62
MISC Register (misc), IO address = 0x08.............................................................................62
External Oscillator setting Register (eoscr), IO address = 0x0a.............................................63
Interrupt Edge Select Register (integs), IO address = 0x0c...................................................63
©Copyright 2020, PADAUK Technology Co. Ltd
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8bit OTP Type SuLED IO Controller
6.10. Port A Digital Input Enable Register (padier), IO address = 0x0d..........................................63
6.11. Port B Digital Input Enable Register (pbdier), IO address = 0x0e..........................................64
6.12. Port A Data Register (pa), IO address = 0x10.......................................................................64
6.13. Port A Control Register (pac), IO address = 0x11 .................................................................64
6.14. Port A Pull-High Register (paph), IO address = 0x12 ............................................................64
6.15. Port B Data Register (pb), IO address = 0x14.......................................................................64
6.16. Port B Control Register (pbc), IO address = 0x15 .................................................................64
6.17. Port B Pull-High Register (pbph), IO address = 0x16 ............................................................65
6.18. Comparator Control Register (gpcc), IO address = 0x18.......................................................65
6.19. Comparator Selection Register (gpcs), IO address = 0x19....................................................65
6.20. Timer2 Control Register (tm2c), IO address = 0x1c ..............................................................66
6.21. Timer2 Scalar Register (tm2s), IO address = 0x17................................................................66
6.22. Timer2 Counter Register (tm2ct), IO address = 0x1d............................................................67
6.23. Timer2 Bound Register (tm2b), IO address = 0x09 ...............................................................67
6.24. PWMG0 control Register (pwmg0c), IO address = 0x20 .......................................................67
6.25. PWMG Clock Register (pwmgclk), IO address = 0x21 ..........................................................68
6.26. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22 .....................................68
6.27. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23 .......................................68
6.28. PWMG Counter Upper Bound High Register (pwmgcubh ), IO address = 0x24 ....................68
6.29. PWMG Counter Upper Bound Low Register (pwmgcubl ), IO address = 0x25 ......................68
6.30. PWMG1 control Register (pwmg1c), IO address = 0x26 .......................................................69
6.31. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28 .....................................69
6.32. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29 .......................................69
6.33. PWMG2 control Register (pwmg2c), IO address = 0x2C.......................................................70
6.34. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2E.....................................70
6.35. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2F .......................................70
7. Instructions.........................................................................................................................71
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
Data Transfer Instructions.....................................................................................................72
Arithmetic Operation Instructions ..........................................................................................75
Shift Operation Instructions...................................................................................................77
Logic Operation Instructions..................................................................................................78
Bit Operation Instructions......................................................................................................81
Conditional Operation Instructions ........................................................................................82
System control Instructions ...................................................................................................83
Summary of Instructions Execution Cycle .............................................................................84
Summary of affected flags by Instructions.............................................................................85
7.10. BIT definition.........................................................................................................................85
©Copyright 2020, PADAUK Technology Co. Ltd
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8bit OTP Type SuLED IO Controller
8. Code Options......................................................................................................................86
9. Special Notes......................................................................................................................87
9.1.
9.2.
Warning ................................................................................................................................87
Using IC................................................................................................................................87
9.2.1. IO pin usage and setting............................................................................................87
9.2.2. Interrupt.....................................................................................................................88
9.2.3. System clock switching..............................................................................................88
9.2.4. Watchdog..................................................................................................................88
9.2.5. TIMER time out .........................................................................................................89
9.2.6. IHRC .........................................................................................................................89
9.2.7. LVR...........................................................................................................................89
9.2.8. Programming Writing.................................................................................................89
Using ICE..............................................................................................................................91
9.3.
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
Revision History:
Revision
Date
Description
0.01
2017/07/21 1st version
1. Amend the address and phone number of PADAUK Technology Co.,Ltd.
2. Amend Section 1.3 CPU Features
3. Amend Section 4.1 AC/DC Device Characteristics
4. Amend Section 4.3 Typical ILRC frequency vs. VDD
5. Amend Section 4.4 Typical IHRC frequency deviation vs. VDD
6. Amend Section 4.5 Typical ILRC Frequency vs. Temperature
7. Amend Section 4.6 Typical IHRC Frequency vs. Temperature
8. Amend Section 4.7 Typical operating current vs. VDD @ system clock = ILRC/n
9. Amend Section 4.8 Typical operating current vs. VDD @ system clock = IHRC/n
10. Amend Section 4.9 Typical operating current vs. VDD @ system clock = 4MHz EOSC / n
11. Amend Section 4.10 Typical operating current vs. VDD @ system clock = 32KHz EOSC / n
12. Amend Section 4.11 Typical operating current vs. VDD @ system clock = 1MHz EOSC / n
13. Amend Section 4.13 Typical IO input high/low threshold voltage (VIH/VIL)
14. Amend Section 4.15 Typical power down current and power save current
15. Delete Section 4.16 Timing charts for boot up conditions
16. Amend Section 5.1. Program Memory – OTP
17. Add Section 5.2.1 Timing charts for reset conditions
18. Amend Table 2: Three oscillation circuits
19. Amend Section 5.4.3. IHRC Frequency Calibration and System Clock
20. Amend Section 5.4.4. External Crystal Oscillator
21. Amend Section 5.4.5. System Clock and LVR level
22. Amend Fig.3: Options of System Clock
0.02
2018/01/24
23. Amend Section 5.5.2. Using the comparator
24. Amend Section 5.5.3 Using the comparator and band-gap 1.20V
25. Amend Section 5.10 Interrupt
26. Amend Section 5.11.1 Power-Save mode
27. Amend Section 5.11.2 Power-Down mode
28. Amend Section 5.11.3 Wake-up
29. Amend Section 6.3. Clock Mode Register
30. Amend Section 6.7 MISC Register
31. Amend Section 6.10. Port A Digital Input Enable Register
32. Amend Section 6.11. Port B Digital Input Enable Register
33. Delete Section 6.13. MISC2 Register
34. Amend Section 6.14. Port A Pull-High Register
35. Amend Section 6.19. Comparator Selection Register.
36. Amend Section 6.20. Timer2 Control Register
37. Amend Section 6.21. Timer2 Scalar Register
38. Delete the Symbol “pc0” in Chapter 7
39. Amend Chapter 8 Code Options
40. Amend Section 9.2.1. IO pin usage and setting
41. Amend Section 9.2.7 LVR
42. Amend Section 9.2.9 BIT definition
43. Amend Section 9.2.10. Programming Writing
44. Amend Section 9.3. Using ICE
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
1. Amend Section 1.1 Special Features
2. Open 32KHz EOSC mode
3. Amend Section 5.4.4 External Crystal Oscillator
4. Amend Section 5.7 8-bit Timer (Timer2) with PWM generation
5. Add Fig.12：Comparator controls the output of PWM waveform
6. Amend Section 5.8.3 Equations for 11-bit PWM Generator
7. Amend Section 5.10 Interrupt
8. Amend Section 5.11.1 Power-Save mode
9. Amend Table 6: Differences in wake-up sources between Power-Save mode and
Power-Down mode
1.03
2018/11/13
10. Amend Section 6.29 PWMG Counter Upper Bound Low Register
11. Amend Section 7.8 Summary of Instructions Execution Cycle and delete 9.2.8
12. Move Section 9.2.9 BIT definition to Section 7.10
13. Updated the link in Section 9.1
14. Amend Section 9.2.5 TIMER time out
15. Amend Section 9.2.8 Programming Writing
16. Amend Section 9.3 Using ICE
1. Amend Section 1.2 System Features
2. Amend SOP14 Pin Definition and Functional Description
3. Amend Section 4.1 and 4.6
4. Amend Section 5.2.1 Timing charts for reset conditions
5. Amend Section 5.7, 5.7.1, 5.7.2, 5.7.3
1.04
2019/10/17 6. Amend Section 5.8.3 Equations for 11-bit PWM Generator
7. Add Section 5.8.4 PWM Waveforms with Complementary Dead Zones
8. Amend Section 5.11.1, 5.11.2, 5.11.3
9. Amend Section 6.3 , 6.10, 6.11,
10. Amend Chapter 8 Code Options
11. Amend Section 9.2.8 Programming Writing
1. Amend 4.1 AC/DC Device Characteristics: tWUP, tSBP
2020/06/09 2. Amend Chapter 8
1.05
3. Amend 5.4.6, 5.8, 5.8.3, 5.12, 5.13.2, 6.18, 9.3
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
1. Features
1.1. Special Features
General purpose series
Not supposed to use in AC RC step-down powered or high EFT requirement applications.
PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.
Operating temperature range: -20°C ~ 70°C
1.2. System Features
1.25KW OTP program memory
80 Bytes data RAM
One hardware 16-bit timer
One hardware 8-bit timers with 6/7/8-bit PWM generation
One set triple 11bit SuLED (Super LED) PWM generators and timers
One hardware comparator
14 IO pins with optional pull-high resistor
Three different IO Driving capability group to meet different application requirements
(1) PB3, PB5, PB7 Drive/ Sink Current= 7mA/30mA
(2) Other IOs (except PA5) Drive/ Sink Current = 7mA/14mA
(3) PA5 Sink Current = 4mA
Every IO pin can be configured to enable wake-up function
Clock sources: IHRC, ILRC & EOSC(XTAL mode)
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast
Eight levels of LVR: 4.5V, 3.5V, 3.0V, 2.7V, 2.5V, 2.2V, 2.0V and 1.8V
Two selectable external interrupt pins: PA0/PB5, PB0/PA4
Band-gap circuit to provide 1.20V reference voltage
1.3. CPU Features
One processing unit operating mode
86 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer to provide adjustable stack level
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer
of Indirect addressing mode
IO space and memory space are independent
1.4. Package Information
PMS152-S16: SOP16 (150mil)
PMS152-1J16A: QFN3*3-16pin (0.5mm pitch)
PMS152-S14: SOP14 (150mil)
PMS152-M10: MSOP10 (118mil)
PMS152-S08: SOP8 (150mil)
PMS152-U06: SOT23-6 (60mil)
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
2. General Description and Block Diagram
The PMS152 family is an IO-Type, fully static, OTP-based CMOS 8-bit microcontroller. It employs RISC
architecture and all the instructions are executed in one cycle except that some instructions are two cycles that
handle indirect memory access.
1.25KW bits OTP program memory and 80 bytes data SRAM are inside, one hardware comparator is built inside
the chip to compare signal between two pin or with either internal reference voltage VinternalR or internal band-gap
reference voltage. PMS152 also provides three hardware timers: one 16-bit timer, one 8-bit timer with PWM
generation, and one new triple 11-bit timer with SuLED PWM generation (PWMG0, PWMG1 & PWMG2) are
included.
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
3. Pin Definition and Functional Description
PMS152-S16 (SOP16-150mil)
PMS152-1J16A (QFN3*3-16P-0.5pitch)
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PMS152
8bit OTP Type SuLED IO Controller
PMS152-S14 (SOP14-150mil)
PMS152-M10 (MSOP10-118mil)
PMS152-S08 (SOP8-150mil)
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PMS152
8bit OTP Type SuLED IO Controller
PMS152-U06 (SOT23-6 60mil)
Description
Pin Type &
Buffer Type
Pin Name
The functions of this pin can be:
(1) Bit 7 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
IO
PA7 /
X1
ST /
(2) X1 is Crystal XIN when crystal oscillator is used.
CMOS
If this pin is used for crystal oscillator, bit 7 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 7 of padier register is “0”.
The functions of this pin can be:
(1) Bit 6 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
IO
PA6 /
X2
ST /
(2) X2 is Crystal XOUT when crystal oscillator is used.
CMOS
If this pin is used for crystal oscillator, bit 6 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 6 of padier register is “0”.
The functions of this pin can be:
(1) Bit 5 of port A. It can be configured as digital input or open-drain output, with
pull-high resistor.
PA5 /
IO (OD)
ST /
PRSTB /
PG2PWM
(2) Hardware reset.
(3) Output of 11-bit PWM generator PWMG2.
CMOS
This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”. Please put 33Ω resistor in
series to have high noise immunity when this pin is in input mode.
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 4 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
PA4 /
CIN+ /
(2) Plus input source of comparator.
(3) Minus input source 1 of comparator.
IO
CIN1- /
INT1A /
PG1PWM
(4) External interrupt line 1A. It can be used as an external interrupt line 1. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting
ST /
CMOS /
Analog
(5) Output of 11-bit PWM generator PWMG1.
When this pin is configured as analog input, please use bit 4 of register padier to
disable the digital input to prevent current leakage. The bit 4 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 3 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
PA3 /
IO
(2) Minus input source 0 of comparator.
CIN0- /
ST /
(3) PWM output from Timer2
TM2PWM /
PG2PWM
CMOS /
Analog
(4) Output of 11-bit PWM generator PWMG2
When this pin is configured as analog input, please use bit 3 of register padier to
disable the digital input to prevent current leakage. The bit 3 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as digital input or two-state output, with
pull-high resistor.
PA0 /
CO /
(2) Output of comparator.
IO
(3) Output of 11-bit PWM generator PWMG0.
(4) External interrupt line 0. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting
ST /
PG0PWM /
INT0
CMOS
The bit 0 of padier register can be set to “0” to disable wake-up from power-down by
toggling this pin.
The functions of this pin can be:
(1) Bit 7 of port B. It can be configured as digital input or two-state output, with
pull-high resistor.
IO
PB7 /
CIN5- /
(2) Minus input source 5 of comparator.
ST /
(3) Output of 11-bit PWM generator PWMG1.
CMOS /
Analog
PG1PWM
When this pin is configured as analog input, please use bit 7 of register pbdier to
disable the digital input to prevent current leakage. The bit 7 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 6 of port B. It can be configured digital input or two-state output, with pull-high
resistor.
PB6 /
CIN4- /
IO
(2) Minus input source 4 of comparator.
ST /
(3) Output of 11-bit PWM generator PWMG1.
PG1PWM
CMOS /
Analog
When this pin is configured as analog input, please use bit 6 of register pbdier to
disable the digital input to prevent current leakage. The bit 6 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 5 of port B. It can be configured as digital input or two-state output, with
pull-high resistor.
PB5 /
PG0PWM /
INT0A
IO
(2) Output of 11-bit PWM generator PWMG0.
ST /
(3) External interrupt line 0A. It can be used as an external interrupt line 0. Both
rising edge and falling edge are accepted to request interrupt service and
configurable by register setting.
CMOS
The bit 5 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
The functions of this pin can be:
(1) Bit 4 of port B. It can be configured as digital input or two-state output, with
pull-high resistor.
PB4 /
IO
TM2PWM /
PG0PWM
ST /
(2) PWM output from Timer2
CMOS
(3) Output of 11-bit PWM generator PWMG0.
The bit 4 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
The functions of this pin can be:
(1) Bit 3 of port B. It can be configured as digital input or two-state output, with
pull-high resistor.
IO
PB3 /
ST /
PG2PWM
(2) Output of 11-bit PWM generator PWMG2
CMOS
The bit 3 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
The functions of this pin can be:
(1) Bit 2 of port B. It can be configured as digital input or two-state output, with
pull-high resistor.
PB2 /
IO
TM2PWM /
PG2PWM
ST /
(2) PWM output from Timer2
CMOS
(3) Output of 11-bit PWM generator PWMG2
The bit 2 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
©Copyright 2020, PADAUK Technology Co. Ltd
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PMS152
8bit OTP Type SuLED IO Controller
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
IO
Bit 1 of port B. It can be configured as digital input or two-state output, with pull-high
resistor.
PB1
ST /
CMOS
The bit 1 of pbdier register can be set to “0” to disable digital input; wake-up from
power-down by toggling this pin is also disabled.
The functions of this pin can be:
(1) Bit 0 of port B. It can be configured as digital input or two-state output, with
pull-high resistor.
IO
PB0 /
INT1
(2) External interrupt line 1. It can be used as an external interrupt line 1. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
ST /
CMOS
If bit 0 of pbdier register is set to “0” to disable digital input, wake-up from
power-down by toggling this pin is also disabled.
VDD
GND
VDD
GND
Positive power
Ground
Notes: IO: Input/Output; ST: Schmitt Trigger input; OD: Open Drain; Analog: Analog input pin
CMOS: CMOS voltage level
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PMS152
8bit OTP Type SuLED IO Controller
4. Device Characteristics
4.1. AC/DC Device Characteristics
All data are acquired under the conditions of Ta= -20 oC ~ 70 oC, VDD=5.0V, fSYS =2MHz unless noted.
Symbol
Description
Operating Voltage
Min
1.8*
-5
Typ
Max
5.5
5
Unit
V
Conditions (Ta=25oC)
VDD
5.0
* Subject to LVR tolerance
LVR% Low Voltage Reset Tolerance
System clock (CLK)* =
IHRC/2
%
0
0
0
8M
4M
2M
V
V
V
DD ≧ 3.5V
DD ≧ 2.5V
DD ≧ 1.8V
fSYS
IHRC/4
Hz
IHRC/8
ILRC
55K
1.8*
1
VDD = 3.0V
VPOR
IOP
Power On Reset Voltage
V
* Subject to LVR tolerance
mA fSYS=IHRC/16=1MIPS@5.0V
uA fSYS=ILRC=55KHz@3.3V
uA fSYS= 0Hz, VDD =5.0V
Operating Current
15
1
Power Down Current
(by stopsys command)
Power Save Current
(by stopexe command)
IPD
0.6
uA fSYS= 0Hz, VDD =3.3V
VDD =5.0V; fSYS= ILRC
IPS
VIL
5
uA
V
Only ILRC module is enabled.
Input low voltage for IO lines
0
0.1 VDD
VDD
0.8 VDD
0.7 VDD
PA5
VIH
Input high voltage for IO lines
V
VDD
Others IO
IO lines sink current
PA7, PA6, PA4, PA3, PA0
PB6, PB4, PB2, PB1, PB0
PB7, PB5, PB3
14
IOL
14
mA VDD=5.0V, VOL=0.5V
30
PA5
4
IO lines drive current
PA5
0
PA7, PA6, PA4, PA3, PA0
PB7, PB6, PB5, PB4, PB3
PB2, PB1, PB0
-7
-7
-7
IOH
mA VDD=5.0V, VOH=4.5V
VIN
Input voltage
-0.3
VDD +0.3
V
VDD +0.3≧VIN≧ -0.3
IINJ (PIN) Injected current on pin
mA
1
100
200
VDD =5.0V
VDD =3.0V
RPH
VBG
Pull-high Resistance
KΩ
V
DD =2.2V ~ 5.5V
Band-gap Reference Voltage
1.145*
15.76*
15.20*
1.20*
16*
1.255*
16.24*
16.80*
V
-20oC <Ta<70oC*
25oC, VDD =2.2V~5.5V
MHz
VDD =2.2V~5.5V,
Frequency of IHRC after
16*
fIHRC
-20oC <Ta<70oC*
VDD =1.8V~5.5V,
-20oC <Ta<70oC
calibration *
13.60*
16*
18.40*
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
Symbol
tINT
Description
Interrupt pulse width
Min
30
Typ
Max
Unit
ns
Conditions (Ta=25oC)
VDD = 5.0V
VDR
RAM data retention voltage*
1.5
V
in stop mode
8k
misc[1:0]=00 (default)
misc[1:0]=01
16k
64k
tWDT
Watchdog timeout period
TILRC
misc[1:0]=10
256k
misc[1:0]=11
Wake-up time period for fast
wake-up
45
Where TILRC is the time
period of ILRC
tWUP
TILRC
Wake-up time period for slow
wake-up
3000
System boot-up period from
power-on for Slow boot-up
System boot-up period from
power-on for Fast boot-up
External reset pulse width
55
ms
us
tSBP
VDD =5V
820
tRST
120
0
us
mV
V
@ VDD =5V
CPos
CPcm
CPspt
Comparator offset*
±10
±20
VDD -1.5
500
Comparator input common mode*
Comparator response time**
Stable time to change comparator
mode
100
2.5
20
ns
Both Rising and Falling
VDD = 3.3V
CPmc
CPcs
7.5
us
Comparator current consumption
uA
*These parameters are for design reference, not tested for each chip.
4.2. Absolute Maximum Ratings
Supply Voltage ............................................
1.8V ~ 5.5V (Maximum Rating: 5.5V)
*If VDD is over the maximum rating, it may lead to a permanent damage of IC.
Input Voltage …………………………………..
Operating Temperature ………………………
Storage Temperature …………………………
Junction Temperature ………………………..
-0.3V ~ VDD + 0.3V
-20°C ~ 70°C
-50°C ~ 125°C
150°C
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PMS152
8bit OTP Type SuLED IO Controller
4.3. Typical ILRC frequency vs. VDD
4.4. Typical IHRC frequency deviation vs. VDD(calibrated to 16MHz)
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PMS152
8bit OTP Type SuLED IO Controller
4.5. Typical ILRC Frequency vs. Temperature
4.6. Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
4.7. Typical operating current vs. VDD @ system clock = ILRC/n
Conditions:
ON: Band-gap, LVR, ILRC; OFF: IHRC, EOSC, T16, TM2;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
ILRC/n vs. VDD
45
ILRC/1
40
ILRC/4
ILRC/16
35
30
25
20
15
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
4.8. Typical operating current vs. VDD @ system clock = IHRC/n
Conditions:
ON: Band-gap, LVR, IHRC; OFF: ILRC, EOSC, T16, TM2;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
IHRC/n vs. VDD
1.4
1.2
1
IHRC/2
IHRC/4
IHRC/8
IHRC/16
IHRC/32
IHRC/64
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
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PMS152
8bit OTP Type SuLED IO Controller
4.9. Typical operating current vs. VDD @ system clock = 4MHz EOSC / n
Conditions:
ON: Band-gap, LVR , EOSC; OFF:, IHRC, ILRC, T16, TM2;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
4.10.Typical operating current vs. VDD @ system clock = 32KHz EOSC / n
Conditions:
ON: Band-gap, LVR, EOSC; OFF: IHRC, ILRC, T16, TM2;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
4.11.Typical operating current vs. VDD @ system clock = 1MHz EOSC / n
Conditions:
ON: Band-gap, LVR, EOSC; OFF: IHRC, ILRC, T16, TM2;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
4.12.Typical IO driving current (IOH) and sink current (IOL)
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PMS152
8bit OTP Type SuLED IO Controller
IoL vs. VDD
40
35
30
25
20
15
10
5
PA5
PB3/PB5/PB7
Others
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
4.13. Typical IO input high/low threshold voltage (VIH/VIL)
Vih, Vil vs. VDD
4.0
3.5
Vih Others
Vih PA5
Vil PA5
Vil Others
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
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PMS152
8bit OTP Type SuLED IO Controller
4.14. Typical resistance of IO pull high device
4.15. Typical power down current (IPD) and power save current (IPS)
stopsys power down current vs. VDD
0.7
0.6
0.5
0.4
0.3
stopsys
0.2
0.1
0
2.0 2.5
3.0 3.5 4.0 4.5
VDD (V)
5.0 5.5
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
stopexe power down current vs. VDD
3.5
3
2.5
2
1.5
1
stopexe
0.5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
5. Functional Description
5.1. Program Memory - OTP
The OTP (One Time Programmable) program memory is used to store the program instructions to be executed.
The OTP program memory may contains the data, tables and interrupt entry. After reset, the initial address
0x000 is reserved for system using, so the program will start from 0x001 which is GOTO FPPA0 instruction
usually. The interrupt entry is 0x10 if used, the last 16 addresses are reserved for system using, like checksum,
serial number, etc. The OTP program memory for PMS152 is 1.25KW that is partitioned as Table 1. The OTP
memory from address ‘0x4E6 to 0x4FF is for system using, address space from0x002 to 0x00F and from
0x011 to 0x4E5 are user program spaces.
Address
0x000
0x001
0x002
•
Function
System Using
GOTO FPPA0 instruction
User program
•
0x00F
0x010
0x011
•
User program
Interrupt entry address
User program
•
0x4E5
0x4E6
•
User program
System Using
•
0x4FF
System Using
Table 1: Program Memory Organization
5.2. Boot Procedure
POR (Power-On-Reset) is used to reset PMS152 when power up. The boot up time can be optional fast or
normal. Time for fast boot-up is about 47 ILRC clock cycles whereas 2945 ILRC clock cycles for normal
boot-up. Customer must ensure the stability of supply voltage after power up no matter which option is chosen,
the power up sequence is shown in the Fig. 1 and tSBP is the boot up time.
Please noted, during Power-On-Reset, the VDD must go higher than VPOR to boot-up the MCU.
Fig.1: Power-Up Sequence
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PMS152
8bit OTP Type SuLED IO Controller
5.2.1. Timing charts for reset conditions
LVR level
SBP
VDD
LVR
t
Program
Execution
Boot up from LVR detection
VDD
t
SBP
WD
Time Out
Program
Execution
Boot up from Watch Dog Time Out
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PMS152
8bit OTP Type SuLED IO Controller
5.3. Data Memory - SRAM
The access of data memory can be byte or bit operation. Besides data storage, the SRAM data memory is also
served as data pointer of indirect access method and the stack memory.
The stack memory is defined in the data memory. The stack pointer is defined in the stack pointer register; the
depth of stack memory of each processing unit is defined by the user. The arrangement of stack memory fully
flexible and can be dynamically adjusted by the user.
For indirect memory access mechanism, the data memory is used as the data pointer to address the data byte.
All the data memory could be the data pointer; it’s quite flexible and useful to do the indirect memory access.
Since the data width is 8-bit, all the 80 bytes data memory of PMS152 can be accessed by indirect access
mechanism.
5.4. Oscillator and Clock
There are three oscillator circuits provided by PMS152: external crystal oscillator (EOSC), internal high RC
oscillator (IHRC) and internal low RC oscillator (ILRC), and these three oscillators are enabled or disabled by
registers eoscr.7, clkmd.4 and clkmd.2 independently. User can choose one of these three oscillators as
system clock source and use clkmd register to target the desired frequency as system clock to meet different
applications.
Oscillator Module
EOSC
Enable/Disable
eoscr.7
IHRC
clkmd.4
ILRC
clkmd.2
Table 2: Three oscillation circuits
5.4.1. Internal High RC oscillator and Internal Low RC oscillator
After boot-up, the IHRC and ILRC oscillators are enabled. The frequency of IHRC can be calibrated to
eliminate process variation by ihrcr register; normally it is calibrated to 16MHz. Please refer to the
measurement chart for IHRC frequency verse VDD and IHRC frequency verse temperature.
The frequency will vary by process, supply voltage and temperature, please refer to DC specification and do
not use for accurate timing application.
5.4.2. Chip calibration
The IHRC frequency and band-gap reference voltage may be different chip by chip due to manufacturing
variation, PMS152 provide the IHRC frequency calibration to eliminate this variation, and this function can be
selected when compiling user’s program and the command will be inserted into user’s program automatically.
The calibration command is shown as below:
.ADJUST_IC SYSCLK=IHRC/(p1), IHRC=(p2)MHz, VDD=(p3)V;
Where, p1=2, 4, 8, 16, 32; In order to provide different system clock.
p2=14 ~ 18; In order to calibrate the chip to different frequency, 16MHz is the usually one.
p3=1.8 ~ 5.5; In order to calibrate the chip under different supply voltage.
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
5.4.3. IHRC Frequency Calibration and System Clock
During compiling the user program, the options for IHRC calibration and system clock are shown as Table 3:
SYSCLK
○ Set IHRC / 2
○ Set IHRC / 4
○ Set IHRC / 8
○ Set IHRC / 16
○ Set IHRC / 32
○ Set ILRC
CLKMD
IHRCR
Calibrated
Calibrated
Calibrated
Description
= 34h (IHRC / 2)
= 14h (IHRC / 4)
= 3Ch (IHRC / 8)
IHRC calibrated to 16MHz, CLK=8MHz (IHRC/2)
IHRC calibrated to 16MHz, CLK=4MHz (IHRC/4)
IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)
IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)
IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)
IHRC calibrated to 16MHz, CLK=ILRC
= 1Ch (IHRC / 16) Calibrated
= 7Ch (IHRC / 32) Calibrated
= E4h (ILRC / 1)
No change
Calibrated
○ Disable
No Change IHRC not calibrated, CLK not changed
Table 3: Options for IHRC Frequency Calibration
Usually, .ADJUST_IC will be the first command after boot up, in order to set the target operating frequency
whenever starting the system. The program code for IHRC frequency calibration is executed only one time that
occurs in writing the codes into OTP memory; after then, it will not be executed again. If the different option for
IHRC calibration is chosen, the system status is also different after boot. The following shows the status of
PMS152 for different option:
(1) .ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0x34：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/2 = 8MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(2) .ADJUST_IC
SYSCLK=IHRC/4, IHRC=16MHz, VDD=3.3V
After boot up, CLKMD = 0x14：
IHRC frequency is calibrated to 16MHz@VDD=3.3V and IHRC module is enabled
System CLK = IHRC/4 = 4MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(3) .ADJUST_IC
SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V
After boot up, CLKMD = 0x3C：
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/8 = 2MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.5V
(4) .ADJUST_IC
After boot up, CLKMD = 0x1C：
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/16 = 1MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(5) .ADJUST_IC
SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0x7C：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/32 = 500KHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
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8bit OTP Type SuLED IO Controller
(6) .ADJUST_IC
SYSCLK=ILRC, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0XE4：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is disabled
System CLK = ILRC
Watchdog timer is disabled, ILRC is enabled, PA5 is input mode
(7) .ADJUST_IC
DISABLE
After boot up, CLKMD is not changed (Do nothing)：
IHRC is not calibrated
System CLK = ILRC or IHRC/64 (by Boot-up_Time)
Watchdog timer is enabled, ILRC is enabled, PA5 is in input mode,
5.4.4. External Crystal Oscillator
If crystal oscillator is used, a crystal or resonator is required between X1 and X2. Fig.2 shows the hardware
connection under this application; the range of operating frequency of crystal oscillator can be from 32 KHz to
4MHz, depending on the crystal placed on; higher frequency oscillator than 4MHz is NOT supported.
(Select driving current for oscillator)
eoscr[6:5]
(Enable crystal oscillator)
eoscr.7
C1
PA7/X1
System clock = EOSC
PA6/X2
C2
The values of C1 and C2 should depend on
the specification of crystal.
Fig.2: Connection of crystal oscillator
Besides crystal, external capacitor and options of PMS152 should be fine tuned in eoscr (0x0a) register to
have good sinusoidal waveform. The eoscr.7 is used to enable crystal oscillator module, eoscr.6 and eoscr.5
are used to set the different driving current to meet the requirement of different frequency of crystal oscillator:
eoscr.[6:5]=01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
eoscr.[6:5]=10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
eoscr.[6:5]=11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
Table 4 shows the recommended values of C1 and C2 for different crystal oscillator; the measured start-up
time under its corresponding conditions is also shown. Since the crystal or resonator had its own characteristic,
the capacitors and start-up time may be slightly different for different type of crystal or resonator, please refer to
its specification for proper values of C1 and C2.
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PMS152
8bit OTP Type SuLED IO Controller
Measured
Frequency
C1
C2
Conditions
(eoscr[6:5]=11)
Start-up time
6ms
4MHz
1MHz
32KHz
4.7pF
10pF
22pF
4.7pF
10pF
22pF
11ms
(eoscr[6:5]=10)
(eoscr[6:5]=01)
450ms
Table 4: Recommend values of C1 and C2 for crystal and resonator oscillators
When using the crystal oscillator, user must pay attention to the stable time of oscillator after enabling it, the
stable time of oscillator will depend on frequency “crystal type” external capacitor and supply voltage. Before
switching the system to the crystal oscillator, user must make sure the oscillator is stable; the reference
program is shown as below:
void
{
FPPA0 (void)
. ADJUST_IC SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V
$ EOSCR
Enable, 4MHz;
// EOSCR = 0b110_00000;
$ T16M
EOSC, /1, BIT13;
// while T16.Bit13 0 => 1, Intrq.T16 => 1
// suppose crystal EOSC Is stable
WORD
count =
=
0;
stt16 count;
Intrq.T16
0;
while(!Intrq.T16) { nop; };
// count from 0x0000 to 0x2000, then trigger INTRQ.T16
// switch system clock to EOSC;
// disable IHRC
clkmd
=
0xB4;
Clkmd.4 = 0;
...
}
Please notice that the crystal oscillator should be fully turned off before entering the power-down mode, in
order to avoid unexpected wake-up event.
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8bit OTP Type SuLED IO Controller
5.4.5. System Clock and LVR level
The clock source of system clock comes from EOSC, IHRC and ILRC, the hardware diagram of system clock
in the PMS152 is shown as Fig.3.
clkmd
÷2, ÷4, ÷8,
IHRC
clock
÷16, ÷32, ÷64
System
clock
CLK
M
U
X
EOSC
clock
÷1, ÷2, ÷4, ÷8
ILRC
÷1, ÷4, ÷16
clock
Fig.3: Options of System Clock
User can choose different operating system clock depends on its requirement; the selected operating system
clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be
selected during compilation. Please refer to Section 4.1.
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8bit OTP Type SuLED IO Controller
5.4.6. System Clock Switching
After IHRC calibration, user may want to switch system clock to a new frequency or may switch system clock at
any time to optimize the system performance and power consumption. Basically, the system clock of PMS152
can be switched among IHRC, ILRC and EOSC by setting the clkmd register at any time; system clock will be
the new one after writing to clkmd register immediately. Please notice that the original clock module can NOT
be turned off at the same time as writing command to clkmd register. The examples are shown as below and
more information about clock switching, please refer to the “Help” -> “Application Note” -> “IC Introduction” ->
“Register Introduction” -> CLKMD”.
Case 1: Switching system clock from ILRC to IHRC/2
…
//
//
//
//
system clock is ILRC
CLKMD.4
CLKMD
// CLKMD.2
…
=
=
=
1;
turn on IHRC first to improve anti-interference ability
switch to IHRC/2, ILRC CAN NOT be disabled here
if need, ILRC CAN be disabled at this time
0x34；
0；
Case 2: Switching system clock from ILRC to EOSC
…
//
//
//
system clock is ILRC
CLKMD
CLKMD.2
…
=
=
0xA6；
0；
switch to IHRC, ILRC CAN NOT be disabled here
ILRC CAN be disabled at this time
Case 3: Switching system clock from IHRC/2 to ILRC
…
//
//
//
system clock is IHRC/2
CLKMD
CLKMD.4
…
=
=
0xF4；
0；
switch to ILRC, IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
Case 4: Switching system clock from IHRC/2 to EOSC
…
//
//
//
system clock is IHRC/2
CLKMD
CLKMD.4
…
=
=
0XB0；
0；
switch to EOSC, IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
Case 5: Switching system clock from IHRC/2 to IHRC/4
…
//
//
system clock is IHRC/2, ILRC is enabled here
switch to IHRC/4
CLKMD
…
=
0X14；
Case 6: System may hang if it is to switch clock and turn off original oscillator at the same time
…
//
system clock is ILRC
CLKMD
=
0x30；
//
CAN NOT switch clock from ILRC to IHRC/2 and
turn off ILRC oscillator at the same time
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PMS152
8bit OTP Type SuLED IO Controller
5.5. Comparator
One hardware comparator is built inside the PMS152; Fig.4 shows its hardware diagram. It can compare
signals between two pins or with either internal reference voltage Vinternal R or internal band-gap reference
voltage. The two signals to be compared, one is the plus input and the other one is the minus input. For the
minus input of comparator can be PA3, PA4, Internal band-gap 1.20 volt, PB6, PB7 or Vinternal R selected by bit
[3:1] of gpcc register, and the plus input of comparator can be PA4 or Vinternal R selected by bit 0 of gpcc register.
The output result can be enabled to output to PA0 directly, or sampled by Time2 clock (TM2_CLK) which
comes from Timer2 module. The output can be also inversed the polarity by bit 4 of gpcc register, the
comparator output can be used to request interrupt service.
16 stages
VDD
gpcs.5=1
gpcs.4=0
gpcs.4=1
gpcs.5=0
MUX
gpcs[3:0]
Vinternal R
gpcc[3:1]
PA3/CIN0-
PA4/CIN1-
Band-gap
000
001 M
gpcc.4
To request interrupt
gpcc.6
010 U
011 X
100
X
O
R
-
PB6/CIN4-
PB7/CIN5-
M
U
X
101
+
D
F
F
To
PA0
0
Timer 2
clock
MUX
1
PA4/CIN+
gpcc.0
TM2_CLK
gpcc.5
gpcs.7
Fig.4: Hardware diagram of comparator
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8bit OTP Type SuLED IO Controller
5.5.1 Internal reference voltage (Vinternal R
)
The internal reference voltage Vinternal R is built by series resistance to provide different level of reference
voltage, bit 4 and bit 5 of gpcs register are used to select the maximum and minimum values of Vinternal R
and bit [3:0] of gpcs register are used to select one of the voltage level which is deivided-by-16 from the
defined maximum level to minimum level. Fig.5 to Fig.8 shows four conditions to have different reference
voltage Vinternal R. By setting the gpcs register, the internal reference voltage Vinternal R can be ranged from
(1/32)*VDD to (3/4)*VDD.
Case 1 : gpcs.5=0 & gpcs.4=0
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/4) VDD ~ (1/4) VDD + (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
4
(n+1)
32
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig.5: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=0
Case 2 : gpcs.5=0 & gpcs.4= 1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (2/3) VDD ~ (1/24) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
24
Fig.6: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=1
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
Case 3 : gpcs.5=1 & gpcs.4= 0
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/5) VDD ~ (1/5) VDD + (1/40) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
5
(n+1)
40
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig.7: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=0
Case 4 : gpcs.5=1 & gpcs.4=1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (1/2) VDD ~ (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
32
Fig.8: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=1
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
5.5.2
Using the comparator
Case I:
Choosing PA3 as minus input and Vinternal R with (18/32)*VDD voltage level as plus input. Vinternal R is
configured as the above Figure “gpcs[5:4] = 2b’00” and gpcs [3:0] = 4b’1001 (n=9) to have Vinternal R
(1/4)*VDD + [(9+1)/32]*VDD = [(9+9)/32]*VDD = (18/32)*VDD.
=
gpcs = 0b1_0_00_1001;
gpcc = 0b1_0_0_0_000_0;
padier = 0bxxxx_0_xxx;
// Vinternal R = VDD*(18/32)
// enable comp, - input: PA3, + input: Vinternal R
// disable PA3 digital input to prevent leakage current
or
$ GPCS
$ GPCC
V
DD*18/32;
Enable, N_PA3, P_R;
// - input: N_xx，+ input: P_R(Vinternal R
)
PADIER = 0bxxxx_0_xxx;
Case 2:
Choosing Vinternal R as minus input with (22/40)*VDD voltage level and PA4 as plus input, the comparator
result will be inversed and then output to PA0. Vinternal R is configured as the above Figure “gpcs[5:4] =
2b’10” and gpcs [3:0] = 4b’1101 (n=13) to have Vinternal R = (1/5)*VDD + [(13+1)/40]*VDD = [(13+9)/40]*VDD
(22/40)*VDD.
=
gpcs = 0b1_0_10_1101;
gpcc = 0b1_0_0_1_011_1;
padier = 0bxxx_0_xxxx;
// output to PA0, Vinternal R = VDD*(22/40)
// Inverse output, - input: Vinternal R, + input: PA4
// disable PA4 digital input to prevent leakage current
or
$ GPCS
$ GPCC
Output, VDD*22/40;
Enable, Inverse, N_R, P_PA4; // - input: N_R(Vinternal R)，+ input: P_xx
PADIER = 0bxxx_0_xxxx;
Note: When selecting output to PA0 output, GPCS will affect the PA3 output function in ICE. Though the IC
is fine, be careful to avoid this error during emulation.
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8bit OTP Type SuLED IO Controller
5.5.3 Using the comparator and band-gap 1.20V
The internal band-gap module can provide 1.20 volt, it can measure the external supply voltage level. The
band-gap 1.20 volt is selected as minus input of comparator and Vinternal R is selected as plus input, the
supply voltage of Vinternal R is VDD, the VDD voltage level can be detected by adjusting the voltage level of
Vinternal R to compare with band-gap. If N (gpcs[3:0] in decimal) is the number to let Vinternal R closest to
band-gap 1.20 volt, the supply voltage VDD can be calculated by using the following equations:
For using Case 1: VDD = [ 32 / (N+9) ] * 1.20 volt ;
For using Case 2: VDD = [ 24 / (N+1) ] * 1.20 volt ;
For using Case 3: VDD = [ 40 / (N+9) ] * 1.20 volt ;
For using Case 4: VDD= [ 32 / (N+1) ] * 1.20 volt ;
Case 1:
$ GPCS VDD*12/40;
// 4.0V * 12/40 = 1.2V
$ GPCC Enable, BANDGAP, P_R; // - input: BANDGAP, + input: P_R(Vinternal R
)
….
if (GPC_Out)
// or GPCC.6
{
//
//
when VDD﹥4V
}
else
{
}
when VDD﹤4V
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
5.6 16-bit Timer (Timer16)
A 16-bit hardware timer (Timer16) is implemented in the PMS152, the clock sources of Timer16 may come
from system clock (CLK), clock of external crystal oscillator (EOSC), internal high RC oscillator (IHRC),
internal low RC oscillator (ILRC), PA4 and PA0, a multiplex is used to select clock output for the clock source.
Before sending clock to the counter16, a pre-scaling logic with divided-by-1, 4, 16, and 64 is used for wide
range counting. The 16-bit counter performs up-counting operation only, the counter initial values can be
stored from memory by stt16 instruction and the counting values can be loaded to memory by ldt16 instruction.
A selector is used to select the interrupt condition of Timer16, whenever overflow occurs, the Timer16 interrupt
can be triggered. The hardware diagram of Timer16 is shown as Fig.9. The interrupt source of Timer16 comes
from one of bit 8 to 15 of 16-bit counter, and the interrupt type can be rising edge trigger or falling edge trigger
which is specified in the bit 5 of integs register (address 0x0C).
PA4
Fig.9: Hardware diagram of Timer16
When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three parameters
to define the Timer16; 1st parameter is used to define the clock source of Timer16, 2nd parameter is used to
define the pre-scalar and the last one is to define the interrupt source. The detail description is shown as
below:
T16M
IO_RW
0x06
$ 7~5:STOP, SYSCLK, X, PA4_F, IHRC, EOSC, ILRC, PA0_F
$ 4~3:/1, /4, /16, /64
// 1st par.
// 2nd par.
// 3rd par.
$ 2~0:BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15
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8bit OTP Type SuLED IO Controller
User can define the parameters of T16M based on system requirement, some examples are shown below and
more examples please refer to “Help Application Note IC Introduction Register Introduction T16M” in
IDE utility.
$ T16M SYSCLK, /64, BIT15;
// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1
// if using System Clock = IHRC / 2 = 8 MHz
// SYSCLK/64 = 8 MHz/64 = 125KHz, about every 512 mS to generate INTRQ.2=1
$ T16M EOSC, /1, BIT13;
// choose (EOSC/1) as clock source, every 2^14 clocks to generate INTRQ.2=1
// if EOSC=32768 Hz, 32768 Hz/(2^14) = 2Hz, every 0.5S to generate INTRQ.2=1
$ T16M PA0_F, /1, BIT8;
// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1
// receiving every 512 times PA0 to generate INTRQ.2=1
$ T16M STOP;
// stop Timer16 counting
If Timer16 is operated at free running, the frequency of interrupt can be described as below:
FINTRQ_T16M = Fclock source ÷ P ÷ 2n+1
Where, F is the frequency of selected clock source to Timer16;
P is the selection of t16m [4:3]; (1, 4, 16, 64)
N is the nth bit selected to request interrupt service, for example: n=10 if bit 10 is selected.
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
5.7 8-bit Timer (Timer2) with PWM generation
An 8-bit hardware timer (Timer2) with PWM generation is implemented in the PMS152. Please refer to Fig.10
shown the hardware diagram of Timer2, the clock sources of Timer2 may come from system clock, internal high
RC oscillator (IHRC), internal low RC oscillator (ILRC), external crystal oscillator (EOSC), PA0, PB0, PA4 and
comparator. Bit [7:4] of register tm2c are used to select the clock of Timer2. If IHRC is selected for Timer2 clock
source, the clock sent to Timer2 will keep running when using ICE in halt state. The output of Timer2 can be
sent to pin PB2, PA3 or PB4, depending on bit [3:2] of tm2c register. A clock pre-scaling module is provided with
divided-by- 1, 4, 16, and 64 options, controlled by bit [6:5] of tm2s register; one scaling module with
divided-by-1~31 is also provided and controlled by bit [4:0] of tm2s register. In conjunction of pre-scaling
function and scaling function, the frequency of Timer2 clock (TM2_CLK) can be wide range and flexible.
The Timer2 counter performs 8-bit up-counting operation only; the counter values can be set or read back by
tm2ct register. The 8-bit counter will be clear to zero automatically when its values reach for upper bound
register in period mode. The upper bound register is used to define the period of timer or duty of PWM. There
are two operating modes for Timer2: period mode and PWM mode; period mode is used to generate periodical
output waveform or interrupt event; PWM mode is used to generate PWM output waveform with optional 6-bit,
7-bit or 8-bit PWM resolution, Fig.11 shows the timing diagram of Timer2 for both period mode and PWM mode.
Fig.10: Timer2 hardware diagram
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8bit OTP Type SuLED IO Controller
Time out and
Time out and
Time out and
Interrupt request
Interrupt request
Interrupt request
Counter
0xFF
bound
Counter
0xFF
Counter
0x3F
bound
bound
Time
Time
Time
Time
Time
Event Trigger
Event Trigger
Event Trigger
Output-pin
Output-pin
Output-pin
Time
Mode 0 – Period Mode
Mode 1 – 8-bit PWM Mode
Mode 1 – 6-bit PWM Mode
Fig.11: Timing diagram of Timer2 in period mode and PWM mode (tm2c.1=1)
A Code Option GPC_PWM is for the applications which need the generated PWM waveform to be controlled by
the comparator result. If the Code Option GPC_PWM is selected, the PWM output stops while the comparator
output is 1 and then the PWM output turns on while the comparator output goes back to 0, as shown in Fig. 12.
PWM Output
Comparator
Output
Fig.12：Comparator controls the output of PWM waveform
5.7.1 Using the Timer2 to generate periodical waveform
If periodical mode is selected, the duty cycle of output is always 50%; its frequency can be summarized as
below:
Frequency of Output = Y ÷ [2 × (K+1) × S1 × (S2+1) ]
Where,
Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1 = tm2s[6:5] : pre-scalar (S1=1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2=0 ~ 31)
Example 1:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ [ 2 × (127＋1) × 1 × (0＋1) ] = 31.25KHz
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8bit OTP Type SuLED IO Controller
Example 2:
Example 3:
Example 4:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s[7:0] = 0b0111_11111, S1=64 , S2 = 31
frequency of output = 8MHz ÷ ( 2 × (127＋1) × 64 × (31＋1) ) =15.25Hz
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_1111, K=15
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 2 × (15＋1) × 1 × (0＋1) ) = 250KHz
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_0001, K=1
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 2 × (1＋1) × 1 × (0＋1) ) =2MHz
The sample program for using the Timer2 to generate periodical waveform from PA3 is shown as below:
Void FPPA0 (void)
{
. ADJUST_IC SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
…
tm2ct = 0x0;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, period mode
tm2c = 0b0001_10_0_0;
while(1)
{
nop;
}
}
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8bit OTP Type SuLED IO Controller
5.7.2 Using the Timer2 to generate 8-bit PWM waveform
If 8-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=0, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [256 × S1 × (S2+1) ]
Duty of Output = [( K＋1 ) ÷ 256]×100%
Where, Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1= tm2s[6:5] : pre-scalar (S1=1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (S2=0 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0111_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 256 × 64 × (31+1) ) = 15.25Hz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b1111_1111, K=255
tm2s = 0b0000_00000, S1=1, S2=0
PWM output keep high
duty of output = [(255+1) ÷ 256] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_1001, K = 9
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(9+1) ÷ 256] × 100% = 3.9%
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8bit OTP Type SuLED IO Controller
The sample program for using the Timer2 to generate PWM waveform from PA3 is shown as below:
void
{
FPPA0 (void)
.ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
wdreset;
tm2ct = 0x0;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA3, PWM mode
tm2c = 0b0001_10_1_0;
while(1)
{
nop;
}
}
5.7.3 Using the Timer2 to generate 6-bit PWM waveform
If 6-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=1, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [64 × S1 × (S2+1) ]
Duty of Output = [( K＋1 ) ÷ 64] × 100%
Where, tm2c[7:4] = Y : frequency of selected clock source
tm2b[7:0] = K : bound register in decimal
tm2s[6:5] = S1 : pre-scalar (S1=1, 4, 16, 64)
tm2s[4:0] = S2 : scalar register in decimal (S2=0 ~ 31)
Users can set Timer2 to be 7-bit PWM mode instead of 6-bit mode by using TM2_Bit code option. At that
time, the calculation factors of the above equations become 128 instead of 64.
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(31+1) ÷ 64] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1111_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 64 × 64 × (31+1) ) = 61.03 Hz
duty of output = [(31+1) ÷ 64] × 100% = 50%
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8bit OTP Type SuLED IO Controller
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0011_1111, K=63
tm2s = 0b1000_00000, S1=1, S2=0
PWM output keep high
duty of output = [(63+1) ÷ 64] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_0000, K=0
tm2s = 0b1000_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(0+1) ÷ 64] × 100% =1.5%
5.8 11-bit PWM Generators
One set of triple 11-bit SuLED (Super LED) hardware PWM generator is implemented in the PMS152. It consists
of three PWM generators (PWMG0, PWMG1 & PWMG2). Their individual outputs are listed as below:
PWMG0 – PA0, PB4, PB5
PWMG1 – PA4, PB6, PB7
PWMG2 – PA3, PB2, PB3, PA5 (open drain output only)
Note: PDK5S-I-S01/2(B) doesn’t support the function of the set of 11-bit SuLED hardware PWM generators.
5.8.1 PWM Waveform
A PWM output waveform (Fig.13) has a time-base (TPeriod = Time of Period) and a time with output high
level (Duty Cycle). The frequency of the PWM output is the inverse of the period (fPWM = 1/TPeriod).
Fig.13: PWM Output Waveform
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8bit OTP Type SuLED IO Controller
5.8.2 Hardware Diagram
Fig.14 shows the hardware diagram of the whole set of SuLED 11-bit hardware PWM generators. Those
three PWM generators use a common Up-Counter and clock source selector to create the time base, and
so the start points (the rising edge) of the PWM cycle are synchronized. The clock source can be IHRC or
system clock. The PWM signal output pins that can be selected via pwmgxc register selection. The period
of PWM waveform is defined by the common PWM upper bound high and low registers, and the duty cycle
of individual PWM waveform is defined by the individual set in the PWM duty high and low registers.
The additional OR and XOR logic of PWMG0 channel is used to create the complementary switching
waveforms with dead zone control. Selecting code option GPC_PWM can also control the generated
PWM waveform by the comparator result.
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8bit OTP Type SuLED IO Controller
Fig.14: Hardware diagram of whole set of triple SuLED 11-bit PWM generators
0x7FF
Counter_Bound[10:1]
Duty[10:0]
Time
Time
Output
Timing Diagram for 11- bit PWM generation
Output
Fig.15: Output Timing Diagram of 11-bit PWM Generator
5.8.3 Equations for 11-bit PWM Generator
PWM Frequency FPWM = F clock source ÷ [ P × (CB10_1 + 1) ]
PWM Duty(in time) = (1 / FPWM) × ( DB10_1 + DB0 × 0.5 + 0.5) ÷ (CB10_1 + 1)
PWM Duty(in percentage) = ( DB10_1 + DB0 × 0.5 + 0.5) ÷ (CB10_1 + 1) × 100%
Where,
P = PWMGCLK [6:4]; pre-scalar P=1, 2, 4, 8, 16, 32, 64, 128
DB10_1 = Duty_Bound[10:1] = {PWMGxDTH[7:0], PWMGxDTL[7:6]}, duty bound
DB0 = Duty_Bound[0] = PWMGxDTL[5]
CB10_1 = Counter_Bound[10:1] = {PWMGCUBH[7:0], PWMGCUBL[7:6]}, counter bound
5.8.4 PWM Waveforms with Complementary Dead Zones
Based on the specific 11 bit PWM architecture of PMS152, here we employ PWM2 output and PWM0 inverse
output after PWM0 xor PWM1 to generate two PWM waveforms with complementary dead zones.
Example program is as follows:
#define dead_zone
#define PWM_Pulse
10
50
//
//
dead time = 10% * (1/PWM_Frequency) us
set 50% as PWM duty cycle
#define PWM_Pulse_1
#define PWM_Pulse_2
35
60
//
//
set 35% as PWM duty cycle
set 60% as PWM duty cycle
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8bit OTP Type SuLED IO Controller
#define switch_time
400*2
//
adjusting switch time
//Note: To avoid noise, switch_time must be a multiple of PWM period. In this example PWM period = 400us,
// so switch_time = 400*2 us.
void FPPA0 (void)
{
.ADJUST_IC
SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V;
//******* Generating fixed duty cycle waveform ************************
//------ Set the counter upper bound and duty cycle -----------------
PWMG0DTL
PWMG0DTH
=
=
0x00;
PWM_Pulse + dead_zone;
PWMG1DTL
PWMG1DTH
=
=
0x00;
dead_zone;
// After PWMG0 xor PWMG, PWM duty cycle=PWM_Pulse%
PWMG2DTL
PWMG2DTH
=
0x00;
=
PWM_Pulse + dead_zone*2;
PWMGCUBL
PWMGCUBH
=
=
0x00;
100;
//---- Configure clock and pre-scalar ------------------
$ PWMGCLK Enable, /1, sysclk;
//------- Output control -----------------------------
$ PWMG0CEnable,Inverse,PWM_Gen,PA0,gen_xor;
//
//
//
//
After PWMG0 xor PWMG,
output the inversed waveform through PA0
disable PWMG1 output
$ PWMG1C Enable, PWMG1,disable;
$ PWMG2C
Enable, PA3;
output PWMG2 waveform through PA3
while(1)
{
//******** Switching duty cycle ********************************
// To avoid the possible instant disappearance of dead zone, user should comply with the following
// instruction sequence.
// When increase the duty cycle: 50%/60%
→
35%
PWMG0DTL =
PWMG0DTH =
PWMG2DTL =
PWMG2DTH =
0x00;
PWM_Pulse_1 + dead_zone;
0x00;
PWM_Pulse_1 + dead_zone*2;
.delay switch_time
// When decrease the duty cycle: 35% → 60%
PWMG2DTL =
PWMG2DTH =
PWMG0DTL =
PWMG0DTH =
0x00;
PWM_Pulse_2 + dead_zone*2;
0x00;
PWM_Pulse_2 + dead_zone;
.delay
switch_time
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8bit OTP Type SuLED IO Controller
}
}
The following figures show the waveforms at different condition.
1. The PWM waveform in a fixed-duty cycle:
PWM2
Dead Zone
PWM0
Fig.16: Complementary PWM waveform with dead zones
2. PWM waveform when switching two duty cycles:
PWM2
Dead Zone
35%
60%
35%
PWM0
Fig.17: Complementary PWM waveform with dead zones
User can find that above example only provides dead zone where PWM are both in high. If need dead zone
where PWM are both in low, you can realize it by resetting each control register’s Inverse like:
$ PWMG0C Enable,PWM_Gen,PA0,gen_xor;
$ PWMG2C Enable, Inverse, PA3;.
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8bit OTP Type SuLED IO Controller
5.9 WatchDog Timer
The watchdog timer (WDT) is a counter with clock coming from ILRC. WDT can be cleared by power-on-reset
or by command wdreset at any time. There are four different timeout periods of watchdog timer to be chosen
by setting the misc register, it is:
8k ILRC clocks period if register misc[1:0]=00 (default)
16k ILRC clocks period if register misc[1:0]=01
64k ILRC clocks period if register misc[1:0]=10
256k ILRC clocks period if register misc[1:0]=11
The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user
should reserve guard band for save operation. Besides, the watchdog period will also be shorter than expected
after Reset or Wakeup events. It is suggested to clear WDT by wdreset command after these events to ensure
enough clock periods before WDT timeout.
When WDT is timeout, PMS152 will be reset to restart the program execution. The relative timing diagram of
watchdog timer is shown as Fig.18.
VDD
t
SBP
WD
Time Out
Program
Execution
Watch Dog Time Out Sequence
Fig.18: Sequence of Watch Dog Time Out
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5.10. Interrupt
There are eight interrupt lines for PMS152:
External interrupt PA0/PB5
External interrupt PB0/PA4
Timer16 interrupt
GPC interrupt
PWMG interrupt
Timer2 interrupt
Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware
diagram of interrupt function is shown as Fig.19. All the interrupt request flags are set by hardware and cleared
by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending
on the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable
global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it.
The stack memory for interrupt is shared with data memory and its address is specified by stack register sp.
Since the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can
use pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack memory.
Since the stack memory is shared with data memory, the stack position and level are arranged by the compiler
in Mini-C project. When defining the stack level in ASM project, users should arrange their locations carefully to
prevent address conflicts.
Fig.19: Hardware diagram of interrupt controller
Once the interrupt occurs, its operation will be:
The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x010.
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8bit OTP Type SuLED IO Controller
During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
Note: Even if INTEN=0, INTRQ will be still triggered by the interrupt source.
After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will be:
The program counter will be restored automatically from the stack memory specified by register sp.
New sp will be updated to sp-2.
Global interrupt will be enabled automatically.
The next instruction will be the original one before interrupt.
User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and four
bytes for two levels interrupt. And so on, two bytes stack memory is for pushaf. For interrupt operation, the
following sample program shows how to handle the interrupt, noticing that it needs four bytes stack memory to
handle one level interrupt and pushaf.
void
{
FPPA0 (void)
...
$
INTEN PA0;
// INTEN =1; interrupt request when PA0 level changed
// clear INTRQ
INTRQ
ENGINT
...
=
0;
// global interrupt enable
DISGINT
...
// global interrupt disable
}
void
{
Interrupt (void)
// interrupt service routine
PUSHAF
// store ALU and FLAG register
// If INTEN.PA0 will be opened and closed dynamically,
// user can judge whether INTEN.PA0 =1 or not.
// Example: If (INTEN.PA0 && INTRQ.PA0) {…}
// If INTEN.PA0 is always enable,
// user can omit the INTEN.PA0 judgement to speed up interrupt service routine.
If (INTRQ.PA0)
{
// Here for PA0 interrupt service routine
INTRQ.PA0 = 0;
// Delete corresponding bit (take PA0 for example)
...
}
...
// X : INTRQ = 0;
// It is not recommended to use INTRQ = 0 to clear all at the end of the
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8bit OTP Type SuLED IO Controller
// interrupt service routine.
// It may accidentally clear out the interrupts that have just occurred
// and are not yet processed.
POPAF
}
// restore ALU and FLAG register
5.11. Power-Save and Power-Down
There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down
modes. ON mode is the state of normal operation with all functions ON, Power-Save mode (“stopexe”) is the
state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is used to
save power deeply. Therefore, Power-Save mode is used in the system which needs low operating power with
wake-up occasionally and Power-Down mode is used in the system which needs power down deeply with
seldom wake-up. Table 5 shows the differences in oscillator modules between Power-Save mode (“stopexe”)
and Power-Down mode (“stopsys”).
Differences in oscillator modules between STOPSYS and STOPEXE
IHRC
Stop
ILRC
Stop
EOSC
Stop
STOPSYS
STOPEXE
No Change
No Change
No Change
Table 5: Differences in oscillator modules between STOPSYS and STOPEXE
5.11.1 Power-Save mode (“stopexe”)
Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all
the oscillator modules active. For CPU, it stops executing; however, for Timer16, counter keep counting
if its clock source is not the system clock. Wake-up from input pins can be considered as a continuation
of normal execution, the detail information for Power-Save mode shows below:
IHRC and EOSC oscillator modules: No change, keep active if it was enabled.
ILRC oscillator modules: must remain enabled, need to start with ILRC when be wakening up.
System clock: Disable, therefore, CPU stops execution.
OTP memory is turned off.
Timer counter: Stop counting if its clock source is system clock or the corresponding oscillator module is
disabled; otherwise, it keeps counting. (The Timer contains TM16, TM2, PWMG0, PWMG1, PWMG2.)
Wake-up sources:
a. IO toggle wake-up: IO toggling in digital input mode (PxC bit is 1 and PxDIER bit is 1)
b. Timer wake-up: If the clock source of Timer is not the SYSCLK, the system will be awakened when
the Timer counter reaches the set value.
c. Comparator wake-up: It need setting GPCC.7=1 and GPCS.6=1 to enable the comparator wake-up
function at the same time.
An example shows how to use Timer16 to wake-up from “stopexe”:
$ T16M
…
ILRC, /1, BIT8
// Timer16 setting
WORD
STT16
count =
count;
0;
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8bit OTP Type SuLED IO Controller
stopexe;
…
The initial counting value of Timer16 is zero and the system will be woken up after the Timer16 counts 256
ILRC clocks.
5.11.2 Power-Down mode (“stopsys”)
Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using
the “stopsys” instruction, this chip will be put on Power-Down mode directly. It is recommend to set
GPCC.7=0 to disable the comparator before the command “stopsys”. The following shows the internal
status of PMS152 detail when “stopsys” command is issued:
All the oscillator modules are turned off.
OTP memory is turned off.
The contents of SRAM and registers remain unchanged.
Wake-up sources: IO toggle in digital mode (PxDIER bit is 1)
Wake-up from input pins can be considered as a continuation of normal execution. To minimize power
consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The
reference sample program for power down is shown as below:
CLKMD
CLKMD.4
…
=
=
0xF4;
0;
//
//
Change clock from IHRC to ILRC
disable IHRC
while (1)
{
STOPSYS;
//
//
//
enter power-down
if (…) break;
if wakeup happen and check OK, then return to high speed,
else stay in power-down mode again
}
CLKMD
=
0x34;
//
Change clock from ILRC to IHRC/2
5.11.3 Wake-up
After entering the Power-Down or Power-Save modes, the PMS152 can be resumed to normal operation
by toggling IO pins. Wake-up from timer are available for Power-Save mode ONLY. Table 6 shows the
differences in wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
Yes
Timer wake-up
STOPSYS
STOPEXE
No
Yes
Yes
Table 6: Differences in wake-up sources between Power-Save mode and Power-Down mode
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When using the IO pins to wake-up the PMS152, registers pxdier should be properly set to enable the
wake-up function for every corresponding pin. The time for normal wake-up is about 3000 ILRC clocks
counting from wake-up event; fast wake-up can be selected to reduce the wake-up time by misc register,
and the time for fast wake-up is about 45 ILRC clocks from IO toggling.
Suspend mode
STOPEXE suspend
or
Wake-up mode
Wake-up time (tWUP) from IO toggle
45 * TILRC,
Where TILRC is the time period of ILRC
Fast wake-up
STOPSYS suspend
STOPEXE suspend
or
3000 * TILRC
,
Normal wake-up
Where TILRC is the clock period of ILRC
STOPSYS suspend
Table 7: Differences in wake-up time between Fast/Normal wake-up
Please notice that when Code Option is set to Fast boot-up, no matter which wake-up mode is selected in
misc.5, the wake-up mode will be forced to be FAST. If Normal boot-up is selected, the wake-up mode is
determined by misc.5.
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5.12 IO Pins
All the pins can be independently set into two states output or input by configuring the data registers (pa, pb),
control registers (pac, pbc) and pull-high resistor (paph, pbph). All these pins have Schmitt-trigger input
buffer and output driver with CMOS level. When it is set to output low, the pull-high resistor is turned off
automatically. If user wants to read the pin state, please notice that it should be set to input mode before
reading the data port; if user reads the data port when it is set to output mode, the reading data comes from
data register, NOT from IO pad. As an example, Table 8 shows the configuration table of bit 0 of port A. The
hardware diagram of IO buffer is also shown as Fig.20.
pa.0 pac.0 paph.0
Description
X
X
0
1
1
0
0
1
1
1
0
1
X
0
1
Input without pull-high resistor
Input with pull-high resistor
Output low without pull-high resistor
Output high without pull-high resistor
Output high with pull-high resistor
Table 8: PA0 Configuration Table
RD pull-high latch
WR pull-high latch
D
D
D
Q
(weak P -MOS)
pull-high
latch
Q
Q1
Data
latch
PAD
WR data latch
RD control latch
Q
WR control latch
Control
latch
M
U
X
RD Port
Data Bus
padier.x or pbdier.x
Wakeup module
Interrupt module
Analog Module
(PA0,PB5,PB0,PA4)
Fig.20: Hardware diagram of IO buffer
Other than PA5, all the IO pins have the same structure; PA5 can be open-drain ONLY when setting to output
mode (without Q1). The corresponding bits in registers padier / pbdier should be set to low to prevent leakage
current for those pins are selected to be analog function. When PMS152 is put in power-down or power-save
mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins needed to
wake-up system must be set to input mode and set the corresponding bits of registers padier and pbdier to
high. The same reason, padier.0 should be set high when PA0 is used as external interrupt pin, pbdier.0 for
PB0, padier.4 for PA4 and pbdier.5 for PB5.
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5.13 Reset and LVR
5.13.1 Reset
There are many causes to reset the PMS152, once reset is asserted, most of all the registers in PMS152
will be set to default values, system should be restarted once abnormal cases happen, or by jumping
program counter to address 0x0. The data memory is in uncertain state when reset comes from power-up
and LVR; however, the content will be kept when reset comes from PRSTB pin or WDT timeout.
5.13.2 LVR reset
By code option, there are 8 different levels of LVR for reset ~ 4.5V, 3.5V, 3.0V, 2.7V, 2.5V, 2.2V, 2.0V and
1.8V; usually, user selects LVR reset level to be in conjunction with operating frequency and supply voltage.
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6. IO Registers
6.1. ACC Status Flag Register (flag), IO address = 0x00
Bit Reset
R/W
-
Description
7 - 4
3
-
Reserved. Please do not use.
0
R/W
OV (Overflow Flag). This bit is set to be 1 whenever the sign operation is overflow.
AC (Auxiliary Carry Flag). There are two conditions to set this bit, the first one is carry out
of low nibble in addition operation and the other one is borrow from the high nibble into low
nibble in subtraction operation.
2
0
R/W
C (Carry Flag). There are two conditions to set this bit, the first one is carry out in addition
operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
1
0
0
0
R/W
R/W
Z (Zero Flag). This bit will be set when the result of arithmetic or logic operation is zero;
Otherwise, it is cleared.
6.2. Stack Pointer Register (sp), IO address = 0x02
Bit
Reset
R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer.
7 - 0
-
R/W
6.3. Clock Mode Register (clkmd), IO address = 0x03
Bit Reset
R/W
Description
System clock (CLK) selection:
Type 0, clkmd[3]=0
Type 1, clkmd[3]=1
000: IHRC÷4
001: IHRC÷2
010: reserved
011: EOSC÷4
100: EOSC÷2
101: EOSC
000: IHRC÷16
001: IHRC÷8
010: ILRC÷16 (ICE does NOT Support.)
011: IHRC÷32
7 - 5
111
R/W
100: IHRC÷64
101: EOSC÷8
110: ILRC÷4
11x: reserved
111: ILRC (default)
4
3
1
0
R/W Internal High RC Enable. 0 / 1: disable / enable
Clock Type Select. This bit is used to select the clock type in bit [7:5].
0 / 1: Type 0 / Type 1
R/W
R/W
Internal Low RC Enable. 0 / 1: disable / enable
If ILRC is disabled, watchdog timer is also disabled.
2
1
1
0
1
0
R/W Watch Dog Enable. 0 / 1: disable / enable
R/W Pin PA5/PRSTB function. 0 / 1: PA5 / PRSTB
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6.4. Interrupt Enable Register (inten), IO address = 0x04
Bit
Reset
R/W
Description
7
0
R/W
Reserved
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R/W Enable interrupt from Timer2. 0 / 1: disable / enable
R/W Enable interrupt from PWMG. 0 / 1: disable / enable
R/W
Enable interrupt from comparator. 0 / 1: disable / enable
R/W Reserved
R/W Enable interrupt from Timer16 overflow. 0 / 1: disable / enable
R/W Enable interrupt from PB0/PA4. 0 / 1: disable / enable
R/W Enable interrupt from PA0/PB5. 0 / 1: disable / enable
6.5. Interrupt Request Register (intrq), IO address = 0x05
Bit
Reset
R/W
Description
7
-
R/W Reserved
Interrupt Request from Timer2, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
6
5
-
-
R/W
R/W
R/W
Interrupt Request from PWMG, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from comparator, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
4
3
2
-
-
-
R/W Reserved
Interrupt Request from Timer16, this bit is set by hardware and cleared by software.
R/W
R/W
R/W
0 / 1: No request / Request
Interrupt Request from pin PB0/PA4, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
1
0
-
-
Interrupt Request from pin PA0/PB5, this bit is set by hardware and cleared by software.
0 / 1: No Request / request
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6.6. Timer16 mode Register (t16m), IO address = 0x06
Bit
Reset R/W
Description
Timer16 Clock source selection.
000: disable
001: CLK (system clock)
010: reserved
7 - 5
000
R/W 011: PA4 falling edge (from external pin)
100: IHRC
101: EOSC
110: ILRC
111: PA0 falling edge (from external pin)
Timer16 clock pre-divider.
00: ÷1
4 - 3
00
R/W 01: ÷4
10: ÷16
11: ÷64
Interrupt source selection. Interrupt event happens when the selected bit status is
changed.
0 : bit 8 of Timer16
1 : bit 9 of Timer16
2 : bit 10 of Timer16
R/W
2 - 0
000
3 : bit 11 of Timer16
4 : bit 12 of Timer16
5: bit 13 of Timer16
6: bit 14 of Timer16
7: bit 15 of Timer16
6.7. MISC Register (misc), IO address = 0x08
Bit
Reset R/W
Description
Reserved. (keep 0 for future compatibility)
7 - 6
-
-
Enable fast Wake up. Fast wake-up is NOT supported when EOSC is enabled.
0: Normal wake up.
5
0
WO
The wake-up time is 3000 ILRC clocks (Not for fast boot-up)
1: Fast wake up.
The wake-up time is 45 ILRC clocks.
Reserved.
4
3
-
-
-
-
Reserved.
Disable LVR function.
2
0
WO
0 / 1 : Enable / Disable
Watch dog time out period
00: 8k ILRC clock period
1 - 0
00
WO 01: 16k ILRC clock period
10: 64k ILRC clock period
11: 256k ILRC clock period
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6.8. External Oscillator setting Register (eoscr), IO address = 0x0a
Bit
Reset R/W
Description
7
0
WO Enable external crystal oscillator. 0 / 1 : Disable / Enable
External crystal oscillator selection.
00 : reserved
6 - 5
00
WO 01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
4 - 1
0
-
0
-
Reserved. Please keep 0 for future compatibility.
WO Power-down the Band-gap and LVR hardware modules. 0 / 1: normal / power-down.
6.9. Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
Reset
R/W
Description
7 - 5
-
-
Reserved.
Timer16 edge selection.
4
0
WO 0 : rising edge of the selected bit to trigger interrupt
1 : falling edge of the selected bit to trigger interrupt
PB0/PA4 edge selection.
00: both rising edge and falling edge of the selected bit to trigger interrupt
WO 01: rising edge of the selected bit to trigger interrupt
10: falling edge of the selected bit to trigger interrupt
11: reserved.
3 - 2
00
PA0/PB5 edge selection.
00: both rising edge and falling edge of the selected bit to trigger interrupt
WO 01: rising edge of the selected bit to trigger interrupt
10: falling edge of the selected bit to trigger interrupt
11: reserved.
1 - 0
00
6.10. Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset
R/W
Description
Enable PA7 digital input and wake-up event. 1 / 0: enable / disable.
7
1
WO This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA7 can NOT be used to wake-up the system.
Enable PA6 digital input and wake-up event. 1 / 0: enable / disable.
6
5
1
1
WO This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA6 can NOT be used to wake-up the system.
Enable PA5 digital input and wake-up event. 1 / 0: enable / disable.
WO
This bit can be set to low to disable wake-up from PA5 toggling.
Enable PA4 digital input, wake-up event and interrupt request. 1 / 0: enable / disable.
This bit should be set to low when PA4 is assigned as comparator input to prevent leakage
current. If this bit is set to low, PA4 can NOT be used to wake-up the system and interrupt
4
1
WO
from this pin is also disabled.
Enable PA3 digital input and wake-up event. 1 / 0: enable / disable.
WO This bit should be set to low when PA3 is assigned as comparator input to prevent leakage
current. If this bit is set to low, PA3 can NOT be used to wake-up the system.
WO Reserved
Enable PA0 digital input and wake-up event and interrupt request. 1 / 0: enable / disable.
WO This bit can be set to low to disable wake-up from PA0 toggling and interrupt request from
this pin.
3
2 - 1
0
1
11
1
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8bit OTP Type SuLED IO Controller
6.11. Port B Digital Input Enable Register (pbdier), IO address = 0x0e
Bit
Reset R/W
Description
Enable PB7~PB6 digital input and wake-up event. 1 / 0: enable / disable.
7 - 6
11
1
WO The bit should be set to low when the pad is assigned as comparator input to prevent
leakage current. If the bit is set to low, the pad can NOT be used to wake-up the system.
Enable PB5 digital input and wake-up event and interrupt request. 1 / 0: enable / disable.
This bit can be set to low to disable wake-up from PB5 toggling and interrupt request from
this pin.
5
4 - 1
0
WO
Enable PB4~PB1 digital input and wake-up event. 1 / 0: enable / disable.
1111
1
WO The bit should be set to low when the pad is assigned as comparator input to prevent
leakage current. If the bit is set to low, the pad can NOT be used to wake-up the system.
Enable PB0 digital input and wake-up event and interrupt request. 1 / 0: enable / disable.
This bit can be set to low to disable wake-up from PB0 toggling and interrupt request from
this pin.
WO
6.12. Port A Data Register (pa), IO address = 0x10
Bit
Reset R/W
0x00 R/W Data register for Port A.
Description
7 - 0
6.13. Port A Control Register (pac), IO address = 0x11
Bit
Reset R/W
Description
Port A control registers. This register is used to define input mode or output mode for each
7 - 0
0x00 R/W corresponding pin of port A. 0 / 1: input / output
Please note : PA5 is an open drain output.
6.14. Port A Pull-High Register (paph), IO address = 0x12
Bit
Reset R/W
Description
Port A pull-high register. This register is used to enable the internal pull-high device on each
R/W corresponding pin of port A and this pull high function is active only for input mode.
0 / 1 : disable / enable
7 - 0 0x00
6.15. Port B Data Register (pb), IO address = 0x14
Bit
Reset R/W
0x00 R/W Data register for Port B.
Description
7 - 0
6.16. Port B Control Register (pbc), IO address = 0x15
Bit
Reset R/W
Description
Port B control register. This register is used to define input mode or output mode for each
corresponding pin of port B. 0 / 1: input / output
7 - 0
0x00 R/W
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8bit OTP Type SuLED IO Controller
6.17. Port B Pull-High Register (pbph), IO address = 0x16
Bit
Reset R/W
Description
Port B pull-high register. This register is used to enable the internal pull-high device on each
corresponding pin of port B and this pull high function is active only for input mode.
0 / 1 : disable / enable
7 - 0
0x00 R/W
6.18. Comparator Control Register (gpcc), IO address = 0x18
Bit
Reset
R/W
Description
Enable comparator. 0 / 1 : disable / enable
7
0
R/W When this bit is set to enable, please also set the corresponding analog input pins to be
digital disable to prevent IO leakage.
Comparator result of comparator.
6
5
4
-
RO
0: plus input < minus input
1: plus input > minus input
Select whether the comparator result output will be sampled by TM2_CLK?
0
0
R/W 0: result output NOT sampled by TM2_CLK
1: result output sampled by TM2_CLK
Inverse the polarity of result output of comparator.
R/W 0: polarity is NOT inversed.
1: polarity is inversed.
Selection the minus input (-) of comparator.
000 : PA3
001 : PA4
010 : Internal 1.20 volt band-gap reference voltage
3 - 1
000
R/W
011 : Vinternal R
100 : PB6 (ICE does NOT Support.)
101 : PB7 (ICE does NOT Support.)
11X: reserved
Selection the plus input (+) of comparator.
R/W 0 : Vinternal R
0
0
1 : PA4
6.19. Comparator Selection Register (gpcs), IO address = 0x19
Bit
Reset
R/W
Description
Comparator output enable (to PA0). 0 / 1 : disable / enable
7
0
WO (Please avoid this situation: GPCS will affect the PA3 output function when selecting output
to PA0 output in ICE.)
6
5
4
0
0
0
-
Reserved
WO Selection of high range of comparator.
WO Selection of low range of comparator.
Selection the voltage level of comparator.
3 - 0
0000
WO
0000 (lowest) ~ 1111 (highest)
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8bit OTP Type SuLED IO Controller
6.20. Timer2 Control Register (tm2c), IO address = 0x1c
Bit
Reset
R/W
Description
Timer2 clock selection.
0000 : disable
0001 : CLK (system clock)
0010 : IHRC or IHRC *2 (by code option TM2_source) (ICE doesn’t support IHRC *2.)
0011 : EOSC
0100 : ILRC
0101 : comparator output
011x : reserved
7 - 4
0000
R/W 1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does
NOT be stopped, Timer2 will keep counting when ICE is in halt state.
Timer2 output selection.
00 : disable
3 - 2
00
R/W 01 : PB2
10 : PA3
11 : PB4
TM2 Mode
1
0
0
0
R/W 0: Period Mode
1: PWM Mode
Inverse the polarity of result output of TM2.
R/W
0: polarity is NOT inversed.
1: polarity is inversed.
6.21. Timer2 Scalar Register (tm2s), IO address = 0x17
Bit
Reset
R/W
Description
PWM resolution selection.
WO 0 : 8-bit
7
0
1 : 6-bit or 7-bit (by code option TM2_bit) (ICE doesn’t support 7-bit.)
Timer2 clock pre-scalar.
00 : ÷ 1
6 - 5
4 - 0
00
WO 01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
00000
WO Timer2 clock scalar.
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8bit OTP Type SuLED IO Controller
6.22. Timer2 Counter Register (tm2ct), IO address = 0x1d
Bit Reset
7 - 0 0x00
R/W
Description
R/W Bit [7:0] of Timer2 counter register.
6.23. Timer2 Bound Register (tm2b), IO address = 0x09
Bit
Reset
R/W
Description
7 - 0
0x00
WO Timer2 bound register.
6.24. PWMG0 control Register (pwmg0c), IO address = 0x20
Bit
Reset
R/W
Description
7
-
-
Reserved.
6
5
-
RO
Output status of PWMG0 generator.
0
WO Enable to inverse the polarity of PWMG0 generator output. 0 / 1: disable / enable.
PWMG0 output selection.
4
3 - 1
0
0
000
0
WO 0: PWMG0 Output
1: PWMG0 XOR PWMG1 or PWMG0 OR PWMG1 (by pwmg0c.0)
PWMG0 Output Port Selection
000: PWMG0 Output Disable
001: PWMG0 Output to PB5
R/W 010: Reserved
011: PWMG0 Output to PA0
100: PWMG0 Output to PB4
1xx: Reserved
PWMG0 output pre- selection.
R/W 0: PWMG0 XOR PWMG1
1: PWMG0 OR PWMG1
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8bit OTP Type SuLED IO Controller
6.25. PWMG Clock Register (pwmgclk), IO address = 0x21
Bit
Reset
R/W
Description
PWMG Disable/ Enable
7
0
WO 0: PWMG Disable
1: PWMG Enable
PWMG clock pre-scalar.
000: ÷1
001: ÷2
010: ÷4
011: ÷8
6 - 4
000
WO
100: ÷16
101: ÷32
110: ÷64
111: ÷128
3 - 1
0
-
-
Reserved
PWMG clock source selection
0
WO 0: System Clock
1: IHRC or IHRC*2 (by code option PWM_Source)
6.26. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22
Bit
Reset
R/W
Description
7 - 0
-
WO Bit[10:3] of PWMG0 Duty.
6.27. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23
Bit
Reset
R/W
Description
7 - 5
-
WO Bit[2:0] of PWMG0 Duty.
4 - 0
-
-
Reserved
Note: It’s necessary to write PWMG0 Duty_Value Low Register before writing PWMG0 Duty_Value High Register.
6.28. PWMG Counter Upper Bound High Register (pwmgcubh ), IO address = 0x24
Bit
Reset
R/W
Description
7 - 0
-
WO Bit[10:3] of PWMG Counter Bound.
6.29. PWMG Counter Upper Bound Low Register (pwmgcubl ), IO address = 0x25
Bit
Reset
R/W
Description
7 - 6
-
WO Bit[2:1] of PWMG Counter Bound.
5 - 0
-
-
Reserved
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8bit OTP Type SuLED IO Controller
6.30. PWMG1 control Register (pwmg1c), IO address = 0x26
Bit
Reset
R/W
Description
7
-
-
Reserved
6
5
-
RO
Output status of PWMG1 generator
0
R/W Enable to inverse the polarity of PWMG1 generator output. 0 / 1: disable / enable.
PWMG1 output selection:
0: PWMG1
1: PWMG2
4
0
R/W
PWMG1 Output Port Selection:
000: PWMG1 Output Disable
001: PWMG1 Output to PB6
3 - 1
000
R/W 010: Reserved
011: PWMG0 Output to PA4
100: PWMG0 Output to PB7
1xx: Reserved
0
-
R/W Reserved
6.31. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28
Bit
Reset
R/W
Description
7 - 0
-
WO Bit[10:3] of PWMG1 Duty
6.32. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29
Bit
Reset
R/W
Description
7 - 5
-
WO Bit[2:0] of PWMG1 Duty.
4 - 0
-
-
Reserved
Note: It’s necessary to write PWMG1 Duty_Value Low Register before writing PWMG1 Duty_Value High Register.
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8bit OTP Type SuLED IO Controller
6.33. PWMG2 control Register (pwmg2c), IO address = 0x2C
Bit
Reset
R/W
Description
7
-
-
Reserved.
6
5
-
RO
Output status of PWMG2 generator.
0
R/W Enable to inverse the polarity of PWMG2 generator output. 0 / 1: disable / enable.
PWMG2 output selection:
0: PWMG2
4
0
R/W
1: PWMG2 ÷2
PWMG2 Output Port Selection:
000: PWMG2 Output Disable
001: PWMG2 Output to PB3
010: Reserved
3 - 1
000
R/W
011: PWMG2 Output to PA3
100: PWMG2 Output to PB2
101: PWMG2 Output to PA5
1xx: Reserved
0
-
R/W Reserved
6.34. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2E
Bit
Reset
R/W
Description
7 - 0
-
WO Bit[10:3] of PWMG2 Duty
6.35. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2F
Bit
Reset
R/W
Description
7 - 5
-
WO Bit[2:0] of PWMG2 Duty
4 - 0
-
-
Reserved
Note: It’s necessary to write PWMG2 Duty_Value Low Register before writing PWMG2 Duty_Value High Register.
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8bit OTP Type SuLED IO Controller
7. Instructions
Symbol
Description
ACC
a
Accumulator (Abbreviation of accumulator)
Accumulator (symbol of accumulator in program)
sp
flag
I
Stack pointer
ACC status flag register
Immediate data
&
Logical AND
|
Logical OR
←
^
Movement
Exclusive logic OR
+
Add
－
〜
〒
OV
Z
Subtraction
NOT (logical complement, 1’s complement)
NEG (2’s complement)
Overflow (The operational result is out of range in signed 2’s complement number system)
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction in
unsigned number system)
C
Auxiliary Carry
AC
(If there is a carry out from low nibble after the result of ALU operation, this bit is set to 1)
Only addressed in 0~0x3F (0~63) is allowed
M.n
IO.n
Only addressed in 0~0x3F (0~63) is allowed
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8bit OTP Type SuLED IO Controller
7.1. Data Transfer Instructions
mov
mov
mov
mov
mov
a, I
Move immediate data into ACC.
Example: mov a, 0x0f;
Result: a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
M, a
a, M
Move data from ACC into memory
Example: mov
MEM, a;
Result: MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
a, MEM ;
Result: a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, IO
Move data from IO into ACC
Example: mov
a, pa ;
Result: a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
Move data from ACC into IO
Example: mov
Result: pb ← a
pb, a;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
ldt16 word
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
clear
clear
stt16
…
lb@ T16val ;
hb@ T16val ;
T16val ;
// clear T16val (LSB)
// clear T16val (MSB)
// initial T16 with 0
set1
…
t16m.5 ;
// enable Timer16
set0
ldt16
….
t16m.5 ;
T16val ;
// disable Timer 16
// save the T16 counting value to T16val
------------------------------------------------------------------------------------------------------------------------
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8bit OTP Type SuLED IO Controller
stt16 word
Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
mov
mov
mov
mov
stt16
…
a, 0x34 ;
lb@ T16val , a ; // move 0x34 to T16val (LSB)
a, 0x12 ;
hb@ T16val , a ; // move 0x12 to T16val (MSB)
T16val ;
// initial T16 with 0x1234
----------------------------------------------------------------------------------------------------------------------
idxm a, index Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
idxm
a, RAMIndex ; // mov memory data in address 0x5B to ACC
------------------------------------------------------------------------------------------------------------------------
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8bit OTP Type SuLED IO Controller
Idxm index, a Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
mov
idxm
a, 0xA5 ;
RAMIndex, a ;
// mov 0xA5 to memory in address 0x5B
------------------------------------------------------------------------------------------------------------------------
Exchange data between ACC and memory
xch
M
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
pushaf
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
.romadr 0x10 ;
// ISR entry address
pushaf ;
…
// put ACC and flag into stack memory
// ISR program
…
// ISR program
popaf ;
reti ;
// restore ACC and flag from stack memory
------------------------------------------------------------------------------------------------------------------------
Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
popaf
Result:
sp ← sp - 2
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
;
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8bit OTP Type SuLED IO Controller
7.2. Arithmetic Operation Instructions
add
add
add
a, I
Add immediate data with ACC, then put result into ACC
Example: add a, 0x0f ;
Result: a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
M, a
Add data in memory with ACC, then put result into ACC
Example: add
a, MEM ;
Result: a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into memory
Example: add
MEM, a;
Result: MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc a, M
addc M, a
Add data in memory with ACC and carry bit, then put result into ACC
Example: addc
a, MEM ;
Result: a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into memory
Example: addc
MEM, a ;
Result: MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc
addc
a
Add carry with ACC, then put result into ACC
Example: addc
a ;
Result: a ← a + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Add carry with memory, then put result into memory
Example: addc
MEM ;
Result: MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
nadd a, M
Add negative logic (2’s complement) of ACC with memory
Example: nadd
a, MEM ;
Result: a ← 〒a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
nadd M, a
Add negative logic (2’s complement) of memory with ACC
Example: nadd
MEM, a ;
Result: MEM ← 〒MEM + a
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sub
sub
a, I
Subtraction immediate data from ACC, then put result into ACC.
Example: sub
a, 0x0f;
Result: a ← a - 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
Subtraction data in memory from ACC, then put result into ACC
Example: sub
Result: a ← a - MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, MEM ;
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8bit OTP Type SuLED IO Controller
sub
M, a
Subtraction data in ACC from memory, then put result into memory
Example: sub MEM, a;
Result: MEM ← MEM - a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc a, M
subc M, a
Subtraction data in memory and carry from ACC, then put result into ACC
Example: subc
a, MEM;
Result: a ← a – MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction ACC and carry bit from memory, then put result into memory
Example: subc
MEM, a ;
Result: MEM ← MEM – a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc
subc
inc
a
Subtraction carry from ACC, then put result into ACC
Example: subc
a;
Result: a ← a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Subtraction carry from the content of memory, then put result into memory
Example: subc
MEM;
Result: MEM ← MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment the content of memory
Example: inc
MEM ;
Result: MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dec
M
Decrement the content of memory
Example: dec
MEM;
Result: MEM ← MEM - 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
clear
M
Clear the content of memory
Example: clear
Result: MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
MEM ;
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8bit OTP Type SuLED IO Controller
7.3. Shift Operation Instructions
sr
a
Shift right of ACC, shift 0 to bit 7
Example: sr a ;
Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of ACC with carry bit 7 to flag
src
sr
a
Example: src a ;
Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory, shift 0 to bit 7
Example: sr MEM ;
M
Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of memory with carry bit 7 to flag
src
sl
M
Example: src MEM ;
Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC shift 0 to bit 0
a
Example: sl a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC with carry bit 0 to flag
slc
sl
a
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory, shift 0 to bit 0
M
Example: sl MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry bit 0 to flag
slc
M
Example: slc MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC
swap
a
Example: swap
Result: a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
a ;
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
7.4. Logic Operation Instructions
and
and
and
or
a, I
a, M
M, a
a, I
Perform logic AND on ACC and immediate data, then put result into ACC
Example: and a, 0x0f ;
Result: a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC
Example: and
a, RAM10 ;
Result: a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory
Example: and
MEM, a ;
Result: MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and immediate data, then put result into ACC
Example: or
a, 0x0f ;
Result: a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
a, M
Perform logic OR on ACC and memory, then put result into ACC
Example: or
a, MEM ;
Result: a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
M, a
a, I
Perform logic OR on ACC and memory, then put result into memory
Example: or
MEM, a ;
Result: MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
xor
xor
Perform logic XOR on ACC and immediate data, then put result into ACC
Example: xor
a, 0x0f ;
Result: a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
Perform logic XOR on ACC and IO register, then put result into IO register
Example: xor
pa, a ;
Result: pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
xor
xor
a, M
M, a
Perform logic XOR on ACC and memory, then put result into ACC
Example: xor
a, MEM ;
Result: a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
not
a
Perform 1’s complement (logical complement) of ACC
Example: not a ;
Result: a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
not
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC7
------------------------------------------------------------------------------------------------------------------------
Perform 1’s complement (logical complement) of memory
not
M
Example: not
MEM ;
Result: MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC7
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of ACC
neg
a
Example: neg
a;
Result: a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
neg
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC8
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of memory
neg
M
Example: neg
MEM;
Result: MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC8
------------------------------------------------------------------------------------------------------------------------
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
comp
a, M
Compare ACC with the content of memory
Example: comp a, MEM;
Result: Flag will be changed by regarding as ( a - MEM )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
comp
mov
mov
mov
comp
a, 0x38 ;
mem, a ;
a, mem ;
a, 0x42 ;
mem, a ;
a, 0x38 ;
a, mem ;
// Z flag is set as 1
// C flag is set as 1
------------------------------------------------------------------------------------------------------------------------
Compare ACC with the content of memory
comp
M, a
Example: comp
MEM, a;
Result: Flag will be changed by regarding as ( MEM - a )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2020, PADAUK Technology Co. Ltd
Page 80 of 91
PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
7.5. Bit Operation Instructions
set0 IO.n
set1 IO.n
swapc IO.n
Set bit n of IO port to low
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of IO port to high
Example: set1 pb.5 ;
Result: set bit 5 of port B to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Swap the nth bit of IO port with carry bit
Example: swapc
IO.0;
Result: C ← IO.0 , IO.0 ← C
When IO.0 is a port to output pin, carry C will be sent to IO.0;
When IO.0 is a port from input pin, IO.0 will be sent to carry C;
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Application Example1 (serial output) :
------------------------------------------------------------------------------------------------------------------------
...
set1
...
pac.0 ;
// set PA.0 as output
set0
swapc
set1
swapc
...
flag.1 ;
pa.0 ;
// C=0
// move C to PA.0 (bit operation), PA.0=0
// C=1
flag.1 ;
pa.0 ;
// move C to PA.0 (bit operation), PA.0=1
------------------------------------------------------------------------------------------------------------------------
Application Example2 (serial input) :
------------------------------------------------------------------------------------------------------------------------
...
set0
...
pac.0 ;
// set PA.0 as input
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift C to bit 7 of ACC
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift new C to bit 7, old C
...
------------------------------------------------------------------------------------------------------------------------
Set bit n of memory to low
set0 M.n
Example: set0 MEM.5 ;
Result: set bit 5 of MEM to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to high
set1 M.n
Example: set1 MEM.5 ;
Result: set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
7.6. Conditional Operation Instructions
ceqsn a, I
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a – I)
Example: ceqsn
a, 0x55 ;
MEM ;
error ;
inc
goto
Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
ceqsn a, M
Example: ceqsn
a, MEM;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
cneqsn a, M
Compare ACC with memory and skip next instruction if both are not equal.
Flag will be changed like as (a ← a - M)
Example: cneqsn
a, MEM;
Result: If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
cneqsn a, I
Compare ACC with immediate data and skip next instruction if both are no equal.
Flag will be changed like as (a ← a - I)
Example: cneqsn
a,0x55 ;
MEM ;
error ;
inc
goto
Result: If a≠0x55, then “goto error”; Otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Check IO bit and skip next instruction if it’s low
t0sn IO.n
t1sn IO.n
t0sn M.n
t1sn M.n
Example: t0sn
pa.5;
Result: If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check IO bit and skip next instruction if it’s high
Example: t1sn
pa.5 ;
Result: If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s low
Example: t0sn MEM.5 ;
Result: If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high
EX: t1sn MEM.5 ;
Result: If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Increment ACC and skip next instruction if ACC is zero
izsn
a
Example: izsn
Result:
a;
a
←
a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
dzsn
izsn
a
Decrement ACC and skip next instruction if ACC is zero
Example: dzsn
Result:
a;
A
←
A - 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment memory and skip next instruction if memory is zero
Example: izsn
Result: MEM
MEM;
MEM + 1, skip next instruction if MEM= 0
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dzsn
M
Decrement memory and skip next instruction if memory is zero
Example: dzsn
Result: MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
MEM;
←
MEM - 1, skip next instruction if MEM = 0
7.7. System control Instructions
call
label
Function call, address can be full range address space
Example: call
function1;
pc + 1
Result: [sp]
←
pc
sp
←
←
function1
sp + 2
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
goto label
Go to specific address which can be full range address space
Example: goto
error;
Result: Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Place immediate data to ACC, then return
Example: ret 0x55;
ret
ret
I
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program which had function call
Example: ret;
Result:
sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
reti
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
No operation
nop
Example: nop;
Result: nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset Watchdog timer.
wdreset
Example: wdreset ;
Result: Reset Watchdog timer.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
pcadd
a
Next program counter is current program counter plus ACC.
Example: pcadd a;
Result: pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
…
mov
pcadd
goto
goto
goto
goto
…
a, 0x02 ;
a ;
// PC <- PC+2
// jump here
err1 ;
correct ;
err2 ;
err3 ;
correct:
…
// jump here
------------------------------------------------------------------------------------------------------------------------
Enable global interrupt enable
engint
Example: engint;
Result: Interrupt request can be sent to FPP0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Disable global interrupt enable
disgint
stopsys
stopexe
Example: disgint ;
Result: Interrupt request is blocked from CPU
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
System halt.
Example: stopsys;
Result: Stop the system clocks and halt the system
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
CPU halt. The oscillator module is still active to output clock, however, system clock is disabled
to save power.
Example: stopexe;
Result: Stop the system clocks and keep oscillator modules active.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset the whole chip, its operation will be same as hardware reset.
Example: reset;
reset
Result: Reset the whole chip.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
7.8. Summary of Instructions Execution Cycle
goto, call, idxm, pcadd, ret, reti
2T
2T
1T
1T
Condition is fulfilled
ceqsn, cneqsn,t0sn, t1sn, dzsn, izsn
Condition is not fulfilled
Others
©Copyright 2020, PADAUK Technology Co. Ltd
Page 84 of 91
PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
7.9. Summary of affected flags by Instructions
Instruction
mov a, I
Z
-
C
-
AC OV Instruction
Z
-
C
-
AC OV Instruction
Z
Y
-
C
-
AC OV
-
-
-
-
mov M, a
mov IO, a
idxm a, index
pushaf
-
-
-
-
mov a, M
ldt16 word
idxm index, a
popaf
-
-
-
-
mov a, IO
stt16 word
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
xch
M
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, I
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, M
addc M, a
sub a, I
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
-
add M, a
addc a, M
addc
a
addc
M
sub a, M
sub M, a
subc a, M
subc M, a
subc
dec
src
a
subc
clear
M
M
inc
sr a
src
sl
M
M
M
a
sr
M
-
Y
Y
-
-
-
-
-
-
sl
a
-
-
-
slc
a
-
-
-
M
-
-
-
slc
and
M
-
-
-
swap
and
a
-
-
-
and
a, I
Y
Y
Y
Y
Y
-
-
-
a, M
Y
Y
-
-
-
M, a
Y
Y
Y
Y
-
-
-
-
or a, I
-
-
-
or a, M
-
-
-
or M, a
-
-
-
xor
xor
neg
a, I
-
-
-
xor
not
neg
IO, a
-
-
-
xor
not
a, M
-
-
-
M, a
a
-
-
-
a
Y
Y
-
-
-
-
M
-
-
-
-
-
-
M
-
-
-
set0 IO.n
set1 M.n
t0sn IO.n
t1sn M.n
-
-
-
set1 IO.n
ceqsn a, I
t1sn IO.n
-
-
-
set0 M.n
ceqsn a, M
t0sn M.n
-
-
-
-
-
-
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
-
-
-
-
-
-
-
-
izsn
dzsn
ret
a
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
dzsn
call
a
Y
-
Y
-
Y
-
Y
-
izsn
M
Y
-
Y
-
Y
-
Y
-
M
label
goto label
reti
I
ret
-
-
-
-
-
-
-
-
nop
-
-
-
-
pcadd
a
-
-
-
-
engint
-
-
-
-
disgint
reset
-
-
-
-
stopsys
wdreset
-
-
-
-
-
-
-
-
stopexe
-
-
-
-
-
-
-
-
nadd M, a
cneqsn a, I
nadd a, M
Y
Y
Y
Y
Y
Y
Y
Y
cneqsn a, M
comp a, M
swapc IO.n
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
-
Y
-
Y
Y
Y
Y
comp
M, a
7.10.BIT definition
Bit access of RAM is only available for address from 0x00 to 0x3F.
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
8. Code Options
Option
Selection
Enable
Disable
4.0V
Description
OTP content is protected and program cannot be read back
OTP content is not protected so program can be read back
Select LVR = 4.0V
Security
3.5V
Select LVR = 3.5V
3.0V
Select LVR = 3.0V
2.7V
Select LVR = 2.7V
LVR
2.5V
Select LVR = 2.5V
2.2V
Select LVR = 2.2V
2.0V
Select LVR = 2.0V
1.8V
Select LVR = 1.8V
Slow
Please refer to tWUP and tSBP in Section 4.1
Please refer to tWUP and tSBP in Section 4.1
INTEN/INTRQ.Bit0 is from PA.0
INTEN/INTRQ.Bit0 is from PB.5
INTEN/INTRQ.Bit1 is from PB.0
INTEN/INTRQ.Bit1 is from PA.4
Comparator does not control all PWM outputs
Comparator controls all PWM outputs
(ICE does NOT Support.)
Boot-up_Time
Interrupt Src0
Interrupt Src1
Fast
PA.0
PB.5
PB.0
PA.4
Disable
GPC_PWM
Enable
16MHZ
32MHZ
When Pwmgclk.0= 1, PWMG clock source = IHRC = 16MHZ
PWM_Source
When Pwmgclk.0= 1, PWMG clock source = IHRC*2 = 32MHZ
(ICE does NOT Support.)
16MHZ
When tm2c[7:4]= 0010, TM2 clock source = IHRC = 16MHZ
TM2_Source
TM2_Bit
When tm2c[7:4]= 0010, TM2 clock source = IHRC*2 = 32MHZ
(ICE does NOT Support.)
32MHZ
6 Bit
When tm2s.7=1, TM2 PWM resolution is 6 Bit
When tm2s.7=1, TM2 PWM resolution is 7 Bit
(ICE does NOT Support.)
7 Bit
All_Edge
The comparator will trigger an interrupt on the rising edge or falling edge
Comparator_Edge Rising_Edge The comparator will trigger an interrupt on the rising edge
Falling_Edge The comparator will trigger an interrupt on the falling edge
©Copyright 2020, PADAUK Technology Co. Ltd
Page 86 of 91
PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
9. Special Notes
This chapter is to remind user who use PMS152 series IC in order to avoid frequent errors upon operation.
9.1. Warning
User must read all application notes of the IC by detail before using it. Please download the related application
notes from the following link:
http://www.padauk.com.tw/tw/technical/index.aspx
9.2. Using IC
9.2.1. IO pin usage and setting
(1) IO pin is set to be digital input
When IO is set as digital input, the level of Vih and Vil would changes with the voltage and temperature.
Please follow the minimum value of Vih and the maximum value of Vil.
The value of internal pull high resistor would also changes with the voltage, temperature and pin voltage.
It is not the fixed value.
(2) IO pin as digital input and enable wakeup function
Configure IO pin as input
Set corresponding bit to “1” in PXDIER
For those IO pins of PA that are not used, PADIER[1:2] should be set low in order to prevent them from
leakage.
(3) PA5 is set to be output pin
PA5 can be set to be Open-Drain output pin only, output high requires adding pull-high resistor.
(4) PA5 is set to be PRSTB input pin
Configure PA5 as input
Set CLKMD.0=1 to enable PA5 as PRSTB input pin
(5) PA5 is set to be input pin and to connect with a push button or a switch by a long wire
Needs to put a >33Ω resistor in between PA5 and the long wire
Avoid using PA5 as input in such application.
(6) PA7 and PA6 as external crystal oscillator
Configure PA7 and PA6 as input
Disable PA7 and PA6 internal pull-high resistor
Configure PADIER register to set PA6 and PA7 as analog input
EOSCR register bit [6:5] selects corresponding crystal oscillator frequency :
01 : for lower frequency, ex : 32KHz
10 : for middle frequency, ex : 455KHz, 1MHz
11 : for higher frequency, ex : 4MHz
Program EOSCR.7 =1 to enable crystal oscillator
Ensure EOSC working well before switching from IHRC or ILRC to EOSC.
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Page 87 of 91
PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
Note: Please read the PMC-APN013 carefully. According to PMC-APN013, the crystal oscillator should be
used reasonably. If the following situations happen to cause IC start-up slowly or non-startup, PADAUK
Technology is not responsible for this: the quality of the user's crystal oscillator is not good, the usage
conditions are unreasonable, the PCB cleaner leakage current, or the PCB layouts are unreasonable.
9.2.2. Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit
Step2: Clear INTRQ register
Step3: In the main program, using ENGINT to enable CPU interrupt function
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine
Step5: After the Interrupt Service Routine being executed, return to the main program
*Use DISGINT in the main program to disable all interrupts
*When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG register.
POPAF instruction is to restore ALU and FLAG register before RETI as below:
void Interrupt (void)
// Once the interrupt occurs, jump to interrupt service routine
// enter DISGINT status automatically, no more interrupt is
{
accepted
PUSHAF;
…
POPAF;
}
// RETI will be added automatically. After RETI being executed, ENGINT status
will be restored
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function.
9.2.3. System clock switching
System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock and
turn off the original clock source at the same time. For example: When switching from clock A to clock B,
please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Example : Switch system clock from ILRC to IHRC/2
CLKMD
=
0x36;
0;
// switch to IHRC, ILRC can not be disabled here
CLKMD.2 =
// ILRC can be disabled at this time
ERROR: Switch ILRC to IHRC and turn off ILRC simultaneously
CLKMD 0x50; // MCU will hang
=
9.2.4. Watchdog
Watchdog will be inactive once ILRC is disabled.
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
9.2.5. TIMER time out
When select $ INTEGS BIT_R (default value) and T16M counter BIT8 to generate interrupt, if T16M counts
from 0, the first interrupt will occur when the counter reaches to 0x100 (BIT8 from 0 to 1) and the second
interrupt will occur when the counter reaches 0x300 (BIT8 from 0 to 1). Therefore, selecting BIT8 as 1 to
generate interrupt means that the interrupt occurs every 512 counts. Please notice that if T16M counter is
restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
If select $ INTEGS BIT_F(BIT triggers from 1 to 0) and T16M counter BIT8 to generate interrupt, the T16M
counter changes to an interrupt every 0x200/0x400/0x600/. Please pay attention to two differences with
setting INTEGS methods.
9.2.6. IHRC
(1)
The IHRC frequency calibration is performed when IC is programmed by the writer.
Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the
IHRC frequency (either for package or COB), if the calibration is done before molding process, the
actual IHRC frequency after molding may be deviated or becomes out of spec. Normally , the
frequency is getting slower a bit.
(2)
(3)
(4)
It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not
take any responsibility for this situation.
Users can make some compensatory adjustments according to their own experiences. For example,
users can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
9.2.7. LVR
User can set MISC.2 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest working
voltage of chip; Otherwise IC may work abnormally.
9.2.8. Programming Writing
There are 6 pins for using the writer to program: PA3, PA4, PA5, PA6, VDD and GND.
If use PDK3S-P-002 to program PMS152 real chip, just use the CN39 jumper (at the back for the writer) with
putting the 16pin package IC on the top of the Textool. For the 14pin package, it need downward one space
on the Textool, for the 10pin package, it need downward three spaces on the Textool, and for the 8pin
package, it need downward four spaces on the Textool.
Other packages could be programmed by connecting the signals correspondingly. All the signals of the left
side of the jumpers are the same and as the descriptions at the left bottom corner. They are VDD, PA0(not
used), PA3, PA4, PA5, PA6, PA7(not used), and GND).
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
If user use PDK5S-P-003 or above to program, please follow the instructions for connecting jumpers.
Special notes about voltage and current while Multi-Chip-Package(MCP) or On-Board Programming
(1) PA5 (VPP) may be higher than 11V.
(2)
VDD may be higher than 6.5V, and its maximum current may reach about 20mA.
(3) All other signal pins level (except GND) are the same as VDD.
User should confirm when using this product in MCP or On-Board Programming, the peripheral components
or circuit will not be damaged by the above voltages, and will not clam the above voltages.
Important Cautions：
You MUST follow the instructions on APN004 and APN011 for programming IC on the handler.
Connecting a 0.01uF capacitor between VDD and GND at the handler port to the IC is always
good for suppressing disturbance. But please DO NOT connect with ＞0.01uF capacitor,
otherwise, programming may be fail.
©Copyright 2020, PADAUK Technology Co. Ltd
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PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
PMS152
8bit OTP Type SuLED IO Controller
9.3. Using ICE
PDK5S-I-S01/2 (B) supports PMS152 1-FPPA MCU emulation work, the following items should be noted when
using PDK5S-I-S01/2(B) to emulate PMS152:
PDK5S-I-S01/2(B) doesn’t support the function of the set of 11-bit SuLED hardware PWM generators.
PDK5S-I-S01/2(B) doesn’t support the instruction NADD/COMP of PMS152.
PDK5S-I-S01/2 (B) doesn’t support SYSCLK=ILRC/16 of PMS152.
PDK5S-I-S01/2 (B) doesn’t support the function Tm2.gpcrs of PMS152.
The PA3 output function will be affected when GPCS selects output to PA0 output.
When simulating PWM waveform, please check the waveform during program running. When the ICE is
suspended or single-step running, its waveform may be inconsistent with the reality.
The ILRC frequency of the PDK5S-I-S01/2(B) simulator is different from the actual IC and is
uncalibrated, with a frequency range of about 34K~38KHz.
Fast Wakeup time is different from PDK5S-I-S01/2(B): 128 SysClk, PMS152: 45 ILRC.
Watch dog time out period is different from PDK5S-I-S01/2:
WDT period
misc[1:0]=00
misc[1:0]=01
misc[1:0]=10
misc[1:0]=11
PDK5S-I-S01/2(B)
2048 * TILRC
PMS152
8192 * TILRC
16384 * TILRC
65536 * TILRC
262144 * TILRC
4096 * TILRC
16384 * TILRC
256 * TILRC
©Copyright 2020, PADAUK Technology Co. Ltd
Page 91 of 91
PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
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