PMS234-S24 [PADAUK]
12-bit ADC Enhanced;型号: | PMS234-S24 |
厂家: | PADAUK Technology |
描述: | 12-bit ADC Enhanced |
文件: | 总107页 (文件大小:1712K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PMC234/PMS234 Series
12-bit ADC Enhanced
Field Programmable Processor Array
(FPPATM) 8-bit OTP Controller
Data Sheet
Version 1.03 – Dec. 19, 2018
Copyright 2018 by PADAUK Technology Co., Ltd., all rights reserved
6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.
TEL: 886-3-572-8688 www.padauk.com.tw
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those which may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’
products, customers should design a product with adequate operating safeguards.
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Table of Contents
1.Features..............................................................................................................................9
1-1. Special Features....................................................................................................................9
1-2. System Functions ..................................................................................................................9
1-3. High Performance RISC CPU Array.......................................................................................9
1-4. Package Information............................................................................................................10
2. General Description and Block Diagram ......................................................................11
3. Pin Assignment and Description...................................................................................12
4. Device Characteristics ...................................................................................................17
4-1. AC/DC Device Characteristics .............................................................................................17
4-2. Absolute Maximum Ratings .................................................................................................19
4-3. Typical ILRC frequency vs. VDD and temperature...............................................................20
4-4. Typical IHRC frequency deviation vs. VDD and temperature (calibrated to 16MHz).............21
4-5. Typical operating current vs. VDD @ system clock = ILRC/n...............................................22
4-6. Typical operating current vs. VDD @ system clock = IHRC/n ..............................................22
4-7. Typical operating current vs. VDD @ system clock = 1MHz EOSC / n.................................23
4-8. Typical operating current vs. VDD @ system clock = 4MHz EOSC / n.................................23
4-9. Typical operating current vs. VDD @ system clock = 32KHz EOSC / n ...............................24
4-10. Typical IO driving current (IOH) and sink current (IOL)..........................................................24
4-11. Typical IO input high/low threshold voltage (VIH/VIL)...........................................................25
4-12. Typical resistance of IO pull high device ............................................................................25
4-13. Typical VDD/2 Bias output voltage.....................................................................................26
4-14. Typical power down current (IPD) and power save current (IPS)...........................................26
4-15. Timing charts for boot up conditions ..................................................................................27
4-15. Typical Comparator Responsive Time (Use V internal R) ........................................................28
4-16. Typical Comparator Responsive Time (Use External Inputs) .............................................29
5. Functional Description...................................................................................................30
5-1. Processing Units..................................................................................................................30
5-1-1. Program Counter .....................................................................................................31
5-1-2. Stack Pointer............................................................................................................31
5-1-3. Single FPP mode.....................................................................................................32
5-2. Program Memory -- OTP......................................................................................................33
5-2-1. Program Memory Assignment..................................................................................33
5-2-2. Example of Using Program Memory for Two FPP mode ..........................................34
5-2-3. Example of Using Program Memory for Single FPP mode.......................................34
©Copyright 2018, PADAUK Technology Co. Ltd
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PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-3. Program Structure ...............................................................................................................35
5-3-1. Program structure of two FPP units mode................................................................35
5-3-2. Program structure of single FPP mode.....................................................................35
5-4. Boot Procedure....................................................................................................................36
5-5. Data Memory -- SRAM.........................................................................................................37
5-6. Arithmetic and Logic Unit.....................................................................................................37
5-7. Oscillator and clock..............................................................................................................38
5-7-1. Internal High RC oscillator and Internal Low RC oscillator........................................38
5-7-2. Chip calibration ........................................................................................................38
5-7-3. IHRC Frequency Calibration and System Clock.......................................................38
5-7-4. External Crystal Oscillator........................................................................................40
5-7-5. System Clock and LVR level....................................................................................41
5-7-6. System Clock Switching...........................................................................................42
5-8. 16-bit Timer (Timer16) .........................................................................................................43
5-9. 8-bit Timer (Timer2) with PWM generation...........................................................................45
5-9-1. Using the Timer2 to generate periodical waveform ..................................................46
5-9-2. Using the Timer2 to generate 8-bit PWM waveform .................................................48
5-9-3. Using the Timer2 to generate 6-bit PWM waveform .................................................49
5-10. WatchDog Timer................................................................................................................50
5-11. Interrupt .............................................................................................................................51
5-12. Power-Save and Power-Down ...........................................................................................53
5-12-1. Power-Save mode (“stopexe”) ...............................................................................53
5-12-2. Power-Down mode (“stopsys”)...............................................................................54
5-12-3. Wake-up ................................................................................................................55
5-13. IO Pins...............................................................................................................................56
5-14. Reset and LVR ..................................................................................................................57
5-14-1. Reset .....................................................................................................................57
5-14-2. LVR (low voltage reset)..........................................................................................57
5-15. Comparator........................................................................................................................58
5-15-1. Comparator Hardware Diagram .............................................................................58
5-15-2. Analog Inputs.........................................................................................................59
5-15-3. Internal reference voltage (Vinternal R) .......................................................................60
5-15-4. Comparator Interrupt Operation .............................................................................62
5-15-5. Synchronizing Comparator Output to Timer2 .........................................................62
5-15-6. Comparator Response Time ..................................................................................62
5-15-7. Using the comparator.............................................................................................63
5-15-8. Using the comparator and band-gap 1.20V............................................................64
5-16. LCD Bias Voltage Generator..............................................................................................65
5-17. Analog-to-Digital Conversion (ADC) module......................................................................66
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-17-1. The input requirement for AD conversion...............................................................67
5-17-2. Select the ADC bit resolution .................................................................................68
5-17-3. ADC clock selection ...............................................................................................68
5-17-4. AD conversion........................................................................................................68
5-17-5. Configure the analog pins ......................................................................................68
5-17-6. Using the ADC .......................................................................................................69
6. IO Registers ....................................................................................................................70
6-1. ACC Status Flag Register (flag), IO address = 0x00............................................................70
6-2. FPP unit Enable Register (fppen), IO address = 0x01..........................................................70
6-3. Stack Pointer Register (sp), IO address = 0x02 ...................................................................70
6-4. Clock Mode Register (clkmd), IO address = 0x03 ................................................................70
6-5. Interrupt Enable Register (inten), IO address = 0x04 ...........................................................71
6-6. Interrupt Request Register (intrq), IO address = 0x05..........................................................71
6-7. Timer16 mode Register (t16m), IO address = 0x06 .............................................................72
6-8. General Data register for IO (gdio), IO address = 0x07........................................................72
6-9. External Oscillator setting Register (eoscr), IO address = 0x0a ...........................................72
6-10. Internal High RC oscillator control Register (ihrcr), IO address = 0x0b...............................73
6-11. Interrupt Edge Select Register (integs), IO address = 0x0c................................................73
6-12. Port A Digital Input Enable Register (padier), IO address = 0x0d.......................................74
6-13. Port B Digital Input Enable Register (pbdier), IO address = 0x0e.......................................74
6-14. Port A Data Register (pa), IO address = 0x10....................................................................74
6-15. Port A Control Register (pac), IO address = 0x11 ..............................................................75
6-16. Port A Pull-up Register (paph), IO address = 0x12 ............................................................75
6-17. Port B Data Register (pb), IO address = 0x14....................................................................75
6-18. Port B Control Register (pbc), IO address = 0x15 ..............................................................75
6-19. Port B Pull-up Register (pbph), IO address = 0x16 ............................................................75
6-20. Port C Data Register (pc), IO address = 0x17....................................................................75
6-21. Port C Control Register (pcc), IO address = 0x18 ..............................................................75
6-22. Port C Pull-up Register (pcph), IO address = 0x19 ............................................................75
6-23. Port D Data Register (pd), IO address = 0x1a....................................................................76
6-24. Port D Control Register (pdc), IO address = 0x1b..............................................................76
6-25. Port D Pull-up Register (pdph), IO address = 0x1c ............................................................76
6-26. ADC Control Register (adcc), IO address = 0x20...............................................................76
6-27. ADC Mode Register (adcm), IO address = 0x21 ................................................................77
6-28. ADC Result High Register (adcrh), IO address = 0x22.......................................................77
6-29. ADC Result Low Register (adcrl), IO address = 0x23 ........................................................77
6-30. Miscellaneous Register (misc), IO address = 0x3b ............................................................78
6-31. Timer2 Control Register (tm2c), IO address = 0x3c ...........................................................79
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
6-32. Timer2 Counter Register (tm2ct), IO address = 0x3d.........................................................79
6-33. Timer2 Scalar Register (tm2s), IO address = 0x37 ............................................................79
6-34. Timer2 Bound Register (tm2b), IO address = 0x09............................................................80
6-35. Comparator Control Register (gpcc), IO address = 0x3e....................................................80
6-36. Comparator Selection Register (gpcs), IO address = 0x22 ................................................80
7. Instructions.....................................................................................................................81
7-1. Data Transfer Instructions....................................................................................................81
7-2. Arithmetic Operation Instructions.........................................................................................85
7-3. Shift Operation Instructions..................................................................................................88
7-4. Logic Operation Instructions ................................................................................................89
7-5. Bit Operation Instructions.....................................................................................................92
7-6. Conditional Operation Instructions .......................................................................................93
7-7. System control Instructions..................................................................................................95
7-8. Summary of Instructions Execution Cycle............................................................................97
7-9. Summary of affected flags by Instructions............................................................................98
8. Code Options..................................................................................................................99
9. Special Notes................................................................................................................100
9-1. Warning ...........................................................................................................................100
9-2. Using IC...........................................................................................................................100
9-2-1. IO pin usage and setting.......................................................................................100
9-2-2. Interrupt................................................................................................................101
9-2-3. System clock switching.........................................................................................102
9-2-4. Power down mode, wakeup and watchdog...........................................................103
9-2-5. TIMER time out.....................................................................................................103
9-2-6. Using ADC............................................................................................................103
9-2-7. LVR ......................................................................................................................104
9-2-8. IHRC ....................................................................................................................104
9-2-9. Program writing ....................................................................................................104
9-3. Using ICE.........................................................................................................................106
9-3-1. Emulating PMC234/PMS234 series IC on ICE PDK3S-I-001/002/003 ...................106
9-3-2. Important Notice for ICE operation.........................................................................107
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Revision History:
Revision
Date
2015/08/01 1st version
1. Add 1-4. Package Information: PMC234-Y24
2. Add 3. PMC234-Y24 Pin Assignment and Description
Description
0.01
0.02
2015/10/30
1. Updated company address & Tel No.
2. Amend 1-1, 1-2, 1-3
3. Add AVDD and AGND in Chapter 3
4. Amend 4-1 AC/DC Device Characteristics
5. Amend 4-3 to 4-13
6. Add 4-14 Typical power down current (IPD) and power save current (IPS)
7. Amend 5-7 Oscillator and clock
8. Amend 5-7-1, 5-7-4, 5-7-5
9. Amend 5-9, 5-9-1, 5-9-2
10. Amend 5-11 Interrupt
11. Amend 5-12-1, 5-12-2, 5-12-3
12. Amend 5-14-1, 5-14-2
1.03
2018/12/19
13. Amend 5-15-1, 5-15-7, 5-15-8
14. Amend Fig. 16: Hardware diagram of comparator
15. Amend Table 7: Differences in wake-up sources between Power-Save mode
and Power-Down mode
16. Amend Fig.25: Analog Input Model
17. Amend 6-7, 6-12, 6-13
18. Amend 7.8 Summary of Instructions Execution Cycle and delete 8.1.8
19. Add Chapter 8 Special Notes
20. Add 9-1 Warning
21. Amend 9-2-1, 9-2-5, 9-2-9
22. Add 9-2-8 IHRC
23. Amend 9-3 Using ICE
©Copyright 2018, PADAUK Technology Co. Ltd
Page 7 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Major Differences between P234C and PMC234/PMS234
There are many differences between P234C and PMC234/PMS234. The table below only shows the major
differences between them.
Item Function
P234C
PMC234/PMS234
26 IO pins
22 IO pins
1
IO Pin
PA[7:0], PB[7:0], PC[5:0]
12mA@5.0V
PA[7:0], PB[7:0], PC[7:0], PD[1:0]
10mA@5.0V
2
3
4
5
6
IO capability
SRAM
200 bytes
208 bytes
Band-gap
LVR
+/- 200mV(@1.20V)
4 levels LVR setting
N/A
+/- 60mV(@1.20V) after calibration
8 levels LVR setting
Yes
Single FPPA mode
ADC reference high
voltage
7
8
9
VDD and PB1
VDD
ADC resolution
8bit to 12bit selectable
padidr , pbdidr, pcdidr
Only 12bit available.
padier , pbdier
Port digital/analog input
configure registers
IHRC option command
WDT time out
10
11
.ADJUST_OTP_IHRCR
512 ILRC clock cycles
.ADJUST_IC
4 selectable periods
Procedure for converting code from P234C to PMC234/PMS234
Please follow the below steps for converting code from P234C to PMC234/PMS234:
1.
2.
Go through the PMC234/PMS234 datasheet and user guide;
Modify the source code engineering file “.pre”; change “.chip P234CXXX” to “.chip PMC234” or “.chip
PMS234”
3.
4.
5.
6.
7.
8.
Press “Build” and then IDE will show some errors and warnings.
Modify the source code correspondingly until all errors have been solved.
Save and build the project files again.
Write to a real chip and test its functions in detail.
Back to the step 3 if necessary.
Contact our FAE at fae@padauk.com.tw if you still have any problems.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 8 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
1. Features
1-1. Special Features
PMC234 series:
High EFT series
Operating temperature range: -40°C ~ 85°C
PMS234 series:
General purpose series
Not supposed to use in AC RC step-down powered or high EFT requirement applications.
PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.
Operating temperature range: -20°C ~ 70°C
1-2. System Functions
4Kx16 bits OTP program memory for both FPP units
208 Bytes data RAM for both FPP units
One hardware 16-bit timer
Provide one hardware comparator
Support fast wake-up
26 IO pins with 10mA driving / sink capability
Every IO pin can be configured to enable wake-up function
Band-gap circuit to provide 1.20V reference voltage
Up to 11-channel 12-bit resolution ADC with 1-channel for internal band-gap reference voltage
One hardware 8-bit timer with PWM generator
Provide software configurable LCD driver IO with optional VDD/2 LCD bias voltage
Provide maximum 4x21 dots LCD display
Operating voltage range: 2.2V ~ 5.5V
Clock sources: internal high RC oscillator, internal low RC oscillator and external crystal oscillator
Eight levels of LVR ~ 4.1V, 3.6V, 3.1V, 2.8V, 2.5V, 2.2V, 2.0V, 1.8V
Two external interrupt pins
1-3. High Performance RISC CPU Array
Operating modes: Two processing units FPPATM mode or Traditional one processing unit mode
100 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer to provide adjustable stack level
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer
of Indirect addressing mode
IO space and memory space are independent
©Copyright 2018, PADAUK Technology Co. Ltd
Page 9 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
1-4. Package Information
PMC234 series
PMC234 - Y24: SSOP24 (150mil);
PMC234 - S20: SOP20 (300mil);
PMC234 - S24: SOP24 (300mil);
PMC234 - S28: SOP28 (300mil);
PMC234 - D20: DIP20 (300mil);
PMC234 - K24: Skinny DIP24 (300mil);
PMC234 - K28: Skinny DIP28 (300mil)
PMS234 series
PMS234 - S20: SOP20 (300mil);
PMS234 - S24: SOP24 (300mil);
PMS234 - S28: SOP28 (300mil);
PMS234 - D20: DIP20 (300mil);
PMS234 - K24: Skinny DIP24 (300mil);
PMS234 - K28: Skinny DIP28 (300mil)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 10 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
2. General Description and Block Diagram
The PMC234/PMS234 series is an ADC-Type of PADAUK’s parallel processing, fully static, OTP-based
CMOS 2x8 bit processor array that can execute two peripheral functions in parallel. It employs RISC
architecture based on patent pending FPPA™ (Field Programmable Processor Array) technology and all the
instructions are executed in one cycle except that some instructions are two cycles that handle indirect
memory access.
4Kx16 bits OTP program memory and 208 bytes data SRAM are inside for two FPP units using, one up to 11
channels 12-bit ADC is built inside the chip with one channel for internal band-gap reference voltage; one
comparator is also provided. PMC234/PMS234 also provides two hardware timers: one is 16-bit timer and the
other one is 8-bit with PWM generation.
Comparator
4KW OTP
&
Task
Interrupt
Control
Controller
16-bit Timer
IO Ports
PWM
Function
FPP0
FPP1
208 bytes
SRAM
I2C
Function
SPI
12-bit ADC
&
Function
Bandgap
UART
Function
8-bit
Timer / PWM
Key Scan
Function
POR / LVD
LCD
Function
Watchdog
Timer
Power
management
©Copyright 2018, PADAUK Technology Co. Ltd
Page 11 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
3. Pin Assignment and Description
PMC234 series
PMC234-Y24 (SSOP24-150mil)
PMC234-S24 (SOP24-300mil)
PMC234-K24 (Skinny DIP24-300mil)
PMC234-S28 (SOP28-300mil)
PMC234-K28 (Skinny DIP28-300mil)
PMC234-S20 (SOP20-300mil)
PMC234-D20 (DIP20-300mil)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 12 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
PMS234 series
PMS234-S24 (SOP24-300mil)
PMS234-S28 (SOP28-300mil)
PMS234-K24 (Skinny DIP24-300mil)
PMS234-K28 (Skinny DIP28-300mil)
PMS234-S20 (SOP20-300mil)
PMS234-D20 (DIP20-300mil)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 13 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Pin Description
Pin Type &
Pin Name
Description
Buffer Type
The functions of this pin can be:
(1) Bit 7 of port A, It can be configured as digital input or two-state output, with pull-
up resistor by software independently
IO
PA7 /
X1
ST /
(2) X1 when crystal oscillator is used.
CMOS
If this pin is used for crystal oscillator, bit 7 of padier register must be programmed
“0” to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function is also disabled if bit 7 of padier register is “0”.
The functions of this pin can be:
(1) Bit 6 of port A. It can be configured as digital input or and two-state output, with
pull-up resistor by software independently
IO
PA6 /
X2
ST /
(2) X2 when crystal oscillator is used.
CMOS
If this pin is used for crystal oscillator, bit 6 of padier register must be programmed
“0” to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function is also disabled if bit 6 of padier register is “0”.
The functions of this pin can be:
(1) Bit 5 of port A. It can be configured as digital input or open-drain output pin.
Please notice that there is no pull-up resistor in this pin.
IO (OC)
ST /
PA5 /
(2) Hardware reset.
RESET#
This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”. Please put 33Ω resistor in
series to have high noise immunity when this pin is in input mode. Please set it
output low or input with external pull-up when not used to prevent leakage current
CMOS
The functions of this pin can be:
(1) Bit 4 of port A. It can be configured as digital input or two-state output, with pull-
up resistor by software independently
IO
PA4 /
AD9 /
CIN2-
(2) Channel 9 of ADC analog input
ST /
(3) Minus input source of comparator.
CMOS /
Analog
When this pin is configured as analog input, please use bit 4 of register padier to
disable the digital input to prevent current leakage. The bit 4 of padier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 3 of port A. It can be configured as digital input or two-state output, with pull-
up resistor independently by software
PA3 /
AD8 /
(2) Channel 8 of ADC analog input
IO
(3) Minus input source of comparator
ST /
PWM /
COM3 /
CIN1-
(4) PWM output from Timer2
CMOS /
Analog
(5) COM3 for LCD. It can provide VDD/2 LCD bias voltage.
When this pin is configured as analog input, please use bit 3 of register padier to
disable the digital input to prevent current leakage. The bit 3 of padier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 14 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 2 of port A. It can be configured as digital input or two-state output, with pull-up
resistor independently by software
PA2 /
PWM /
COM2
IO
ST /
(2) PWM output from Timer2
CMOS
(3) COM2 for LCD. It can provide VDD/2 LCD bias voltage.
The bit 2 of padier register can be set to “0” to disable wake-up from power-down by
toggling this pin.
The functions of this pin can be:
(1) Bit 1 of port A. It can be configured as digital input or two-state output, with pull-up
resistor independently by software
PA1 /
PWM /
COM1
IO
ST /
(2) PWM output from Timer2
CMOS
(3) COM1 for LCD. It can provide VDD/2 LCD bias voltage.
The bit 1 of padier register can be set to “0” to disable wake-up from power-down by
toggling this pin.
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as digital input or two-state output, with pull-up
resistor independently by software
PA0 /
INT0 /
COM0
IO
(2) External interrupt line 0. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
ST /
CMOS
(3) COM0 for LCD. This pin is also the COM0 from LCD bias voltage generator.
The bit 0 of padier register can be set to “0” to disable wake-up from power-down by
toggling this pin.
PB7 / AD7
PB6 / AD6
PB5 / AD5
PB4 / AD4
PB3 / AD3
PB2 / AD2
The functions of these pins can be:
(1) Bit 7~1 of port B. These seven pins can each be configured as analog input,
digital input, and two-state output mode with pull-up resistor independently by
software.
IO
ST /
CMOS /
Analog
(2) Channel 7~1 of ADC analog input.
When any of these seven pins acts as analog inputs, please use register pbdier to
disable the digital input to prevent current leakage. If the control bit in pbdier register
is set to “0” to disable digital input, wake-up from power-down by toggling the
corresponding pin is also disabled.
PB1 / AD1
The functions of this pin can be:
(1) Bit 0 of port B. It can be configured as analog input, digital input, and two-state
output mode with pull-up resistor independently by software.
(2) Channel 0 of ADC analog input. When this pin acts as analog input, please use bit
0 of register pbdier to disable the digital input to prevent current leakage.
(3) External interrupt line 1. Both rising edge and falling edge are accepted to request
interrupt service and configurable by register setting.
PB0 /
AD0 /
INT1 /
CO
IO
ST /
CMOS /
Analog
(4) Comparator output.
If bit 0 of pbdier register is set to “0” to disable digital input, wake-up from power-down
by toggling this pin is also disabled.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 15 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Pin Type &
Buffer Type
Pin Name
Description
IO
The functions of this pin can be:
PC5 /
CIN+/
CIN4-
ST /
(1) Bit 5 of port C. It can be configured as analog input, digital input, and two-state
output mode with pull-up resistor independently by software.
(2) Plus or minus input source of comparator.
CMOS /
Analog
PC7
PC6
PC4
PC3
PC2
PC1
Bit 7, 6, 4, 3, 2, 1 of port C. These pins can be configured as digital input mode and
two-state output mode with pull-up resistor independently by software.
IO
ST /
CMOS
IO
The functions of this pin can be:
PC0 /
CIN3-
ST /
(1) Bit 0 of port C. It can be configured as analog input, digital input, and two-state
output mode with pull-up resistor independently by software.
(2) Minus input source of comparator.
CMOS /
Analog
IO
PD1
PD0
Bit 1, 0 of port D. These pins can be configured as digital input mode and two-state
output mode with pull-up resistor independently by software.
ST /
CMOS
VDD: Digital positive power
VDD /
AVDD
VDD /
AVDD
AVDD: Analog positive power
VDD is the IC power supply while AVDD is the ADC power supply. AVDD and VDD
are double bonding internally and they have the same external pin.
GND: Digital negative power
GND /
AGND
GND /
AGND
AGND: Analog negative power
GND is the IC ground pin while AGND is the ADC ground pin. AGND and GND are
double bonding internally and they have the same external pin.
Notes: IO: Input/Output; ST: Schmitt Trigger input; OC: Open Collector; Analog: Analog input pin;
CMOS: CMOS voltage level
©Copyright 2018, PADAUK Technology Co. Ltd
Page 16 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4. Device Characteristics
4-1. AC/DC Device Characteristics
Symbol
Description
Operating Voltage
Min
Typ
Max
Unit
Conditions (Ta=25℃)
VDD
2.2
5.0
5.5
V
* Subject to LVR tolerance
System clock
IHRC
0
0
0
0
8M
4M
2M
1M
V
V
V
V
V
DD ≧ 4.0V
DD ≧ 3.0V
DD ≧ 2.5V
DD ≧ 2.2V
DD ≧ 5.0V
IHRC & crystal oscillator
IHRC & crystal oscillator
IHRC & crystal oscillator
Internal low RC oscillator
fSYS
Hz
24K
1.7
15
mA fSYS=IHRC/16=1MIPS@5.0V
uA fSYS=ILRC=12KHz@3.3V
uA fSYS= 0Hz,VDD=5.0V
uA fSYS= 0Hz,VDD=3.3V
VDD=5.0V;
Operating Current
IOP
IPD
Power Down Current
1.0
0.5
(by stopsys command)
Power Save Current
IPS
0.3
mA Band-gap, LVR, IHRC, ILRC,
Timer16 modules are ON.
V
(by stopexe command)
VIL
VIH
IOL
IOH
VIN
Input low voltage for IO lines
Input high voltage for IO lines
IO lines sink current
0
0.7 VDD
7
0.2VDD
VDD
V
10
-7
13
mA VDD=5.0V, VOL=0.5V
mA VDD=5.0V, VOH=4.5V
IO lines drive current
-5
-9
-0.3
VDD+0.3
Input voltage
V
1
IINJ (PIN) Injected current on pin
mA VDD+0.3≧VIN≧ -0.3
62
VDD=5.0V
KΩ VDD=3.3V
VDD=2.2V
RPH
Pull-up Resistance
100
210
3.86
3.35
2.84
2.61
2.37
2.04
1.86
1.67
4.15
3.60
3.05
2.80
2.55
2.20
2.00
1.80
4.44
3.85
3.26
3.00
2.73
2.35
2.14
1.93
VLVR
Low Voltage Reset Voltage *
V
Band-gap Reference Voltage
(before calibration)
1.11
1.20
1.29
VDD=5V, 25oC
V
VBG
Band-gap Reference Voltage *
(after calibration)
VDD=2.2V ~ 5.5V,
1.140*
1.145*
15.76*
15.04*
15.28*
1.200*
1.200*
16*
1.260*
1.255*
16.24*
16.96*
16.72*
-40oC <Ta<85oC*
-20oC <Ta<70oC*
25oC, VDD=2.2V~5.5V
VDD=2.2V~5.5V, -40oC <Ta<85oC*
VDD=2.2V~5.5V, -20oC <Ta<70oC*
Frequency of IHRC after
fIHRC
MHz
16*
calibration *
16*
©Copyright 2018, PADAUK Technology Co. Ltd
Page 17 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Symbol
Description
Min
20.4*
15.6*
16.8*
10.2*
4.55*
5.55*
30
Typ
24*
24*
24*
12*
7*
Max
27.6*
32.4*
31.2*
13.8*
9.45*
8.45*
Unit
Conditions (Ta=25℃)
VDD=5.0V, Ta=25oC
VDD=5.0V, -40oC <Ta<85oC*
VDD=5.0V, -20oC <Ta<70oC*
VDD=3.3V, Ta=25oC
VDD=2.2V, -40oC <Ta<85oC*
VDD=2.2V, -20oC <Ta<70oC*
VDD = 5.0V
fILRC
Frequency of ILRC *
KHz
7*
tINT
VADC
VAD
Interrupt pulse width
Supply voltage for workable ADC
AD Input Voltage
ns
V
2.5
5.0
VDD
12
0
V
ADrs
ADC resolution
bit
0.9
0.8
2
@5V
ADcs ADC current consumption
mA
us
@3V
ADclk ADC clock period
ADC conversion time
2.5V ~ 5.5V
tADCONV (TADCLK is the period of the
selected AD conversion clock)
AD DNL ADC Differential NonLinearity
AD INL ADC Integral NonLinearity
ADos ADC offset*
17
TADCLK 12-bit resolution
±2*
±4*
3
LSB
LSB
mV
RAM data retention voltage*
VDR
1.5
V
PMC234/PMS234 in stop
mode.
CPos Comparator offset*
CPcm Comparator input common
mode*
-
±10
±20
VDD-1.5
500
mV
V
0
CPspt Comparator response time**
100
2.5
ns
us
Both Rising and Falling
Stable time to change
CPmc
7.5
comparator mode
40
20
@5.0V
@3.3V
CPcs Comparator current consumption
uA
R(VDD/2) (VDD/2) pull-up / pull-down
resistance
2.5
5
10
KΩ
Deviation of (VDD/2) output
ΔV(VDD/2)
±1%
±3%
@ VDD = 5.0V
voltage
2408
4096
misc[1:0]=00 (default)
misc[1:0]=01
ILRC
clock
tWDT
Watchdog timeout period
16384
256
misc[1:0]=10
misc[1:0]=11
period
System boot-up period from
power-on
Where TILRC is the clock
period of ILRC
tSBP
1024
TILRC
©Copyright 2018, PADAUK Technology Co. Ltd
Page 18 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Symbol
Description
Min
Typ
Max
Unit
Conditions (Ta=25℃)
System wake-up period
Fast wake-up by IO toggle from
STOPEXE suspend
Where TSYS is the time
period of system clock
Where TSIHRC is the stable time
of IHRC from power-on.
TSIHRC = 5us@5V
128
TSYS
Fast wake-up by IO toggle from
STOPSYS suspend, IHRC is the
system clock
128 TSYS
+
TSIHRC
tWUP
Fast wake-up by IO toggle from
STOPSYS suspend, ILRC is the
system clock
128 TSYS
Where TSILRC is the stable time
of ILRC from power-on.
TSILRC = 43ms@5V
+
TSILRC
Normal wake-up from
STOPEXE or STOPSYS
suspend
Where TILRC is the clock
1024
TILRC period of ILRC
tRST
External reset pulse width
120
us @VDD=5V
*These parameters are for design reference, not tested for each chip.
** Response time is measured with comparator input at (VDD-1.5)/2 -100mV, and (VDD-1.5)/2+100mV
4-2. Absolute Maximum Ratings
Supply Voltage ………………………….. 2.2V ~ 5.5V
Input Voltage …………………………….. -0.3V ~ VDD + 0.3V
Operating Temperature ………………… PMC Series: -40°C ~ 85°C
PMS Series: -20°C ~ 70°C
Junction Temperature …………………… 150 oC
Storage Temperature …………………… -50 oC ~ 125 oC
©Copyright 2018, PADAUK Technology Co. Ltd
Page 19 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-3. Typical ILRC frequency vs. VDD and temperature
©Copyright 2018, PADAUK Technology Co. Ltd
Page 20 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-4. Typical IHRC frequency deviation vs. VDD and temperature (calibrated to 16MHz)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 21 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-5. Typical operating current vs. VDD @ system clock = ILRC/n
Conditions:
2-FPPA (FPPA0: tog PA0, FPPA1: idle)
ON: ILRC; OFF: Band-gap, LVR, IHRC, EOSC, T16, TM2, ADC, Comparator modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
4-6. Typical operating current vs. VDD @ system clock = IHRC/n
Conditions:
2-FPPA (FPPA0: tog PA0, FPPA1: idle)
ON: Band-gap, LVR, IHRC; OFF: ILRC, EOSC, T16, TM2, ADC, Comparator modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
©Copyright 2018, PADAUK Technology Co. Ltd
Page 22 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-7. Typical operating current vs. VDD @ system clock = 1MHz EOSC / n
Conditions:
2-FPPA (FPPA0: tog PA0, FPPA1: idle)
ON: EOSC, MISC.6 = 1; OFF: Band-gap, LVR, IHRC, ILRC, T16, TM2, ADC, Comparator modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
4-8. Typical operating current vs. VDD @ system clock = 4MHz EOSC / n
Conditions:
2-FPPA (FPPA0: tog PA0, FPPA1: idle)
ON: EOSC, MISC.6 = 1; OFF: Band-gap, LVR, IHRC, ILRC, T16, TM2, ADC, Comparator modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
©Copyright 2018, PADAUK Technology Co. Ltd
Page 23 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-9. Typical operating current vs. VDD @ system clock = 32KHz EOSC / n
Conditions:
2-FPPA (FPPA0: tog PA0, FPPA1: idle)
ON: EOSC, MISC.6 = 1; OFF: Band-gap, LVR, IHRC, ILRC, T16, TM2, ADC, Comparator modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
4-10. Typical IO driving current (IOH) and sink current (IOL)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 24 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-11. Typical IO input high/low threshold voltage (VIH/VIL)
4-12. Typical resistance of IO pull high device
©Copyright 2018, PADAUK Technology Co. Ltd
Page 25 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-13. Typical VDD/2 Bias output voltage
4-14. Typical power down current (IPD) and power save current (IPS)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 26 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-15. Timing charts for boot up conditions
LVD level
VDD
POR
VDD
LVD
t
SBP
t
SBP
Program
Program
Execution
Execution
Boot up from LVD detection
Boot up from Power-On Reset
VDD
VDD
t
SBP
WD
Time Out
Reset#
t
SBP
Program
Execution
Program
Execution
Boot up from Reset Pad reset
Boot up from Watch Dog Time Out
©Copyright 2018, PADAUK Technology Co. Ltd
Page 27 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-15. Typical Comparator Responsive Time (Use V internal R
)
Measurement Conditions:
Plus input: PC5
Measurement Conditions:
Plus input: PC5
Minus input: V internal R = (5/16)*VDD
V internal R: use Case I, R1
Fix V internal R, use PC5 falling edge to measure
response time
Minus input: V internal R = (5/16)*VDD
V internal R: use Case I, R1
Fix V internal R, use PC5 rising edge to measure
response time
nS Response Time (Plus input with falling edge)
nS
Response Time (Plus input with rising edge)
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
60
40
40
20
20
2.2 2.5
3.0 3.5 4.0 4.5 5.0 5.5 (V)
VDD
2.2 2.5
3.0 3.5 4.0 4.5 5.0 5.5 (V)
VDD
Measurement Conditions:
Plus input: V internal R = (5/16)*VDD
Minus input: PC5
Measurement Conditions:
Plus input: V internal R = (5/16)*VDD
Minus input: PC5
V internal R: use Case I, R1
Fix V internal R, use PC5 falling edge to measure
response time
V internal R: use Case I, R1
Fix V internal R, use PC5 rising edge to measure
response time
nS Response Time (Minus input with falling edge)
nS Response Time (Minus input with rising edge)
200
180
160
140
120
100
80
220
200
180
160
140
120
100
80
60
40
60
20
40
2.2 2.5
3.0 3.5 4.0 4.5 5.0 5.5 (V)
VDD
2.2 2.5
3.0 3.5 4.0 4.5 5.0 5.5 (V)
VDD
©Copyright 2018, PADAUK Technology Co. Ltd
Page 28 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
4-16. Typical Comparator Responsive Time (Use External Inputs)
Measurement Conditions:
Plus input: PC5
Minus input: PC0 = (5/16)VDD
Fix PC0, use PC5 falling edge to measure
response time
Measurement Conditions:
Plus input: PC5
Minus input: PC0 = (5/16)VDD
Fix PC0, use PC5 rising edge to measure
response time
nS Response Time (Plus input with falling edge)
nS Response Time (Plus input with rising edge)
220
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
60
40
40
20
2.2 2.5
3.0 3.5 4.0 4.5 5.0 5.5 (V)
VDD
2.2 2.5
3.0 3.5 4.0 4.5 5.0 5.5 (V)
VDD
Measurement Conditions:
Plus input: PC5 = (5/16)VDD
Minus input: PC0
Fix PC5, use PC0 falling edge to measure
response time
Measurement Conditions:
Plus input: PC5 = (5/16)VDD
Minus input: PC0
Fix PC5, use PC0 rising edge to measure
response time
nS Response Time (Plus input with falling edge)
nS Response Time (Plus input with rising edge)
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
60
40
40
20
20
2.2 2.5
3.0 3.5 4.0 4.5 5.0 5.5 (V)
VDD
2.2 2.5
3.0 3.5 4.0 4.5 5.0 5.5 (V)
VDD
©Copyright 2018, PADAUK Technology Co. Ltd
Page 29 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5. Functional Description
5-1. Processing Units
There are two processing units (FPP unit) inside the chip of PMC234/PMS234. In each processing unit, it
includes (i) its own Program Counter to control the program execution sequence (ii) its own Stack Pointer to
store or restore the program counter for program execution (iii) its own accumulator (iv) Status Flag to record
the status of program execution. Each FPP unit has its own program counter and accumulator for program
execution, flag register to record the status, and stack pointer for jump operation. Based on such
architecture, FPP unit can execute its own program independently, thus parallel processing can be expected.
These two FPP units share the same 4Kx16 bits OTP program memory, 208 bytes data SRAM and all the IO
ports, these two FPP units are operated at mutual exclusive clock cycles to avoid interference. One task
switch is built inside the chip to decide which FPP unit should be active for the corresponding cycle. The
hardware diagram and basic timing diagram of FPP units are illustrated in Fig. 1. For FPP0 unit, its program
will be executed in sequence every other system clock, shown as (M-1)th, Mth and (M+1)th instructions. For
FPP1 unit, its program will be also executed in sequence every other system clock, shown as (N-1)th, Nth
and (N+1)th instructions.
System Clock
FPP0
Program Counter 0
Stack Pointer 0
Accumulator 0
Task Switch
Time
(M-1)th
Mth
(M+1)th
4KW OTP
Program
Memory
Flag register 0
FPP0 active
FPP1
Program Counter 1
Stack Pointer 1
Accumulator 1
208 bytes
SRAM
(N-1)th
Nth
(N+1)th
IO Port
Flag register 1
FPP1 active
Fig. 1: Hardware and Timing Diagram of FPP unit
Each FPP unit has half computing power of whole system; for example, FPP0 and FPP1will be operated at
4MHz if system clock is 8MHz. The FPP unit can be enabled or disabled by programming the FPP unit
Enable Register, only FPP0 is enabled after power-on reset. The system initialization will be started from
FPP0 and FPP1 unit can be enabled by user’s program if necessary. Both FPP0 and FPP1 can be enabled
or disabled by using any one FPP unit.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 30 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-1-1. Program Counter
Program Counter (PC) is the unit that contains the address of an instruction to be executed next. The
program counter is automatically incremented at each instruction cycle so that instructions are retrieved
sequentially from the program memory. Certain instructions, such as branches and subroutine calls,
interrupt the sequence by placing a new value in the program counter. The bit length of the program
counter is 12 for PMC234/PMS234. The program counter of FPP0 is 0 after hardware reset and 1 for FPP1.
Whenever an interrupt happens in FPP0, the program counter will jump to 0x10 for interrupt service routine.
Each FPP unit has its own program counter to control the program execution sequence.
5-1-2. Stack Pointer
The stack pointer in each processing unit is used to point the top of the stack area where the local variables
and parameters to subroutines are stored; the stack pointer register (sp) is located in IO address 0x02h.
The bit number of stack pointer is 8 bit; the stack memory cannot be accessed over 208 bytes and should
be defined within 208 bytes from 0x00h address. The stack memory of PMC234/PMS234 for each FPP unit
can be assigned by user via stack pointer register, means that the depth of stack pointer for each FPP unit
is adjustable in order to optimize system performance. The following example shows how to define the
stack in the ASM (assembly language) project:
﹒ROMADR
GOTO
GOTO
...
0
FPPA0
FPPA1
﹒RAMADR
WORD
WORD
...
0
// Address must be less than 0x100
// one WORD
// two WORD
Stack0 [1]
Stack1 [2]
FPPA0:
SP
=
=
Stack0;
// assign Stack0 for FPPA0,
// one level call because of Stack0[1]
...
call
...
function1
FPPA1:
SP
Stack1;
// assign Stack1 for FPPA1,
// two level call because of Stack1[2]
...
call
...
function2
In Mini-C project, the stack calculation is done by system software, user will not have effort on it, and the
example is shown as below:
void
FPPA0 (void)
{
...
}
©Copyright 2018, PADAUK Technology Co. Ltd
Page 31 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
User can check the stack assignment in the window of program disassembling, Fig. 2 shows that the status
of stack before FPP0 execution, system has calculated the required stack space and has reserved for the
program.
Fig. 2: Stack Assignment in Mini-C project
5-1-3. Single FPP mode
For traditional MCU user who does not need parallel processing capability, PMC234/PMS234 provides
single FPP mode optional to behave as traditional MCU. After single FPP mode is selected, FPP1 is always
disabled and only FPP0 is active. Fig.3 shows the timing diagram for each FPP unit, FPP1 is always
disabled and only FPP0 active. Please notice that wait and delay instructions are NOT supported when
single FPP mode is chosen.
System Clock
FPP0
Task Switch
Program Counter 0
Time
Stack Pointer 0
(M-1)th
(M+1)
(M+3)th
th (M+2)th
(M+4)th
Mth
4KW OTP
Program
Memory
Accumulator 0
Flag register 0
FPP0 active
FPP1
208 bytes
SRAM
Program Counter 1
Stack Pointer 1
Accumulator 1
Flag register 1
IO Port
FPP1 is always inactive
Fig. 3: Timing Diagram of single FPP mode
©Copyright 2018, PADAUK Technology Co. Ltd
Page 32 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-2. Program Memory -- OTP
5-2-1. Program Memory Assignment
The OTP (One Time Programmable) program memory is used to store the program instructions to be
executed. All program codes for each FPP unit are stored in this OTP memory for both FPP0 and FPP1.
The OTP program memory may contains the data, tables and interrupt entry. After reset, the initial address
for FPP0 is 0x0 and 0x1 for FPP1. The interrupt entry is 0x10 if used and interrupt function is for FPP0 only,
the last eight addresses are reserved for system using, like checksum, serial number, etc. The OTP
program memory for PMC234/PMS234 is a 4Kx16 bit that is partitioned as Table 1. The OTP memory from
address 0xFF8 to 0xFFF is for system using, address space from 0x002 to 0x00F and from 0x011 to 0xFF7
are user program space. The address 0x001 is the FPP1 initial address for two FPP units mode and user
program for single FPP unit mode.
Address
0x000
0x001
0x002
•
Function
FPP0 reset – goto instruction
FPP1 reset – goto instruction
User program
•
0x00F
0x010
0x011
•
User program
Interrupt entry address
User program
•
0xFF7
0xFF8
•
User program
System Using
•
0xFFF
System Using
Table 1: Program Memory Organization of PMC234/PMS234
©Copyright 2018, PADAUK Technology Co. Ltd
Page 33 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-2-2. Example of Using Program Memory for Two FPP mode
Table 2 shows one example of using program memory which two FPP units are active.
Address
Function
000 FPP0 reset – goto instruction (goto
0x020)
001 Begin of FPP1 program
• •
00F goto 0x1A1 to continue FPP1 program
010 Interrupt entry address (FPP0 only)
• •
01F End of ISR
020 Begin of FPP0 user program
• •
1A0 End of FPP0 user program
1A1 Continuing FPP1 program
• •
FF7 End of FPP1 program
FF8 System Using
• •
FFF System Using
Table 2: Example of using Program Memory for two FPP units mode
5-2-3. Example of Using Program Memory for Single FPP mode
The entire user’s program memory can be assigned to FPP0 when single FPP mode is selected. Table 3
shows the example of program memory using for single FPP unit mode.
Address
000 FPP0 reset
Function
001 Begin of user program
002 user program
• •
00F goto instruction (goto 0x020)
010 Interrupt entry address
011 ISR
• •
01F End of ISR
020 user program
• •
• •
FF7 user program
FF8 System Using
• •
FFF System Using
Table 3: Example of using Program Memory for single FPP mode
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Page 34 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-3. Program Structure
5-3-1. Program structure of two FPP units mode
After power-up, the program starting address of FPP0 is 0x000 and 0x001 for FPP1. The 0x010 is the entry
address of interrupt service routine, which belongs to FPP0 only. The basic firmware structure for
PMC234/PMS234 is shown as Fig. 4, the program codes of two FPP units are placed in one whole
program space. Except for the initial addresses of processing units and entry address of interrupt, the
memory location is not specially specified; the program codes of processing unit can be resided at any
location no matter what the processing unit is. After power-up, the fpp0Boot will be executed first, which will
include the system initialization and other FPP units enabled.
.romadr 0x00
// Program Begin
goto
fpp0Boot;
goto fpp1Boot;
//------Interrpt service Routine-----------------
.romadr 0x010
pushaf ;
t0sn
goto
t0sn
…
intrq.0;
ISR_PA0;
intrq.1;
//PA.0 ISR
//PB.0 ISR
goto
ISR_PB0;
//------End of ISR---------
//------ Begin of FPP0 ----------
fpp0Boot :
//--- Initialize FPP0 SP and so on…
…
fpp0Loop:
…
goto fpp0Loop:
FPP0 function
subroutine
//------ End of FPP0 --------
//------ Begin of FPP1 ----------
fpp1Boot :
//--- Initialize FPP1 SP and so on…
…
FPP1 function
subroutine
fpp1Loop:
…
goto fpp1Loop:
//--------- End of FPP1 --------
Fig. 4: Program Structure
5-3-2. Program structure of single FPP mode
After power-up, the program starting address of FPP0 is 0x000, 0x010 is the entry address of interrupt
service routine. For single FPP unit mode, the firmware structure is same as traditional MCU. After power-
up, the program will be executed from address 0x000, then continuing the program sequence.
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Page 35 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-4. Boot Procedure
POR (Power-On-Reset) is used to reset PMC234/PMS234 when power up, however, the supply voltage
may be not stable. To ensure the stability of supply voltage after power up, it will wait 1024 ILRC clock cycles
before first instruction being executed, which is tSBP and shown in the Fig. 5. After boot up procedure, the
default system clock is ILRC; user should ensure that the power should be stable after boot up time.
VDD
t
SBP
POR
Program
Execution
Boot up from Power-On Reset
Fig. 5: Power-On-Reset Sequence
Fig. 6 shows the typical program flow after boot up. Please notice that the FPP1 is disabled after reset and
recommend NOT enabling FPP1 before system and FPP0 initialization.
Start
Initialize the system
FPP0
Initialize the I/O
Initialize the shared
Resources
Set the Stack of FPP0
Enable FPP1
FPP0 Firmware
Set the Stack of FPP1
FPP1
FPP1 Firmware
Fig. 6: Boot Procedure
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Page 36 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-5. Data Memory -- SRAM
Fig. 7 shows the SRAM data memory organization of PMC234/PMS234, all the SRAM data memory could
be accessed by FPP0 and FPP1 directly with 1T clock cycle, the data access can be byte or bit operation.
Besides data storage, the SRAM data memory is also served as data pointer of indirect access method and
the stack memory for all FPP units.
The stack memory for each processing unit should be independent from each other, and defined in the data
memory. The stack pointer is defined in the stack pointer register of each processing unit; the depth of stack
memory of each processing unit is defined by the user. The arrangement of stack memory fully flexible and
can be dynamically adjusted by the user.
For indirect memory access mechanism, the data memory is used as the data pointer to address the data
byte. All the data memory could be the data pointer; it’s quite flexible and useful to do the indirect memory
access. Since the data width is 8-bit, all the 208 bytes data memory of PMC234/PMS234 can be accessed
by indirect access mechanism.
Address
000h
˙
DATA
˙
index
˙
DATA
FPP0
FPP1
˙
FPP0 stack
˙
˙
˙
˙
DATA
˙
FPP1 stack
˙
˙
˙
˙
DATA
˙
˙
˙
˙
˙
˙
CFh
Fig. 7: Data Memory Organization
5-6. Arithmetic and Logic Unit
Arithmetic and Logic Unit (ALU) is the computation element to operate integer arithmetic, logic, shift and
other specialized operations. The operation data can be from instruction, accumulator or SRAM data
memory. Computation result could be written into accumulator or SRAM. FPP0 and FPP1 will share ALU for
its corresponding operation.
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Page 37 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-7. Oscillator and clock
There are three oscillator circuits provided by PMC234/PMS234: external crystal oscillator (EOSC), internal
high RC oscillator (IHRC) and internal low RC oscillator (ILRC), and these three oscillators are enabled or
disabled by registers eoscr.7, clkmd.4 and clkmd.2 independently. User can choose one of these three
oscillators as system clock source and use clkmd register to target the desired frequency as system clock to
meet different application.
Oscillator Module
EOSC
Enable/Disable
eoscr.7
IHRC
clkmd.4
ILRC
clkmd.2
5-7-1. Internal High RC oscillator and Internal Low RC oscillator
After boot-up, the IHRC and ILRC oscillators are enabled. The frequency of IHRC can be calibrated to
eliminate process variation by ihrcr register; normally it is calibrated to 16MHz. The frequency deviation
can be within 1% normally after calibration under the calibrated voltage, however, it still drifts slightly with
supply voltage and operating temperature. Please refer to the measurement chart for IHRC frequency
verse VDD and IHRC frequency verse temperature. The frequency of ILRC will vary by process, supply
voltage and temperature, please refer to DC specification and do not use for accurate timing application.
5-7-2. Chip calibration
The IHRC frequency and band-gap reference voltage may be different chip by chip due to manufacturing
variation, PMC234/PMS234 provide both the IHRC frequency calibration and band-gap calibration to
eliminate this variation, and this function can be selected when compiling user’s program and the command
will be inserted into user’s program automatically. The calibration command is shown as below:
.ADJUST_IC SYSCLK=IHRC/(p1), IHRC=(p2)MHz, VDD=(p3)V, Bandgap=(p4);
Where, p1=2, 4, 8, 16, 32; In order to provide different system clock.
p2=14 ~ 18; In order to calibrate the chip to different frequency, 16MHz is the usually one.
p3=2.5 ~ 5.5; In order to calibrate the chip under different supply voltage.
p4= On or Off; Band-gap calibration is On or Off.
5-7-3. IHRC Frequency Calibration and System Clock
During compiling the user program, the options for IHRC calibration and system clock are shown as Table 4:
SYSCLK
○ Set IHRC / 2
○ Set IHRC / 4
○ Set IHRC / 8
○ Set IHRC / 16
○ Set IHRC / 32
○ Set ILRC
CLKMD
IHRCR
Calibrated
Calibrated
Calibrated
Description
= 34h (IHRC / 2)
= 14h (IHRC / 4)
= 3Ch (IHRC / 8)
IHRC calibrated to 16MHz, CLK=8MHz (IHRC/2)
IHRC calibrated to 16MHz, CLK=4MHz (IHRC/4)
IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)
IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)
IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)
IHRC calibrated to 16MHz, CLK=ILRC
= 1Ch (IHRC / 16) Calibrated
= 7Ch (IHRC / 32) Calibrated
= E4h (ILRC / 1)
No change
Calibrated
○ Disable
No Change IHRC not calibrated, CLK not changed, Band-gap OFF
Table 4: Options for IHRC Frequency Calibration
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Page 38 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Usually, .ADJUST_IC will be the first command after boot up, in order to set the target operating frequency
whenever starting the system. The program code for IHRC frequency calibration is executed only one time
that occurs in writing the codes into OTP memory; after then, it will not be executed again. If the different
option for IHRC calibration is chosen, the system status is also different after boot. The following shows the
status of PMC234/PMS234 for different option:
(1) .ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V, Bandgap=On
After boot up, CLKMD = 0x34:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/2 = 8MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V
(2) .ADJUST_IC
SYSCLK=IHRC/4, IHRC=16MHz, VDD=3.3V, Bandgap=On
After boot up, CLKMD = 0x14:
IHRC frequency is calibrated to 16MHz@VDD=3.3V and IHRC module is enabled
System CLK = IHRC/4 = 4MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V
(3) .ADJUST_IC
SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V, Bandgap=On
After boot up, CLKMD = 0x3C:
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/8 = 2MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V
(4) .ADJUST_IC
SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.5V, Bandgap=On
After boot up, CLKMD = 0x1C:
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/16 = 1MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V
(5) .ADJUST_IC
SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V, Bandgap=Off
After boot up, CLKMD = 0x7C:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/32 = 500KHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(6) .ADJUST_IC
SYSCLK=ILRC, IHRC=16MHz, VDD=5V, Bandgap=Off
After boot up, CLKMD = 0XE4:
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is disabled
System CLK = ILRC
Watchdog timer is disabled, ILRC is enabled, PA5 is input mode
(7) .ADJUST_IC
DISABLE
After boot up, CLKMD is not changed (Do nothing):
IHRC is not calibrated and IHRC module is disabled, Band-gap is not calibrated
System CLK = ILRC
Watchdog timer is enabled, ILRC is enabled, PA5 is in input mode
©Copyright 2018, PADAUK Technology Co. Ltd
Page 39 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-7-4. External Crystal Oscillator
If crystal oscillator is used, a crystal or resonator is required between X1 and X2. Fig. 8 shows the
hardware connection under this application; the range of operating frequency of crystal oscillator can be
from 32 KHz to 4MHz, depending on the crystal placed on; higher frequency oscillator than 4MHz is NOT
supported.
(Select driving current for oscillator)
eoscr[6:5]
(Enable crystal oscillator)
eoscr.7
C1
PA7/X1
System clock = EOSC
PA6/X2
C2
The values of C1 and C2 should depend on
the specification of crystal.
Fig. 8: Connection of crystal oscillator
Besides crystal, external capacitor and options of PMC234/PMS234 should be fine tuned in eoscr (0x0a)
register to have good sinusoidal waveform. The eoscr.7 is used to enable crystal oscillator module, eoscr.6
and eoscr.5 are used to set the different driving current to meet the requirement of different frequency of
crystal oscillator:
eoscr.[6:5]=01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
eoscr.[6:5]=10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
eoscr.[6:5]=11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
Table 5 shows the recommended values of C1 and C2 for different crystal oscillator; the measured start-up
time under its corresponding conditions is also shown. Since the crystal or resonator had its own
characteristic, the capacitors and start-up time may be slightly different for different type of crystal or
resonator, please refer to its specification for proper values of C1 and C2.
Measured
Frequency
C1
C2
Conditions
Start-up time
6ms
4MHz
1MHz
32KHz
4.7pF
10pF
22pF
4.7pF
10pF
22pF
(eoscr[6:5]=11, misc.6=0)
(eoscr[6:5]=10, misc.6=0)
(eoscr[6:5]=01, misc.6=0)
11ms
450ms
Table 5: Recommend values of C1 and C2 for crystal and resonator oscillators
When using the crystal oscillator, user must pay attention to the stable time of oscillator after enabling it,
the stable time of oscillator will depend on frequency ` crystal type ` external capacitor and supply voltage.
Before switching the system to the crystal oscillator, user must make sure the oscillator is stable; the
reference program is shown as below:
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Page 40 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
void
{
FPPA0 (void)
.ADJUST_IC SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V, Bandgap=On
// If Band-gap is not calibrated, it can use “. ADJUST_IC ...... Bandgap=Off”
...
$
$
EOSCR Enable, 4Mhz;
T16M EOSC, /1, BIT13;
// EOSCR = 0b110_00000;
// T16 receive 2^14=16384 clocks of crystal EOSC,
// Intrq.T16 =>1, crystal EOSC Is stable
WORD
count
=
0;
stt16count;
Intrq.T16 =
0;
wait1
Intrq.T16;
0xB4;
// count from 0x0000 to 0x2000, then setINTRQ.T16
// switch system clock to EOSC;
// disable IHRC
clkmd
=
Clkmd.4 = 0;
...
Please notice that the crystal oscillator should be fully turned off before entering the power-down mode, in
order to avoid unexpected wakeup event. If the 32KHz crystal oscillator is used and extremely low
operating current is required, misc.6 can be set to reduce current after crystal oscillator is running normally.
5-7-5. System Clock and LVR level
The clock source of system clock comes from EOSC, IHRC and ILRC, the hardware diagram of system
clock in the PMC234/PMS234 is shown as Fig. 9.
clkmd[7:5]
÷2, ÷4, ÷6,
IHRC
clock
÷8, ÷16, ÷32, ÷64
System
clock
CLK
M
U
X
EOSC
clock
÷1, ÷2, ÷4, ÷8
ILRC
÷1 (default), ÷4
clock
clkmd.3
Fig. 9: Options of System Clock
User can choose different operating system clock depends on its requirement; the selected operating
system clock should be combined with supply voltage and LVR level to make system stable. The LVR
level will be selected during compilation, and the lowest LVR levels can be chosen for different operating
frequencies. Please refer to Section 4.1.
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Page 41 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-7-6. System Clock Switching
After IHRC calibration, user may want to switch system clock to a new frequency or may switch system
clock at any time to optimize the system performance and power consumption. Basically, the system clock
of PMC234/PMS234 can be switched among IHRC, ILRC and EOSC by setting the clkmd register at any
time; system clock will be the new one after writing to clkmd register immediately. Please notice that the
original clock module can NOT be turned off at the same time as writing command to clkmd register. The
examples are shown as below and more information about clock switching, please refer to the “Help ->
Application Note -> CLKMD”.
Case 1: Switching system clock from ILRC to IHRC/2
…
//
//
//
system clock is ILRC
CLKMD
CLKMD.2
…
=
=
0x34;
0;
switch to IHRC/2,ILRC CAN NOT be disabled here
ILRC CAN be disabled at this time
Case 2: Switching system clock from ILRC to EOSC
…
//
system clock is ILRC
CLKMD
CLKMD.2
…
=
=
0xA6; //
switch to IHRC,ILRC CAN NOT be disabled here
ILRC CAN be disabled at this time
0;
//
Case 3: Switching system clock from IHRC/2 to ILRC
…
//
//
//
system clock is IHRC/2
CLKMD
CLKMD.4
…
=
=
0xF4;
0;
switch to ILRC,IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
Case 4: Switching system clock from IHRC/2 to EOSC
…
//
system clock is IHRC/2
CLKMD
CLKMD.4
=
=
0XB0; //
switch to EOSC,IHRC CAN NOT be disabled here
IHRC CAN be disabled at this time
0;
//
…
Case 5: Switching system clock from IHRC/2 to IHRC/4
…
//
system clock is IHRC/2, ILRC is enabled here
switch to IHRC/4
CLKMD
…
=
0X14; //
Case 6: System may hang if it is to switch clock and turn off original oscillator at the same time
…
//
//
//
system clock is ILRC
CLKMD
=
0x30;
CAN NOT switch clock from ILRC to IHRC/2 and
turn off ILRC oscillator at the same time
©Copyright 2018, PADAUK Technology Co. Ltd
Page 42 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-8. 16-bit Timer (Timer16)
A 16-bit hardware timer (Timer16) is implemented in the PMC234/PMS234, the clock sources of Timer16
may come from system clock (CLK), clock of external crystal oscillator (EOSC), internal high RC oscillator
(IHRC), internal low RC oscillator (ILRC) and PA0, a multiplex is used to select clock output for the clock
source. Before sending clock to the counter16, a pre-scaling logic with divided-by-1, 4, 16, and 64 is used
for wide range counting. The 16-bit counter performs up-counting operation only, the counter initial values
can be stored from memory by stt16 instruction and the counting values can be loaded to memory by ldt16
instruction. A selector is used to select the interrupt condition of Timer16, whenever overflow occurs, the
Timer16 interrupt can be triggered. The hardware diagram of Timer16 is shown as Fig. 10. The interrupt
source of Timer16 comes from one of bit 8 to 15 of 16-bit counter, and the interrupt type can be rising edge
trigger or falling edge trigger which is specified in the bit 4 of integs register (IO address 0x0C).
stt16 command
DATA Memory
t16m[7:5]
t16m[4:3]
ldt16 command
CLK
M
U
X
Pre-
scalar
÷
1, 4,
16, 64
16-bit
up
counter
Bit[15:0]
IHRC
EOSC
ILRC
Data Bus
PA0↓
Bit[15:8]
M
U
X
To set
interrupt
request flag
or
t16m[2:0]
integs.4
Fig. 10: Hardware diagram of Timer16
When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three
parameters to define the Timer16; 1st parameter is used to define the clock source of Timer16, 2nd
parameter is used to define the pre-scalar and the last one is to define the interrupt source. The detail
description is shown as below:
T16M
$ 7~5:
IO_RW
0x06
STOP, SYSCLK, X, X, IHRC, EOSC, ILRC, PA0_F
/1, /4, /16, /64
// 1st par.
// 2nd par.
// 3rd par.
$ 4~3:
$ 2~0:
BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15
©Copyright 2018, PADAUK Technology Co. Ltd
Page 43 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
User can define the parameters of T16M based on system requirement, some examples are shown below
and more examples can refer to “Help Application Note IC Introduction Register Introduction
T16M” in IDE utility.
$
T16M
SYSCLK, /64, BIT15;
// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1
// if using System Clock = IHRC / 2 = 8 MHz
// SYSCLK/64 = 8 MHz/64 = 125KHz, about every 512 mS to generate INTRQ.2=1
$
$
$
T16M
EOSC, /1, BIT13;
// choose (EOSC/1) as clock source, every 2^14 clocks to generate INTRQ.2=1
// if EOSC=32768 Hz, 32768 Hz/(2^14) = 2Hz, every 0.5S to generate INTRQ.2=1
T16M
PA0_F, /1, BIT8;
// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1
// receiving every 512 times PA0 to generate INTRQ.2=1
T16M
STOP;
// stop Timer16 counting
If Timer16 is operated at free running, the frequency of interrupt can be described as below:
FINTRQ_T16M = Fclock source ÷ P ÷ 2n+1
Where,
F is the frequency of selected clock source to Timer16;
P is the selection of t16m [4:3]; (1, 4, 16, 64)
N is the nth bit selected to request interrupt service, for example: n=10 if bit 10 is selected.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 44 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-9. 8-bit Timer (Timer2) with PWM generation
An 8-bit hardware timer (Timer2) with PWM generation is implemented in the PMC234/PMS234, please
refer to Fig. 11 shown its hardware diagram, the clock sources of Timer2 may come from system clock,
internal high RC oscillator (IHRC), internal low RC oscillator (ILRC), PA0, PA3, PA4 and comparator output,
bit [7:4] of register tm2c are used to select the clock of Timer2. Please notice that external crystal oscillator
is NOT to be the clock of Timer2 because of possible clock glitch. If IHRC is selected for Timer2 clock
source, the clock sent to Timer2 will keep running when using ICE in halt state. According to the setting of
register tm2c[3:2], Timer2 output can be selectively output to PA1 or PA2 or PA3. At this point, regardless of
whether PX.x is the input or output state, Timer2 signal will be forced to output. A clock pre-scaling module
is provided with divided-by-1, 4, 16, and 64 options, controlled by bit [6:5] of tm2s register; one scaling
module with divided-by-1~31 is also provided and controlled by bit [4:0] of tm2s register. In conjunction of
pre-scaling function and scaling function, the frequency of Timer2 clock (TM2_CLK) can be wide range and
flexible. TM2_CLK can be selected as system clock in order to provide special frequency of system clock,
please refer to clkmd register.
The Timer2 counter performs 8-bit up-counting operation only; the counter values can be set or read back
by tm2ct register. The 8-bit counter will be clear to zero automatically when its values reach for upper bound
register, the upper bound register is used to define the period of timer or duty of PWM. There are two
operating modes for Timer2: period mode and PWM mode; period mode is used to generate periodical
output waveform or interrupt event; PWM mode is used to generate PWM output waveform with optional 6-
bit or 8-bit PWM resolution, Fig. 12 shows the timing diagram of Timer2 for both period mode and PWM
mode.
TM2_CLK
tm2s.7
tm2s[6:5] tm2s[4:0]
tm2c[7:4]
tm2c.1
edge to
interrupt
CLK,
IHRC,
ILRC,
Cmp,
PA0,
M
U
X
Pre-
scalar
÷
1, 4,
16, 64
Scalar
8-bit
up
counter
tm2ct[7:0]
÷
1 ~ 31
X
O
R
D
E
M
U
X
~PA0,
PA3,
PA1
PA2
PA3
~PA3,
PA4,
~PA4
upper
bound
register
tm2c.0
tm2b[7:0]
tm2c[3:2]
Fig. 11 : Timer2 hardware diagram
©Copyright 2018, PADAUK Technology Co. Ltd
Page 45 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Time out and
Time out and
Time out and
Interrupt request
Interrupt request
Interrupt request
Counter
0xFF
bound
Counter
0xFF
Counter
0x3F
bound
bound
Time
Time
Time
Time
Time
Event Trigger
Event Trigger
Event Trigger
Output-pin
Output-pin
Output-pin
Time
Mode 0 – Period Mode
Mode 1 – 8-bit PWM Mode
Mode 1 – 6-bit PWM Mode
Fig. 12: Timing diagram of Timer2 in period mode and PWM mode (tm2c.1=1)
5-9-1. Using the Timer2 to generate periodical waveform
If periodical mode is selected, the duty cycle of output is always 50%; its frequency can be summarized as
below:
Frequency of Output = Y ÷ [2 × (K+1) × S1 × (S2+1) ]
Where, Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1 = tm2s[6:5] : pre-scalar (1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (1 ~ 31)
Example 1:
tm2c = 0b0001_1100, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ [ 2 × (127+1) × 1 × (0+1) ] = 31.25KHz
Example 2:
tm2c = 0b0001_1100, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s[7:0] = 0b0_11_11111, S1=64 , S2 = 31
frequency = 8MHz ÷ ( 2 × (127+1) × 64 × (31+1) ) =15.25Hz
©Copyright 2018, PADAUK Technology Co. Ltd
Page 46 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Example 3:
tm2c = 0b0001_1100, Y=8MHz
tm2b = 0b0000_1111, K=15
tm2s = 0b0_00_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (15+1) × 1 × (0+1) ) = 250KHz
Example 4:
tm2c = 0b0001_1100, Y=8MHz
tm2b = 0b0000_0001, K=1
tm2s = 0b0_00_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (1+1) × 1 × (0+1) ) =2MHz
The sample program for using the Timer2 to generate periodical waveform from PA2 is shown as below:
void
{
FPPA0 (void)
. ADJUST_IC SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
…
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA2, period mode
tm2c = 0b0001_01_0_0;
while(1)
{
nop;
}
}
©Copyright 2018, PADAUK Technology Co. Ltd
Page 47 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-9-2. Using the Timer2 to generate 8-bit PWM waveform
If 8-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=0, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [256 × S1 × (S2+1) ]
Duty of Output = [( K+1 ) ÷ 256]×100%
Where, Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1 = tm2s[6:5] : pre-scalar (1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (1 ~ 31)
Example 1:
tm2c = 0b0001_1110, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 2:
tm2c = 0b0001_1110, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0_11_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 256 × 64 × (31+1) ) = 15.25Hz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 3:
tm2c = 0b0001_1110, Y=8MHz
tm2b = 0b1111_1111, K=255
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(255+1) ÷ 256] × 100% = 100%
Example 4:
tm2c = 0b0001_1110, Y=8MHz
tm2b = 0b0000_1001, K = 9
tm2s = 0b0_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(9+1) ÷ 256] × 100% = 3.9%
©Copyright 2018, PADAUK Technology Co. Ltd
Page 48 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
The sample program for using the Timer2 to generate PWM waveform from PA2 is shown as below:
void
{
FPPA0 (void)
. .ADJUST_IC SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
wdreset;
tm2ct = 0x00;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
//
8-bit PWM, pre-scalar = 1, scalar = 2
system clock, output=PA2, PWM mode
tm2c = 0b0001_01_1_0;
while(1)
{
nop;
}
}
5-9-3. Using the Timer2 to generate 6-bit PWM waveform
If 6-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=1, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [64 × S1 × (S2+1) ]
Duty of Output = [( K+1 ) ÷ 64] × 100%
Where, tm2c[7:4] = Y : frequency of selected clock source
tm2b[7:0] = K : bound register in decimal
tm2s[6:5] = S1 : pre-scalar (1, 4, 16, 64)
tm2s[4:0] = S2 : scalar register in decimal (1 ~ 31)
Example 1:
tm2c = 0b0001_1110, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(31+1) ÷ 64] × 100% = 50%
Example 2:
tm2c = 0b0001_1110, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1_11_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 64 × 64 × (31+1) ) = 61.03 Hz
duty of output = [(31+1) ÷ 64] × 100% = 50%
©Copyright 2018, PADAUK Technology Co. Ltd
Page 49 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
Example 3:
tm2c = 0b0001_1110, Y=8MHz
tm2b = 0b0011_1111, K=63
tm2s = 0b1_00_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty of output = [(63+1) ÷ 64] × 100% = 100%
Example 4:
tm2c = 0b0001_1110, Y=8MHz
tm2b = 0b0000_0000, K=0
tm2s = 0b1_00_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(0+1) ÷ 64] × 100% =1.5%
5-10. WatchDog Timer
The watchdog timer (WDT) is a counter with clock coming from ILRC and there are four different timeout
periods of watchdog timer can be chosen by setting the misc register, it is:
256 ILRC clocks period if register misc[1:0]=11
2048 ILRC clocks period if register misc[1:0]=00 (default)
4096 ILRC clocks period if register misc[1:0]=01
16384 ILRC clocks period if register misc[1:0]=10
The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature;
user should reserve guard band for save operation. WDT can be cleared by power-on-reset or by
command wdreset at any time. When WDT is timeout, PMC234/PMS234 will be reset to restart the
program execution. The relative timing diagram of watchdog timer is shown as Fig. 13.
VDD
t
SBP
WD
Time Out
Program
Execution
Watch Dog Time Out Sequence
Fig. 13: Sequence of Watch Dog Time Out
©Copyright 2018, PADAUK Technology Co. Ltd
Page 50 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-11. Interrupt
There are six interrupt lines for PMC234/PMS234:
External interrupt PA0
External interrupt PB0
ADC interrupt
Timer16 interrupt
Timer2 interrupt
Comparator interrupt,
Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the
hardware diagram of interrupt function is shown as Fig. 14. All the interrupt request flags are set by
hardware and cleared by writing intrq register. When the request flags are set, it can be rising edge, falling
edge or both, depending on the setting of register integs. All the interrupt request lines are also controlled
by engint instruction (enable global interrupt) to enable interrupt operation and disgint instruction (disable
global interrupt) to disable it. Only FPP0 can accept the interrupt request, other FPP unit will not be
interfered by interrupt.
The stack memory for interrupt is shared with data memory and its address is specified by stack register sp.
Since the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user
can use pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack
memory. Since the stack memory is shared with data memory, user should manipulate the memory using
carefully. By adjusting the memory location of stack point, the depth of stack pointer for every FPP unit
could be fully specified by user to achieve maximum flexibility of system.
Inten.6
Timer2
output
Intrq.6
Inten.4
Intrq.4
Inten.3
Intrq.3
Inten.2
Intrq.2
Inten.1
Intrq.1
Inten.0
Intrq.0
detect
event
Comparator
output
detect
rising
edge
interrupt
to FPP0
ADC output
T16 output
detect
event
detect
rising
edge
engint / disgint
detect
both
edges
PB0
PA0
Note: “engint” and
“disgint” are instructions
detect
both
edges
Fig. 14: Hardware diagram of interrupt controller
Once the interrupt occurs, its operation will be:
The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x10.
During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
Note: Even if INTEN=0, INTRQ will be still triggered by the interrupt source.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 51 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will
be:
The program counter will be restored automatically from the stack memory specified by register sp.
New sp will be updated to sp-2.
Global interrupt will be enabled automatically.
The next instruction will be the original one before interrupt.
User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and
four bytes for two levels interrupt. For interrupt operation, the following sample program shows how to
handle the interrupt, noticing that it needs four bytes stack memory to handle interrupt and pushaf.
void
{
FPPA0
(void)
...
$
INTEN PA0;
// INTEN =1; interrupt request when PA0 level changed
// clear INTRQ
INTRQ
ENGINT
...
=
0;
// global interrupt enable
// global interrupt disable
DISGINT
...
}
void Interrupt (void)
// interrupt service routine
{
PUSHAF
// store ALU and FLAG register
// If INTEN.PA0 will be opened and closed dynamically,
// user can judge whether INTEN.PA0 =1 or not.
// Example: If (INTEN.PA0 && INTRQ.PA0) {…}
// If INTEN.PA0 is always enable,
// user can omit the INTEN.PA0 judgement to speed up interrupt service routine.
If (INTRQ.PA0)
{
// Here for PA0 interrupt service routine
INTRQ.PA0 = 0;
...
// Delete corresponding bit (take PA0 for example)
}
...
// X : INTRQ = 0;
// It is not recommended to use INTRQ = 0 to clear all at the end of
// the interrupt service routine.
// It may accidentally clear out the interrupts that have just
occurred
// and are not yet processed.
POPAF
// restore ALU and FLAG register
}
©Copyright 2018, PADAUK Technology Co. Ltd
Page 52 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-12. Power-Save and Power-Down
There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down
modes. ON mode is the state of normal operation with all functions ON, Power-save mode (“stopexe”) is
the state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is
used to save power deeply. Therefore, Power-save mode is used in the system which needs low operating
power with wake-up occasionally and Power-Down mode is used in the system which needs power down
deeply with seldom wake-up. Table 6 shows the differences in oscillator modules between Power-Save
mode (“stopexe”) and Power-Down mode (“stopsys”).
Differences in oscillator modules between STOPSYS and STOPEXE
IHRC
Stop
ILRC
Stop
EOSC
Stop
STOPSYS
STOPEXE
No Change
No Change
No Change
Table 6: Differences in oscillator modules between STOPSYS and STOPEXE
5-12-1. Power-Save mode (“stopexe”)
Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all
the oscillator modules active. For CPU, it stops executing; however, for Timer16, counter keep counting if
its clock source is not the system clock. The wake-up sources for “stopexe” can be IO-toggle or Timer16
counts to the set values when clock sources of Timer16 come from IHRC, ILRC or EOSC modules.
Wake-up from input pins can be considered as a continuation of normal execution, the detail information
for Power-Save mode shows below:
IHRC and EOSC oscillator modules: No change, keep active if it was enabled
ILRC oscillator modules: must remain enabled, need to start with ILRC when be wakening up
System clock: Disable, therefore, CPU stops execution
OTP memory is turned off
T16/ T2: Stop counting if system clock is selected or the corresponding oscillator module is
disabled; otherwise, it keeps counting.
Wake-up sources: IO toggle in digital mode (PxDIER bit is 1)or Timer16 or Timer2.
The watchdog timer must be disabled before issuing the “stopexe” command, the example is shown as
below:
CLKMD.En_WatchDog
stopexe;
….
=
0;
// disable watchdog timer
// power saving
Wdreset;
CLKMD.En_WatchDog
=
1;
// enable watchdog timer
Another example shows how to use Timer16 to wake-up from “stopexe”:
$ T16M IHRC, /1, BIT8
…
// Timer16 setting
WORD
STT16
stopexe;
…
count
count;
=
0;
The initial counting value of Timer16 is zero and the system will be waken up after the Timer16 counts
256 IHRC clocks.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 53 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-12-2. Power-Down mode (“stopsys”)
Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using
the “stopsys” instruction, this chip will be put on Power-Down mode directly. Before entering Power-Down
mode, the internal low-frequency oscillator (ILRC) must be enabled to wake up the system, that is, before
issuing the stopsys command, the bit 2 of the CLKMD register must be set to 1.The internal low frequency
RC oscillator must be enabled before entering the Power-Down mode, means that bit 2 of register clkmd
(0x03) must be set to high before issuing “stopsys” command in order to resume the system when
wakeup. The following shows the internal status of PMC234/PMS234 in detail when “stopsys” command
is issued:
All the oscillator modules are turned off
Enable internal low RC oscillator (set bit 2 of register clkmd)
OTP memory is turned off
The contents of SRAM and registers remain unchanged
Wake-up sources: IO toggle in digital mode (PxDIER bit is 1).
Wake-up from input pins can be considered as a continuation of normal execution. To minimize power
consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The
reference sample program for power down is shown as below:
CMKMD
=
0xF4;
0;
//
//
Change clock from IHRC to ILRC
disable IHRC
CLKMD.4 =
…
while (1)
{
STOPSYS;
if (…) break;
//
//
//
enter power-down
if wakeup happen and check OK, then return to high speed,
else stay in power-down mode again
}
CLKMD
=
0x34;
//
Change clock from ILRC to IHRC/2
©Copyright 2018, PADAUK Technology Co. Ltd
Page 54 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM
8-bit Controller
5-12-3. Wake-up
After entering the Power-Down or Power-Save modes, the PMC234/PMS234 can be resumed to normal
operation by toggling IO pins, Timer interrupt is available for Power-Save mode ONLY. Table 7 shows the
differences in wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
Yes
Timer Interrupt
STOPSYS
STOPEXE
No
Yes
Yes
Table 7: Differences in wake-up sources between Power-Save mode and Power-Down mode
When using the IO pins to wake-up the PMC234/PMS234, registers padier and pbdier should be
properly set to enable the wake-up function for every corresponding pin. The wake-up time for normal
wake-up is about 1024 ILRC clocks counting from wake-up event; fast wake-up can be selected to
reduce the wake-up time by misc register. For fast wake-up mechanism, the wake-up time is 128 system
clocks from IO toggling if STOPEXE was issued, and 128 system clocks plus oscillator (IHRC or ILRC)
stable time from IO toggling if STOPSYS was issued. The oscillator stable time is the time for IHRC or
ILRC oscillator from power-on, depending on which oscillator is used as system clock source. Please
notice that the fast wake-up will turn off automatically when EOSC is selected as system clock.
System clock
Suspend mode
Wake-up mode
Wake-up time (tWUP) from IO toggle
source
128 * TSYS,
STOPEXE suspend
fast wake-up
IHRC or ILRC
Where TSYS is the time period of system clock
128 TSYS + TSIHRC
;
STOPSYS suspend
STOPSYS suspend
fast wake-up
fast wake-up
fast wake-up
IHRC
ILRC
Where TSIHRC is the stable time of IHRC from
power-on.
128 TSYS + TSILRC
;
Where TSILRC is the stable time of ILRC from
power-on.
STOPSYS or
STOPEXE
suspend
1024 * TILRC
,
EOSC
Where TILRC is the clock period of ILRC
1024 * TILRC
Where TILRC is the clock period of ILRC
1024 * TILRC
Where TILRC is the clock period of ILRC
,
STOPEXE suspend normal wake-up
STOPSYS suspend normal wake-up
Any one
Any one
,
Please notice that the clock source of watch-dog will be switched to system clock (for example: 4MHz)
when fast wakeup is enabled. Therefore, for fast wake-up, recommending turning off the watchdog timer
before enabling the fast wakeup. After wake-up, the watchdog timer is turned on after disabling the fast
wakeup.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 55 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-13. IO Pins
Other than PA5, all the pins can be independently set into two states output or input by configuring the data
registers (pa, pb, pc, pd), control registers (pac, pbc, pcc, pdc) and pull-up registers (paph, pbph, pcph,
pdph). All these pins have Schmitt-trigger input buffer and output driver with CMOS level. When it is set to
output low, the pull-up resistor is turned off automatically. If user wants to read the pin state, please notice
that it should be set to input mode before reading the data port; if user reads the data port when it is set to
output mode, the reading data comes from data register, NOT from IO pad. As an example, Table 6 shows
the configuration table of bit 0 of port A. The hardware diagram of IO buffer is also shown as Fig. 15.
pa.0 pac.0 paph.0
Description
Input without pull-up resistor
X
X
0
1
1
0
0
1
1
1
0
1
X
0
1
Input with pull-up resistor
Output low without pull-up resistor
Output high without pull-up resistor
Output high with pull-up resistor
Table 8: PA0 Configuration Table
RD pull-high latch
WR pull-high latch
D
D
D
Q
(weak P-MOS)
pull-high
latch
Q
Data
latch
Q1
PAD
WR data latch
RD control latch
Q
WR control latch
Control
latch
M
U
X
RD Port
Data Bus
padier.x or pbdier.x
Wakeup module
Interrupt module
(PA0,PB0 only)
Analog Module
Fig. 15: Hardware diagram of IO buffer
PA5 can is open-drain ONLY when setting to output mode (without Q1). The corresponding bits in registers
padier / pbdier should be set to low to prevent leakage current for port A and port B pins which are
selected to be analog function. When PMC234/PMS234 is put in power-down or power-save mode, every
pin can be used to wake-up system by toggling its state. Therefore, those pins needed to wake-up system
must be set to input mode and set the corresponding bits of registers padier and pbdier to high. The same
reason, padier.0 should be set high when PA0 is used as external interrupt pin and pbdier.0 for PB0.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 56 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-14. Reset and LVR
5-14-1. Reset
There are many causes to reset the PMC234/PMS234, once reset is asserted, most of all the registers in
PMC234/PMS234 will be set to default values, When reset comes from WDT timeout, gdio register (IO
address 0x07) keeps the same value, system should be restarted once abnormal cases happen, or by
jumping program counter to address 0x0. The data memory is in uncertain state when reset comes from
power-up and LVR; however, the content will be kept when reset comes from PRST# pin or WDT timeout.
5-14-2. LVR (low voltage reset)
By code option, there are many different levels of LVR for reset . Usually, user selects LVR level to be in
conjunction with operating frequency and supply voltage.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 57 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-15. Comparator
5-15-1. Comparator Hardware Diagram
One comparator is built inside the PMC234/PMS234; Fig. 16 shows its hardware diagram. It can compare
signals between two pins or with either internal reference voltage Vinternal R or internal band-gap reference
voltage. The two signals to be compared, one will be the plus input of comparator and the other one is the
minus input of comparator. For the minus input of comparator, it can be PC0/CIN3-, PC5/CIN4-, Internal
band-gap 1.20 volt, PA3/CIN1-, PA4/CIN2- or Vinternal R selected by bit [3:1] of gpcc register, and for the
plus input of comparator, it can be PC5/CIN+ or Vinternal R selected by bit 0 of gpcc register. The
comparator result can be selected through gpcs.7 to forcibly output to PB0 whatever input or output state.
It can be a direct output or sampled by Timer2 clock (TM2_CLK) which comes from Timer2 module. The
output polarity can be also inverted by setting gpcc.4 register. The comparator output can be used to
request interrupt service or read through gpcc.6.
The comparator is disabled after power-on reset and can be enabled by setting gpcc.7=1, the comparator
module can be put into power-down mode only when issuing stopsys command which will put
PMC234/PMS234 into power-down mode.
16
VDD
gpcs.5=1
gpcs.4=0
gpcs.4=1
gpcs.5=0
MUX
gpcs[3:0]
Vinternal R
gpcc[3:1]
PC0/CIN3-
PC5/CIN4-
Band-gap
000
001 M
gpcc.4
To request interrupt
gpcc.6
010 U
011 X
100
X
O
R
-
PA3/CIN1-
PA4/CIN2-
M
U
X
101
+
D
F
F
To
PB0
0
Timer 2
clock
MUX
1
PC5/CIN+
gpcc.0
TM2_CLK
gpcc.5
gpcs.7
Fig. 16: Hardware diagram of comparator
©Copyright 2018, PADAUK Technology Co. Ltd
Page 58 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-15-2. Analog Inputs
A simplified circuit for the analog inputs is shown in the Fig. 19. All the analog input pins for comparator
are shared function with a digital input which had reverse biased ESD protection diodes to VDD and GND,
therefore, the analog input signal must be between VDD and GND.
Analog Input Pad
VDD
VT ~ 0.7V
RS<10K
RIC~1K
To
Comparator
Input
VT ~ 0.7v
CPIN
~ 4pF
↓
VAI
ILeakage
±400nA
~
Where:
VAI: Voltage of Analog Input
RS: Source Impedance
CPIN: Pin Input Capacitance
RIC: Interconnect Resistance
ILeakage: Leakage Current at Pin
VT: Threshold Voltage
Fig. 17: Analog Input Model of Comparator
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Page 59 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-15-3. Internal reference voltage (Vinternal R
)
The internal reference voltage Vinternal R is built by series resistance to provide different level of reference
voltage, bit 4 and bit 5 of gpcs register are used to select the maximum and minimum values of Vinternal R
and bit [3:0] of gpcs register are used to select one of the voltage level which is deivided-by-16 from the
defined maximum level to minimum level. Fig. 18 to Fig. 21 shows four conditions to have different
reference voltage Vinternal R. By setting the gpcs register, the internal reference voltage Vinternal R can be
ranged from (1/32)*VDD to (3/4)*VDD.
Case 1 : gpcs.5=0 & gpcs.4=0
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/4) VDD ~ (1/4) VDD + (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
4
(n+1)
32
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig. 18: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=0
Case 2 : gpcs.5=0 & gpcs.4= 1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (2/3) VDD ~ (1/24) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
24
Fig. 19: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=1
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Page 60 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
Case 3 : gpcs.5=1 & gpcs.4= 0
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (3/5) VDD ~ (1/5) VDD + (1/40) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
5
(n+1)
40
V internal R
=
*
VDD +
*
VDD, n = gpcs[3:0] in decimal
Fig. 20: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=0
Case 4 : gpcs.5=1 & gpcs.4=1
16 stages
VDD
8R
8R
8R
gpcs.4=0
gpcs.4=1
gpcs.5=1
R
R
R
R
gpcs.5=0
MUX
gpcs[3:0]
V internal R = (1/2) VDD ~ (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
(n+1)
V internal R
=
*
VDD, n = gpcs[3:0] in decimal
32
Fig. 21: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=1
©Copyright 2018, PADAUK Technology Co. Ltd
Page 61 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-15-4. Comparator Interrupt Operation
Interrupt request flag intrq.4 will be set to request interrupt service whenever the rising edge of
comparator output gpcc.6 is detected, this interrupt request flag will be latched until cleared by software
via intrq register. The interrupt service routine handling is similar to other interrupt request lines. The
relative hardware timing diagram is shown as Fig. 22.
gpcc.4
gpcc.6
X
-
O
M
U
X
R
+
D
F
F
Timer 2
clock
TM2_CLK
gpcc.5
(rising edge)
Inten.6
Intrq.6
Inten.4
Intrq.4
Inten.3
Intrq.3
Inten.2
Intrq.2
Inten.1
Intrq.1
Inten.0
Intrq.0
detect
rising edge
to set intrq.4
engint / disgint
Note: “engint ” and
“disgint ” are instructions
Fig. 22: Hardware Diagram of Comparator Interrupt Operation
5-15-5. Synchronizing Comparator Output to Timer2
The comparator output can be synchronized with Timer2 by setting gpcc.5=1. When enabled, the
comparator output is sampled by the rising edge of Timer2 clock source (TM2_CLK). If the pre-scalar
function is used with Timer2, the comparator output is sampled after the pre-scaling and scaling functions,
Please refer to Fig. 11 Timer2 hardware diagram and Fig. 16 Comparator hardware diagram, TM2_CLK
is the clock source after pre-scaling and scaling functions, and will be sent to Timer2 counter for counting
and comparator for sampling clock.
5-15-6. Comparator Response Time
The comparator output is undetermined for a period of time after changing an input source or a new
reference voltage; this period is referred as the response time. Please refer to Section 4-15 and 4-16 the
measurement of comparator responsive time. Typically, the measurement will be based on the compared
voltage level near (VDD-1.5)/2. If the compared voltage level is not within the range, the responsive time
may be longer.
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Page 62 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-15-7. Using the comparator
Case I:
Choosing PC0/CIN3- as minus input and Vinternal R with (18/32)*VDD voltage level as plus input,.
internal R is configured as the above Figure “gpcs[5:4] = 2b’00” and gpcs [3:0] = 4b’1001 (n=9) to
have Vinternal R = (1/4)*VDD + [(9+1)/32]*VDD = [(9+9)/32]*VDD = (18/32)*VDD.
V
gpcs
gpcc
= 0b0_0_00_1001;
= 0b1_0_0_0_000_0;
= 0bxxxx_xxx0;
// Vinternal R = VDD*(18/32)
// enable comp, - input: PC0/CIN3-, + input: Vinternal R
// disable PC0 digital input to prevent leakage current
pbdier
// please refer to section 9.2.1
or
$ GPCS VDD*18/32;
$ GPCC Enable, N_PC0, P_R;
// - input: N_xx,+ input: P_R(Vinternal R)
pbdier
= 0bxxxx_xxx0;
Case 2:
Choosing Vinternal R as minus input with (22/40)*VDD voltage level and PC5/CIN+ as plus input, the
comparator result will be inversed and then output to PB0. Vinternal R is configured as the above
Figure “gpcs[5:4] = 2b’10” and gpcs [3:0] = 4b’1101 (n=13) to have Vinternal R = (1/5)*VDD
[(13+1)/40]*VDD = [(13+9)/40]*VDD = (22/40)*VDD.
+
gpcs
gpcc
= 0b1_0_1_0_1101;
= 0b1_0_0_1_011_1;
= 0bxxxx_xx0x;
// output to PB0, Vinternal R = VDD*(22/40)
// Inverse output, - input: Vinternal R, + input: PC5/CIN+
// disable PA4 digital input to prevent leakage current
pbdier
// please refer to section 9.2.1
or
$ GPCS Output, VDD*22/40;
$ GPCC Enable, Inverse, N_R, P_PC5;
pbdier = 0bxxxx_xx0x;
// - input: N_R(Vinternal R),+ input: P_xx
Note: When PC0 or PC5 is selected as the comparator input, its digital input function is disabled
through the register pbdier.0 or pbdier.1. Therefore, the digital input state of PB0 or PB1 port will
be changed synchronously.
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Page 63 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-15-8. Using the comparator and band-gap 1.20V
The internal band-gap module can provide 1.20 volt, it can measure the external supply voltage level.
The band-gap 1.20 volt is selected as minus input of comparator and Vinternal R is selected as plus input,
the supply voltage of Vinternal R is VDD, the VDD voltage level can be detected by adjusting the voltage
level of Vinternal R to compare with band-gap. If N (gpcs[3:0] in decimal) is the number to let Vinternal R closest
to band-gap 1.20 volt, the supply voltage VDD can be calculated by using the following equations:
For using Case 1: VDD = [ 32 / (N+9) ] * 1.20 volt ;
For using Case 2: VDD = [ 24 / (N+1) ] * 1.20 volt ;
For using Case 3: VDD = [ 40 / (N+9) ] * 1.20 volt ;
For using Case 4: VDD = [ 32 / (N+1) ] * 1.20 volt ;
Case 1:
$ GPCS
$ GPCC
….
VDD*12/40;
// 4.0V * 12/40 = 1.2V
Enable, BANDGAP, P_R; // - input: BANDGAP, + input: P_R(Vinternal R
)
if (GPC_Out)
// or GPCC.6
{
// when VDD﹥4V
}
else
{
}
//
when VDD﹤4V
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Page 64 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-16. LCD Bias Voltage Generator
This function can be enabled by bit 4 of misc register. Those pins which are defined to output VDD/2
voltage are PA3 PA2 PA1 PA0 during input mode, being used as COM function for LCD application. If
user
、
、
、
wants to output VDD VDD/2 GND three levels voltage, the corresponding pins must be set to
、
、
output-high for VDD, enabling VDD/2 bias voltage with input mode for VDD/2, and
correspondingly, Fig. 23 shows how to use this function.
output-low for GND
VDD
VDD/2
GND
Pin set to output high
Pin set to input
Pin set to output low
Fig. 23: Using VDD/2 bias voltage generator
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Page 65 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-17. Analog-to-Digital Conversion (ADC) module
adcm[3:0]
adcc [5:2]
Scalar
and
1001
system clock
PA4/AD9
PA3/AD8
PB7/AD7
PB6/AD6
PB5/AD5
PB4/AD4
PB3/AD3
PB2/AD2
PB1/AD1
PB0/AD0
MUX
1000
ADCCLK
0111
0110
0101
0100
0011
0010
0001
0000
VIN
A/D
Converter
signal for conversion
1111
{adcrh[7:0],adcrl[7:4]} for 12-bit resolution
{adcrh[7:0],adcrl[7:5]} for 11-bit resolution
(adcrh[7:0],adcrl[7:6]) for 10-bit resolution
{adcrh[7:0],adcrl[7]} for 9-bit resolution
{adcrh[7:0]} for 8-bit resolution
band-gap
voltage
generator
Fig. 24: ADC Block Diagram
There are six registers when using the ADC module, which are:
ADC Control Register (adcc)
ADC Mode Register (adcm)
ADC Result High/Low Register (adcrh, adcrl)
Port A/B Digital Input Enable Register (padier, pbdier)
The following steps are recommended to do the AD conversion procedure:
(1) Configure the ADC module:
Select the ADC input channel by adcc register
Select the bit resolution of ADC by adcm register
Configure the AD conversion clock by adcm register
Configure the pin as analog input by padier, pbdier register
Enable the ADC module by adcc register
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Page 66 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
(2) Configure interrupt for ADC: (if desired)
Clear the ADC interrupt request flag in bit 3 of intrq register
Enable the ADC interrupt request in bit 3 of inten register
Enable global interrupt by issuing engint command
(3) Start AD conversion:
Set ADC process control bit in the adcc register to start the conversion (set1 adcc.6).
(4) Wait for the completion flag of AD conversion, by either:
Waiting for the completion flag by using command “wait1 addc.6”; or
Waiting for the ADC interrupt.
(5) Read the ADC result registers:
Read adcrh and adcrl the result registers
(6) For next conversion, goto step 1 or step 2 as required.
5-17-1. The input requirement for AD conversion
For the AD conversion to meet its specified accuracy, the charge holding capacitor (CHOLD) must be
allowed to fully charge to the voltage reference high level and discharge to the voltage reference low
level. The analog input model is shown as Fig. 25, the signal driving source impedance (Rs) and the
internal sampling switch impedance (Rss) will affect the required time to charge the capacitor CHOLD
directly. The internal sampling switch impedance may vary with ADC supply voltage; the signal driving
source impedance will affect accuracy of analog input signal. User must ensure the measured signal is
stable before sampling; therefore, the maximum signal driving source impedance is highly dependent on
the frequency of signal to be measured.
Fig. 25: Analog Input Model
Before starting the AD conversion, the minimum signal acquisition time should be met for the selected
analog input signal. The signal acquisition time (TACQ) of ADC in PMC234/PMS234 series is fixed to one
clock period of ADCLK, the selection of ADCLK must be met the minimum signal acquisition time.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 67 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-17-2. Select the ADC bit resolution
The ADC resolution is 12-bit, please configure adcm register bit [7:5] to be “100” before starting AD
conversion via $ADCM instruction. Higher resolution can detect small signal variation; however, it will
take more time to convert the analog signal to digital signal. The selection can be done via adcm register.
The ADC bit resolution should be configured before starting the AD conversion.
5-17-3. ADC clock selection
The clock of ADC module (ADCLK) can be selected by adcm register; there are 8 possible options for
ADCLK from sysclk/1 to sysclk/128. Due to the signal acquisition time TACQ is one clock period of ADCLK,
the ADCLK must meet that requirement. The recommended ADC clock is to operate at 2us.
5-17-4. AD conversion
The process of AD conversion starts from setting START/DONE bit (bit 6 of adcc) to high, the
START/DONE flag for read will be cleared automatically, then converting analog signal bit by bit and
finally setting START/DONE high to indicate the completion of AD conversion. If ADCLK is selected,
T
ADCLK is the period of ADCLK and the AD conversion time can be calculated as follows:
12-bit resolution: AD conversion time = 17 TADCLK
5-17-5. Configure the analog pins
The 10 analog input signals for ADC shared with Port A[3], Port A[4], and Port B[7:0]. To avoid leakage
current at the digital circuit, those pins defined for analog input should disable the digital input function
(set the corresponding bit of padier or pbdier register to be 0).
The measurement signals of ADC belong to small signal; it should avoid the measured signal to be
interfered during the measurement period, the selected pin should (1) be set to input mode (2) turn off
weak pull-up resistor (3) set the corresponding pin to analog input by port A/B digital input disable
register (padier / pbdier).
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Page 68 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
5-17-6. Using the ADC
The following example shows how to use ADC with PB0~PB3.
First, defining the selected pins:
PBC
PBPH
PBDIER =
=
=
0B_XXXX_0000;
0B_XXXX_0000;
0B_XXXX_0000;
//
//
//
PB0 ~ PB3 as Input
PB0 ~ PB3 without pull-up resistor
PB0 ~ PB3digital input is disabled
Next, setting ADCC register, example as below:
$
$
ADCC
ADCC
Enable, PB3;
Enable, PB0;
//
//
set PB3 as ADC input
set PB0 as ADC input
Next, setting ADCM register, example as below:
$
$
$
$
ADCM
ADCM
ADCM
ADCM
12BIT, /32;
12BIT, /16;
12BIT, /8;
8BIT, /8;
//
//
//
recommend /32 @System Clock=16MHz
recommend /16 @System Clock=8MHz
recommend /8 @System Clock=4MHz
Then, start the ADC conversion:
AD_START
WAIT1
=
1;
//
//
start ADC conversion
wait ADC conversion result
AD_DONE
;
Finally, it can read ADC result when AD_DONE is high:
WORD
Data
Data;
=
//
two bytes result: ADCRH and ADCRL
(ADCRH << 8) | ADCRL;
The ADC can be disabled by using the following method:
ADCC Disable;
$
or
ADCC
=
0;
©Copyright 2018, PADAUK Technology Co. Ltd
Page 69 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6. IO Registers
6-1. ACC Status Flag Register (flag), IO address = 0x00
Bit Reset
R/W
-
Description
7 - 4
3
-
Reserved. These four bits are “1” when reading.
0
R/W
OV (Overflow Flag). This bit is set whenever the sign operation is overflow.
AC (Auxiliary Carry Flag). There are two conditions to set this bit, the first one is carry out
of low nibble in addition operation and the other one is borrow from the high nibble into
low nibble in subtraction operation.
2
0
R/W
C (Carry Flag). There are two conditions to set this bit, the first one is carry out in addition
operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
1
0
0
0
R/W
R/W
Z (Zero Flag). This bit will be set when the result of arithmetic or logic operation is zero;
Otherwise, it is cleared.
6-2. FPP unit Enable Register (fppen), IO address = 0x01
Bit Reset
R/W
-
Description
7 - 2
-
Reserved. Please keep 0 for future compatibility.
1
0
0
1
R/W
R/W
FPP1 enable. This bit is used to enable FPP1. 0 / 1: disable / enable
FPP0 enable. This bit is used to enable FPP0. 0 / 1: disable / enable
6-3. Stack Pointer Register (sp), IO address = 0x02
Bit Reset R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer.
7 - 0 R/W
-
6-4. Clock Mode Register (clkmd), IO address = 0x03
Bit Reset R/W
Description
System clock selection:
Type 0, clkmd[3]=0
Type 1, clkmd[3]=1
000: IHRC/4
001: IHRC/2
000: IHRC/16
001: IHRC/8
010: reserved
011: EOSC/4
100: EOSC/2
101: EOSC
010: reserved
011: IHRC/32
100: IHRC/64
101: EOSC/8
11x: reserved.
7 - 5
111
R/W
110: ILRC/4
111: ILRC (default)
4
3
1
0
R/W Internal High RC Enable. 0 / 1: disable / enable
Clock Type Select. This bit is used to select the clock type in bit [7:5].
RW
0 / 1: Type 0 / Type 1.
Internal Low RC Enable. 0 / 1: disable / enable
R/W
2
1
If ILRC is disabled, watchdog timer is also disabled.
1
0
1
0
R/W Watch Dog Enable. 0 / 1: disable / enable
R/W Pin PA5/RESET# function. 0 / 1: PA5 / RESET#.
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Page 70 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6-5. Interrupt Enable Register (inten), IO address = 0x04
Bit
7
Reset R/W
Description
-
-
Reserved.
R/W Enable interrupt from Timer2. 0 / 1: disable / enable.
Reserved.
6
0
-
5
-
4
0
0
0
0
0
R/W Enable interrupt from comparator. 0 / 1: disable / enable.
R/W Enable interrupt from ADC. 0 / 1: disable / enable.
R/W Enable interrupt from Timer16 overflow. 0 / 1: disable / enable.
R/W Enable interrupt from PB0. 0 / 1: disable / enable.
R/W Enable interrupt from PA0.0 / 1: disable / enable.
3
2
1
0
6-6. Interrupt Request Register (intrq), IO address = 0x05
Bit
Reset R/W
Description
7
-
-
-
-
-
Reserved.
Interrupt Request from Timer2, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
6
5
4
R/W
-
Reserved.
Interrupt Request from comparator output, this bit is set by hardware (rising edge) and
cleared by software. 0 / 1: No request / Request
R/W
Interrupt Request from ADC, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
3
2
1
0
-
-
-
-
R/W
R/W
R/W
R/W
Interrupt Request from Timer16, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PB0, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PA0, this bit is set by hardware and cleared by software.
0 / 1: No Request / request
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Page 71 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6-7. Timer16 mode Register (t16m), IO address = 0x06
Bit
Reset R/W
Description
Timer Clock source selection.
000: disable
001: system clock (CLK)
010: reserved
7 - 5
000
R/W 011: reserved
100: IHRC
101: EOSC
110: ILRC
111: PA0 falling edge (from external pin)
Timer16 clock pre-divider.
00: /1
4 - 3
00
R/W 01: /4
10: /16
11: /64
Interrupt source selection. Interrupt event happens when selected bit goes high.
0 : bit 8 of Timer16
1 : bit 9 of Timer16
2 : bit 10 of Timer16
2 - 0
000
R/W 3 : bit 11 of Timer16
4 : bit 12 of Timer16
5 : bit 13 of Timer16
6 : bit 14 of Timer16
7 : bit 15 of Timer16
6-8. General Data register for IO (gdio), IO address = 0x07
Bit
Reset R/W
Description
General data for IO. This port is the general data buffer in IO space and cleared when
POR or LVR, and it will KEEP the old values when reset from watch dog time out. It can
7 - 0
00
R/W perform the IO operation, like wait0 gdio.x, wait1 gdio.x and tog gdio.x to replace of
operations which instructions are supported in memory space (ex: wait1 mem; wait0
mem; tog mem).
6-9. External Oscillator setting Register (eoscr), IO address = 0x0a
Bit
Reset R/W
Description
7
0
WO Enable external crystal oscillator. 0 / 1 : Disable / Enable
External crystal oscillator selection.
00 : Reserved
6 - 5
00
WO 01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
4 - 1
0
-
-
Reserved. Please keep 0 for future compatibility.
0
WO Power-down the Band-gap and LVR hardware modules. 0 / 1: normal / power-down.
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Page 72 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6-10. Internal High RC oscillator control Register (ihrcr), IO address = 0x0b
Bit
Reset R/W
Description
Bit [7:0] for frequency calibration of IHRC. 0x00 for lowest frequency and 0xff for highest
frequency.
7 - 0
00 WO
6-11. Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
Reset R/W
Description
7 - 5
-
-
Reserved.
Timer16 edge selection.
4
0
WO 0 : rising edge of the selected bit to trigger interrupt
1 : falling edge of the selected bit to trigger interrupt
PB0 edge selection.
00 : both rising edge and falling edge of the selected bit to trigger interrupt
WO 01 : rising edge of the selected bit to trigger interrupt
10 : falling edge of the selected bit to trigger interrupt
11 : reserved.
3 - 2
00
00
PA0 edge selection.
00 : both rising edge and falling edge of the selected bit to trigger interrupt
WO 01 : rising edge of the selected bit to trigger interrupt
10 : falling edge of the selected bit to trigger interrupt
11 : reserved.
1 - 0
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Page 73 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6-12. Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset R/W
Description
Enable PA7 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA7 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PA6 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA6 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PA5 wake-up event. 1 / 0 : enable / disable.
7
1
WO
6
5
4
1
1
1
WO
WO
WO
This bit can be set to low to disable wake-up from PA5 toggling.
Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.
Enable PA4 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PA4 is assigned as AD input to prevent leakage
current. If this bit is set to low, PA4 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PA3 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PA3 is assigned as AD input to prevent leakage
current. If this bit is set to low, PA3 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PA2 wake-up event. 1 / 0 : enable / disable.
3
1
WO
2
1
1
1
WO
WO
This bit can be set to low to disable wake-up from PA2 toggling.
Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.
Enable PA1 wake-up event. 1 / 0 : enable / disable.
This bit can be set to low to disable wake-up from PA1 toggling.
Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.
Enable PA0 wake-up event and interrupt request. 1 / 0 : enable / disable.
This bit can be set to low to disable wake-up from PA0 toggling and interrupt request
from this pin.
0
1
WO
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
6-13. Port B Digital Input Enable Register (pbdier), IO address = 0x0e
Bit
Reset R/W
Description
Enable PB7~PB0 digital input to prevent leakage when the pin is assigned for AD input.
When disable is selected, the wakeup function from this pin is also disabled.
0 / 1 : disable / enable
7 - 0
0xff
WO
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
6-14. Port A Data Register (pa), IO address = 0x10
Bit
Reset R/W
R/W Data register for Port A.
Description
7 - 0
-
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12-bit ADC Enhanced FPPATM Controller
6-15. Port A Control Register (pac), IO address = 0x11
Bit
Reset R/W
Description
Port A control registers. This register is used to define input mode or output mode for
each corresponding pin of port A. 0 / 1: input / output
7 - 0
0x00
R/W
Please note that PA5 can be INPUT or OUTPUT LOW ONLY, the output state will be tri-
state when PA5 is programmed into output mode with data 1.
6-16. Port A Pull-up Register (paph), IO address = 0x12
Bit
Reset R/W
Description
Port A pull-up register. This register is used to enable the internal pull-up device on each
7 - 0 0x00 R/W corresponding pin of port A and this pull high function is active only for input mode.
0 / 1 : disable / enable. Please note that PA5 does NOT have pull-up resistor.
6-17. Port B Data Register (pb), IO address = 0x14
Bit
Reset R/W
R/W Data register for Port B.
Description
7 - 0
-
6-18. Port B Control Register (pbc), IO address = 0x15
Bit
Reset R/W
Description
Port B control register.
7 - 0
0x00
R/W This register is used to define input mode or output mode for each corresponding pin of
port B. 0 / 1: input / output
6-19. Port B Pull-up Register (pbph), IO address = 0x16
Bit
Reset R/W
Description
Port B pull-up register.
7 - 0 0x00 R/W This register is used to enable the internal pull-up device on each corresponding pin of
port B. 0 / 1 : disable / enable
6-20. Port C Data Register (pc), IO address = 0x17
Bit
Reset R/W
R/W Bit [7:0] of data register for Port C.
Description
7 - 0
-
6-21. Port C Control Register (pcc), IO address = 0x18
Bit
Reset R/W
Description
Bit [7:0] of port C control register.
7 - 0
0x00
R/W This register is used to define input mode or output mode for each corresponding pin.
0 / 1: input / output
6-22. Port C Pull-up Register (pcph), IO address = 0x19
Bit
Reset R/W
Description
Bit [7:0] of Port C pull-up register.
7 - 0 0x00 R/W This register is used to enable the internal pull-up device on each corresponding pin.
0 / 1 : disable / enable
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PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6-23. Port D Data Register (pd), IO address = 0x1a
Bit
Reset R/W
Description
7 - 2
1 - 0
-
-
-
Reserved
R/W Bit [1:0] of data register for Port D.
6-24. Port D Control Register (pdc), IO address = 0x1b
Bit
Reset R/W
Description
7 - 2
-
-
Reserved
Bit [1:0] of port D control register.
1 - 0
00
R/W This register is used to define input mode or output mode for each corresponding pin.
0 / 1: input / output
6-25. Port D Pull-up Register (pdph), IO address = 0x1c
Bit
Reset R/W
Description
7- 2
-
-
Reserved
Bit [1:0] of Port D pull-up register.
1 - 0
00
R/W This register is used to enable the internal pull-up device on each corresponding pin.
0 / 1 : disable / enable
6-26. ADC Control Register (adcc), IO address = 0x20
Bit Reset R/W
Description
7
0
-
R/W Enable ADC function. 0/1: Disable/Enable.
ADC process control bit.
Write “1” to start AD conversion, and the flag is cleared automatically when starting the
6
R/W
AD conversion ;
Read “1” to indicate the completion of AD conversion and “0” is in progressing.
Channel selector. These four bits are used to select input signal for AD conversion.
0000: PB0/AD0,
0001: PB1/AD1,
0010: PB2/AD2,
0011: PB3/AD3,
0100: PB4/AD4,
5 - 2 0000 R/W 0101: PB5/AD5,
0110: PB6/AD6,
0111: PB7/AD7
1000: PA3/AD8
1001: PA4/AD9
1111: band-gap 1.20 volt reference voltage
Others: reserved
1 - 0
-
-
Reserved. (keep 0 for future compatibility)
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6-27. ADC Mode Register (adcm), IO address = 0x21
Bit Reset
R/W
Description
Bit Resolution.
7 - 5
4
000
-
WO 100:12-bit, AD 12-bit result [11:0] = { adcrh[7:0], adcrl[7:4] }.
Others: reserved,
-
Reserved (keep 0 for future compatibility)
ADC clock source selection.
000: sysclk/1,
001: sysclk/2,
010: sysclk/4,
3 - 1
000
WO 011: sysclk/8,
100: sysclk/16,
101: sysclk/32,
110: sysclk/64,
111: sysclk/128,
0
-
-
Reserved
6-28. ADC Result High Register (adcrh), IO address = 0x22
Bit Reset
R/W
Description
These eight read-only bits will be the bit [11:4] of AD conversion result. The bit 7 of this
register is the MSB of ADC result for any resolution.
7- 0
-
RO
6-29. ADC Result Low Register (adcrl), IO address = 0x23
Bit Reset
R/W
RO
-
Description
These four bits will be the bit [3:0] of AD conversion result.
Reserved
7 - 4
3 - 0
-
-
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6-30. Miscellaneous Register (misc), IO address = 0x3b
Bit Reset
R/W
Description
7
6
0
0
-
Reserved
Enable extremely low current for 32KHz crystal oscillator AFTER oscillation.
WO 0: Normal.
1: Low driving current for 32KHz crystal oscillator.
Enable fast Wake-up. Fast wake-up is NOT supported when EOSC is enabled.
0: Normal wake-up.
The wake-up time is 1024 ILRC clocks
1: Fast wake-up. (for
The wake-up time is 128 CLKs (system clock) + oscillator stable time.
If wake-up from STOPEXE suspend, there is no oscillator stable time;
If wake-up from STOPSYS suspend, it will be IHRC or ILRC stable time from
power-on.
5
0
WO
Please notice that the clock source of watch-dog will be switched to system clock (for
example: 4MHz) when fast wakeup is enabled. Therefore, for fast wake-up,
recommending turning off the watchdog timer before enabling the fast wakeup. After
wake-up, turning on the watchdog timer after disabling the fast wakeup.
Enable to generate half VDD on PA0/PA1/PA2/PA3 pins.
0 / 1 : Disable / Enable
4
3
2
0
0
0
WO
Recover time from LVR.
WO 0: Normal. The system will take about 1024 ILRC clocks to boot up from LVR.
1: Fast. The system will take about 64 ILRC clocks to boot up from LVR.
Disable LVR function.
WO
0 / 1 : Enable / Disable
Watch dog time out period
00: 2048 ILRC clock period
1 - 0
00
WO 01: 4096 ILRC clock period
10: 16384 ILRC clock period
11: 256 ILRC clock period
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6-31. Timer2 Control Register (tm2c), IO address = 0x3c
Bit Reset
R/W
Description
Timer2 clock selection.
0000 : disable
0001 : system clock
0010 : internal high RC oscillator (IHRC)
0011 : reserved
0100 : ILRC
0101 : comparator output
011x : reserved
7 - 4
0000
R/W
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PA3 (rising edge)
1011 : ~PA3 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2
does NOT be stopped, Timer2 will keep counting when ICE is in halt state.
Timer2 output selection.
00 : disable
3 - 2
00
R/W 01 : PA2
10 : PA3
11 : PA1
Timer2 mode selection.
1
0
0
0
R/W
R/W
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer2 output.
0 / 1: disable / enable.
6-32. Timer2 Counter Register (tm2ct), IO address = 0x3d
Bit Reset
7 - 0 0x00
R/W
Description
R/W Bit [7:0] of Timer2 counter register.
6-33. Timer2 Scalar Register (tm2s), IO address = 0x37
Bit Reset
R/W
Description
PWM resolution selection.
7
0
WO 0 : 8-bit
1 : 6-bit
Timer2 clock pre-scalar.
00 : ÷ 1
WO 01 : ÷ 4
10 : ÷ 16
6 - 5
00
11 : ÷ 64
4 - 0 00000 WO Timer2 clock scalar.
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
6-34. Timer2 Bound Register (tm2b), IO address = 0x09
Bit Reset
7 - 0 0x00
R/W
Description
WO
Timer2 bound register.
6-35. Comparator Control Register (gpcc), IO address = 0x3e
Bit Reset
R/W
Description
Enable comparator.
0 / 1 : disable / enable
7
0
R/W
When this bit is set to enable, please also set the corresponding analog input pins to
be digital disable to prevent IO leakage.
Comparator result of comparator.
0: plus input < minus input
6
5
4
-
RO
R/W
R/W
1: plus input > minus input
Select whether the comparator result output will be sampled by TM2_CLK?
0: result output NOT sampled by TM2_CLK
1: result output sampled by TM2_CLK
Inverse the polarity of result output of comparator.
0: polarity is NOT inversed.
0
0
1: polarity is inversed.
Selection the minus input (-) of comparator.
000 : PC0/CIN3-
001 : PC5/CIN+
3 - 1
000
R/W
R/W
010 : Internal 1.20 volt band-gap reference voltage
011 : Vinternal R
100 : PA3/CIN1-
101 : PA4/CIN2-
Selection the plus input (+) of comparator.
0 : Vinternal R
0
0
1 : PC5/CIN+
6-36. Comparator Selection Register (gpcs), IO address = 0x22
Bit
Reset
R/W
WO
-
Description
Comparator output enable (to PB0).
0 / 1 : disable / enable
Reserved.
7
0
6
5
4
-
0
0
WO Selection of high range of comparator.
WO Selection of low range of comparator.
Selection the voltage level of comparator.
3 - 0
0000
WO
0000 (lowest) ~ 1111 (highest)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 80 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
7. Instructions
Symbol
Description
ACC
a
Accumulator (ACC is the shorthand of accumulator)
Accumulator (a is symbol of accumulator in program)
sp
flag
I
Stack pointer
ACC status flag register
Immediate data
&
Logical AND
|
Logical OR
←
^
Movement
Exclusive logic OR
+
Add
-
〜
〒
OV
Z
Subtraction
NOT (logical complement, 1’s complement)
NEG (2’s complement)
Overflow (The operational result is out of range in signed 2’s complement number system)
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction in
unsigned number system)
C
AC
Auxiliary Carry
(If there is a carry out from low nibble after the result of ALU operation, this bit is set to 1)
Program counter for FPP0
pc0
pc1
Program counter for FPP1
7-1. Data Transfer Instructions
mov
mov
mov
a, I
Move immediate data into ACC.
Example: mov a, 0x0f;
Result: a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
M, a
a, M
Move data from ACC into memory
Example: mov
MEM, a;
Result: MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
Result: a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, MEM ;
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
mov
mov
nmov
a, IO
IO, a
M, a
Move data from IO into ACC
Example: mov a, pa ;
Result: a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Move data from ACC into IO
Example: mov
Result: pb ← a
pb, a;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Take the negative logic (2’s complement) of ACC to put on memory
Example: mov
MEM, a;
Result: MEM ← 〒a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
a, 0xf5 ;
ram9, a;
// ACC is 0xf5
nmov
// ram9 is 0x0b, ACC is 0xf5
------------------------------------------------------------------------------------------------------------------------
Take the negative logic (2’s complement) of memory to put on ACC
nmov
a, M
Example: mov
a, MEM ;
Result: a ← 〒MEM; Flag Z is set when 〒MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
nmov
a, 0xf5 ;
ram9, a ;
a, ram9 ;
// ram9 is 0xf5
// ram9 is 0xf5, ACC is 0x0b
------------------------------------------------------------------------------------------------------------------------
Load high byte data in OTP program memory to ACC by using index as OTP address. It needs
2T to execute this instruction.
ldtabh index
Example: ldtabh index;
Result:
a ← {bit 15~8 of OTP [index]};
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
...
ROMptr ;
// declare a pointer of ROM in RAM
mov
mov
mov
mov
...
a, la@TableA ; // assign pointer to ROM TableA (LSB)
lb@ROMptr, a ; // save pointer to RAM (LSB)
a, ha@TableA ; // assign pointer to ROM TableA (MSB)
hb@ROMptr, a ; // save pointer to RAM (MSB)
ldtabh
...
ROMptr ;
// load TableA MSB to ACC (ACC=0X02)
TableA :
dc
0x0234, 0x0042, 0x0024, 0x0018 ;
------------------------------------------------------------------------------------------------------------------------
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
ldtabl index
Load low byte data in OTP to ACC by using index as OTP address. It needs 2T to execute this
instruction.
Example: ldtabl index;
Result:
a ← {bit7~0 of OTP [index]};
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
...
ROMptr ;
// declare a pointer of ROM in RAM
mov
mov
mov
mov
...
a, la@TableA ; // assign pointer to ROM TableA (LSB)
lb@ROMptr, a ; // save pointer to RAM (LSB)
a, ha@TableA ; // assign pointer to ROM TableA (MSB)
hb@ROMptr, a ; // save pointer to RAM (MSB)
ldtabl
...
ROMptr ;
// load TableA LSB to ACC (ACC=0x34)
TableA :
dc 0x0234, 0x0042, 0x0024, 0x0018 ;
------------------------------------------------------------------------------------------------------------------------
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
ldt16 word
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
...
T16val ;
// declare a RAM word
clear
clear
stt16
...
lb@ T16val ; // clear T16val (LSB)
hb@ T16val ; // clear T16val (MSB)
T16val ;
// initial T16 with 0
set1
...
t16m.5 ;
// enable Timer16
set0
ldt16
...
t16m.5 ;
T16val ;
// disable Timer16
// save the T16 counting value to T16val
------------------------------------------------------------------------------------------------------------------------
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
stt16 word
Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
...
T16val ;
// declare a RAM word
mov
mov
mov
mov
stt16
...
a, 0x34 ;
lb@ T16val , a ; // move 0x34 to T16val (LSB)
a, 0x12 ;
hb@ T16val , a ; // move 0x12 to T16val (MSB)
T16val ;
// initial T16 with 0x1234
----------------------------------------------------------------------------------------------------------------------
xch
M
Exchange data between ACC and memory
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
idxm a, index Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------
word
...
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
...
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an addr.(MSB), be 0
// save pointer to RAM (MSB)
hb@RAMIndex, a ;
idxm
a, RAMIndex ;
// move data in address 0x5B to ACC
------------------------------------------------------------------------------------------------------------------------
Idxm index, a Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
...
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
...
a, 0x5B ;
// assign pointer to an address (LSB)
lb@RAMIndex, a ; // save pointer to RAM (LSB)
a, 0x00 ; // assign 0x00 to an addr.(MSB), be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
mov
idxm
a, 0xA5 ;
RAMIndex, a ;
// mov 0xA5 to memory in address 0x5B
------------------------------------------------------------------------------------------------------------------------
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
pushaf
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
.romadr 0x10 ;
// ISR entry address
pushaf ;
...
// put ACC and flag into stack memory
// ISR program
...
// ISR program
popaf ;
reti ;
// restore ACC and flag from stack memory
------------------------------------------------------------------------------------------------------------------------
Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
popaf
Result:
sp ← sp - 2
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
;
7-2. Arithmetic Operation Instructions
add
a, I
Add immediate data with ACC, then put result into ACC
Example: add a, 0x0f ;
Result: a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
add
a, M
Add data in memory with ACC, then put result into ACC
Example: add
Result: a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, MEM ;
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
add
M, a
Add data in memory with ACC, then put result into memory
Example: add
MEM, a;
Result: MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc a, M
Add data in memory with ACC and carry bit, then put result into ACC
Example: addc
a, MEM ;
Result: a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc M, a
Add data in memory with ACC and carry bit, then put result into memory
Example: addc
MEM, a ;
Result: MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc
addc
a
Add carry with ACC, then put result into ACC
Example: addc
a ;
Result: a ← a + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Add carry with memory, then put result into memory
Example: addc
MEM ;
Result: MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
nadd a, M
Add negative logic (2’s complement) of ACC with memory
Example: nadd
a, MEM ;
Result: a ← 〒a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
nadd M, a
Add negative logic (2’s complement) of memory with ACC
Example: nadd
MEM, a ;
Result: MEM ← 〒MEM + a
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sub
sub
a, I
Subtraction immediate data from ACC, then put result into ACC.
Example: sub
a, 0x0f;
Result: a ← a – 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
Subtraction data in memory from ACC, then put result into ACC
Example: sub
Result: a ← a – MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, MEM ;
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PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
sub
M, a
Subtraction data in ACC from memory, then put result into memory
Example: sub
MEM, a;
Result: MEM ← MEM – a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc a, M
Subtraction data in memory and carry from ACC, then put result into ACC
Example: subc
a, MEM;
Result: a ← a – MEM – C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc M, a
Subtraction ACC and carry bit from memory, then put result into memory
Example: subc
MEM, a ;
Result: MEM ← MEM – a – C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc
subc
inc
a
Subtraction carry from ACC, then put result into ACC
Example: subc
a;
Result: a ← a – C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Subtraction carry from the content of memory, then put result into memory
Example: subc
MEM;
Result: MEM ← MEM – C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment the content of memory
Example: inc
MEM ;
Result: MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dec
M
Decrement the content of memory
Example: dec
MEM;
Result: MEM ← MEM – 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
clear
M
Clear the content of memory
Example: clear
Result: MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
MEM ;
©Copyright 2018, PADAUK Technology Co. Ltd
Page 87 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
7-3. Shift Operation Instructions
sr
a
Shift right of ACC
Example: sr a ;
Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of ACC with carry
src
sr
a
Example: src a ;
Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory
M
Example: sr MEM ;
Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of memory with carry
src
sl
M
Example: src MEM ;
Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC
a
Example: sl a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC with carry
slc
sl
a
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory
M
Example: sl MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry
slc
M
Example: slc MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC
swap
swap
a
Example: swap
a ;
Result: a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
M
Swap the high nibble and low nibble of memory
Example: swap
MEM ;
Result: MEM (b3,b2,b1,b0,b7,b6,b5,b4) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 88 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
7-4. Logic Operation Instructions
and
and
and
or
a, I
a, M
M, a
a, I
Perform logic AND on ACC and immediate data, then put result into ACC
Example: and a, 0x0f ;
Result: a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC
Example: and
a, RAM10 ;
Result: a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory
Example: and
MEM, a ;
Result: MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and immediate data, then put result into ACC
Example: or
a, 0x0f ;
Result: a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
a, M
Perform logic OR on ACC and memory, then put result into ACC
Example: or
a, MEM ;
Result: a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
M, a
a, I
Perform logic OR on ACC and memory, then put result into memory
Example: or
MEM, a ;
Result: MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
xor
xor
xor
Perform logic XOR on ACC and immediate data, then put result into ACC
Example: xor
a, 0x0f ;
Result: a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, IO
Perform logic XOR on ACC and IO register, then put result into ACC
Example: xor
a, pa ;
Result: a ← a ^ pa ; // pa is the data register of port A
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
Perform logic XOR on ACC and IO register, then put result into IO register
Example: xor
Result: pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
pa, a ;
©Copyright 2018, PADAUK Technology Co. Ltd
Page 89 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
xor
xor
not
a, M
M, a
a
Perform logic XOR on ACC and memory, then put result into ACC
Example: xor
a, MEM ;
Result: a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform 1’s complement (logical complement) of ACC
Example: not
a ;
Result: a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
not
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC7
------------------------------------------------------------------------------------------------------------------------
Perform 1’s complement (logical complement) of memory
not
M
Example: not
MEM ;
Result: MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC7
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of ACC
neg
a
Example: neg
a;
Result: a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
neg
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC8
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of memory
neg
M
Example: neg
Result: MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
MEM;
©Copyright 2018, PADAUK Technology Co. Ltd
Page 90 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
neg
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC8
------------------------------------------------------------------------------------------------------------------------
Compare ACC with immediate data
comp
a, I
Example: comp
a, 0x55;
Result: Flag will be changed by regarding as ( a - 0x55 )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
a, 0x38 ;
a, 0x38 ;
a, 0x42 ;
a, 0x24 ;
a, 0x6a ;
comp
comp
comp
comp
// Z flag is set
// C flag is set
// C, Z flags are clear
// C, AC flags are set
------------------------------------------------------------------------------------------------------------------------
Compare ACC with the content of memory
comp
a, M
Example: comp
a, MEM;
Result: Flag will be changed by regarding as ( a - MEM )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
comp
mov
mov
mov
comp
a, 0x38 ;
mem, a ;
a, mem ;
a, 0x42 ;
mem, a ;
a, 0x38 ;
a, mem ;
// Z flag is set
// C flag is set
------------------------------------------------------------------------------------------------------------------------
Compare ACC with the content of memory
comp
M, a
Example: comp
MEM, a;
Result: Flag will be changed by regarding as ( MEM - a )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 91 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
7-5. Bit Operation Instructions
set0 IO.n
Set bit n of IO port to low
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
set1 IO.n
Set bit n of IO port to high
Example: set1 pb.5 ;
Result: set bit 5 of port B to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
tog IO.n
Toggle bit state of bit n of IO port
Example: tog pa.5 ;
Result: toggle bit 5 of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
set0 M.n
set1 M.n
swapc IO.n
Set bit n of memory to low
Example: set0 MEM.5 ;
Result: set bit 5 of MEM to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to high
Example: set1 MEM.5 ;
Result: set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Swap the nth bit of IO port with carry bit
Example: swapc
IO.0;
Result: C ← IO.0 , IO.0 ← C
When IO.0 is a port to output pin, carry C will be sent to IO.0;
When IO.0 is a port from input pin, IO.0 will be sent to carry C;
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Application Example1 (serial output) :
------------------------------------------------------------------------------------------------------------------------
...
set1
...
pac.0 ;
// set PA.0 as output
set0
swapc
set1
swapc
...
flag.1 ;
pa.0 ;
// C=0
// move C to PA.0 (bit operation), PA.0=0
// C=1
flag.1 ;
pa.0 ;
// move C to PA.0 (bit operation), PA.0=1
©Copyright 2018, PADAUK Technology Co. Ltd
Page 92 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
------------------------------------------------------------------------------------------------------------------------
Application Example2 (serial input) :
------------------------------------------------------------------------------------------------------------------------
...
set0
...
pac.0 ;
// set PA.0 as input
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift C to bit 7 of ACC
swapc
src
pa.0 ;
a ;
// read PA.0 to C (bit operation)
// shift new C to bit 7, old C
...
------------------------------------------------------------------------------------------------------------------------
7-6. Conditional Operation Instructions
ceqsn a, I
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a - I)
Example: ceqsn
a, 0x55 ;
MEM ;
inc
goto
error ;
Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
ceqsn a, M
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
Example: ceqsn
a, MEM;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
ceqsn M, a
cneqsn a, M
Compare ACC with memory and skip next instruction if both are equal.
Example: ceqsn
MEM, a;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are not equal.
Flag will be changed like as (a ← a - M)
Example: cneqsn
a, MEM;
Result: If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 93 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
cneqsn a, I
Compare ACC with immediate data and skip next instruction if both are no equal.
Flag will be changed like as (a ← a - I)
Example: cneqsn
a,0x55 ;
MEM ;
error ;
inc
goto
Result: If a≠0x55, then “goto error”; Otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Check IO bit and skip next instruction if it’s low
t0sn IO.n
t1sn IO.n
t0sn M.n
t1sn M.n
Example: t0sn
pa.5;
Result: If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check IO bit and skip next instruction if it’s high
Example: t1sn
pa.5 ;
Result: If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s low
Example: t0sn MEM.5 ;
Result: If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high
EX: t1sn MEM.5 ;
Result: If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Increment ACC and skip next instruction if ACC is zero
izsn
dzsn
izsn
dzsn
a
Example: izsn
Result:
a;
a
←
a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a
Decrement ACC and skip next instruction if ACC is zero
Example: dzsn
Result:
a;
A
←
A - 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment memory and skip next instruction if memory is zero
Example: izsn
Result: MEM
MEM;
MEM + 1, skip next instruction if MEM= 0
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Decrement memory and skip next instruction if memory is zero
Example: dzsn
Result: MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
MEM;
←
MEM - 1, skip next instruction if MEM = 0
©Copyright 2018, PADAUK Technology Co. Ltd
Page 94 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
Wait here until bit n of IO port is low.
Example: wait0 pa.5;
wait0 IO.n
wait1 IO.n
Result:
Wait bit 5 of port A low to execute next instruction;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Wait here until bit n of IO port is low.
Example: wait1 pa.5;
Result:
Wait bit 5 of port A high to execute next instruction;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
7-7. System control Instructions
call
label
Function call, address can be full range address space
Example: call
function1;
pc + 1
Result: [sp]
←
pc
sp
←
←
function1
sp + 2
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
goto label
Go to specific address which can be full range address space
Example: goto
error;
Result: Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Delay the (N+1) cycles which N is specified by the content of ACC, the timing is based on the
executing FPP unit. After the delay instruction is executed, the ACC will be zero.
delay
a
Example: delay
a;
Result: Delay 16 cycles here if ACC=0fh
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Note: Because ACC is the temporarily buffer for counting, please make sure that it will not be
interrupted when executing this instruction. Otherwise, it may be not the expected delay time.
Delay the (N+1) cycles which N is specified by the immediate data, the timing is based on the
delay
I
executing FPP unit. After the delay instruction is executed, the ACC will be zero.
Example: delay
0x05;
Result: Delay 6 cycles here
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Note: Because ACC is the temporarily buffer for counting, please make sure that it will not be
interrupted when executing this instruction. Otherwise, it may be not the expected delay time.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 95 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
Delay the (N+1) cycles which N is specified by the content of memory, the timing is based on
the executing FPP unit. After the delay instruction is executed, the ACC will be zero.
delay
M
Example: delay
M;
Result: Delay 256 cycles here if M=ffh
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Note: Because ACC is the temporarily buffer for counting, please make sure that it will not be
interrupted when executing this instruction. Otherwise, it may be not the expected delay time.
Place immediate data to ACC, then return
ret
ret
I
Example: ret 0x55;
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program which had function call
Example: ret;
Result:
sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
reti
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
nop
No operation
Example: nop;
Result: nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
pcadd
a
Next program counter is current program counter plus ACC.
Example: pcadd a;
Result: pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
...
mov
pcadd
goto
goto
goto
goto
...
a, 0x02 ;
a ;
// PC <- PC+2
// jump here
err1 ;
correct ;
err2 ;
err3 ;
correct:
...
------------------------------------------------------------------------------------------------------------------------
// jump here
©Copyright 2018, PADAUK Technology Co. Ltd
Page 96 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
engint
Enable global interrupt enable
Example: engint;
Result: Interrupt request can be sent to FPP0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
disgint
stopsys
Disable global interrupt enable
Example: disgint ;
Result: Interrupt request is blocked from FPP0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
System halt.
Example: stopsys;
Result: Stop the system clocks and halt the system
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
stopexe
CPU halt. The oscillator modes is still active to output clock, however, system clock is disabled
to save power.
Example: stopexe;
Result: Stop the system clocks and keep oscillator modes active.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
reset
Reset the whole chip, its operation will be same as hardware reset.
Example: reset;
Result: Reset the whole chip.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
wdreset
Reset Watchdog timer.
Example: wdreset ;
Result: Reset Watchdog timer.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
7-8. Summary of Instructions Execution Cycle
Differences in commend timing between single / double FPPA mode:
Instruction
Condition
1 FPPA
2T
2 FPPA
1T
goto, call
Condition is fulfilled
2T
1T
ceqsn, cneqsn, t0sn, t1sn, dzsn,
izsn
Condition is not fulfilled
1T
1T
ldtabh, ldtabl, idxm, pcadd, ret, reti
Others
2T
2T
1T
1T
©Copyright 2018, PADAUK Technology Co. Ltd
Page 97 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
7-9. Summary of affected flags by Instructions
Instruction
mov a, I
Z
-
C
-
AC OV Instruction
Z
-
C
-
AC OV Instruction
Z
Y
-
C
-
AC OV
-
-
-
-
-
-
-
-
-
-
mov M, a
mov IO, a
ldtabh index
stt16 word
idxm index,
add a, I
-
-
-
-
mov a, M
nmov M, a
ldtabl
-
-
-
-
-
-
-
-
mov a, IO
nmov a, M
ldt16 word
idxm a, index
popaf
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
xch
M
-
-
-
-
-
-
-
-
pushaf
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, M
addc M, a
nadd a, M
sub a, M
subc M, a
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add M, a
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
addc a, M
addc
a
addc
M
nadd M, a
sub M, a
sub a, I
subc a, M
subc
dec
src
a
subc
clear
M
M
inc
sr a
src
sl
M
M
a
sr
M
-
Y
Y
-
-
-
M
-
-
-
sl
a
-
-
-
slc
a
-
-
-
M
-
-
-
slc
and
M
-
-
-
swap
and
a
-
-
-
swap
and
M
-
-
-
a, I
Y
Y
Y
Y
Y
Y
-
-
-
a, M
Y
Y
Y
Y
Y
Y
-
-
-
-
M, a
Y
Y
-
-
-
-
or a, I
-
-
-
or a, M
-
-
-
or M, a
-
-
-
xor
a, I
-
-
-
xor a, IO
-
-
-
xor IO, a
-
-
-
xor
a, M
M
-
-
-
xor
M, a
-
-
-
not
a
Y
Y
Y
-
-
-
-
-
-
not
-
-
-
neg
a
-
-
Y
-
-
Y
-
neg
M
-
comp
a, I
Y
-
Y
-
Y
-
comp
a,
Y
-
comp
M,
Y
-
Y
-
Y
-
set0 IO.n
set0 M.n
ceqsn a, I
cneqsn a, M
t1sn IO.n
set1 IO.n
set1 M.n
tog IO.n
-
-
-
-
-
-
-
-
swapc
-
Y
Y
-
-
-
Y
Y
-
Y
Y
-
Y
Y
ceqsn a, M
cneqsn a, I
t0sn M.n
Y
Y
-
Y
Y
-
Y
Y
Y
Y
ceqsn M, a
t0sn IO.n
t1sn M.n
Y
-
Y
-
Y
-
Y
Y
-
Y
Y
-
-
Y
Y
-
-
-
-
-
-
-
izsn
dzsn
call
a
Y
Y
-
Y
Y
-
dzsn
a
Y
-
Y
-
Y
-
Y
-
izsn
wait1 IO.n
delay
M
Y
-
Y
-
Y
-
Y
-
M
wait0 IO.n
goto label
label
I
-
-
-
-
a
-
-
-
-
delay
ret
-
-
-
-
delay
reti
M
-
-
-
-
ret
I
-
-
-
-
-
-
-
-
-
-
-
-
nop
-
-
-
-
pcadd
a
-
-
-
-
engint
stopexe
-
-
-
-
disgint
reset
-
-
-
-
stopsys
wdreset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
©Copyright 2018, PADAUK Technology Co. Ltd
Page 98 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
8. Code Options
Option
Selection
Enable
Disable
4.1V
Description
Security Enable
Security
Security Disable
Select LVR = 4.1V
Select LVR = 3.6V
Select LVR = 3.1V
Select LVR = 2.8V
Select LVR = 2.5V
Select LVR = 2.2V
Select LVR = 2.0V
Select LVR = 1.8V
3.6V
3.1V
2.8V
LVR
2.5V
2.2V
2.0V
1.8V
Yes
reach normal operating voltage quickly within 20 mS
can’t reach normal operating voltage quickly within 20 mS
Single FPP unit mode
Under_20mS_VDD_OK
FPPA
No
1-FPPA
2-FPPA
Two FPP units mode
©Copyright 2018, PADAUK Technology Co. Ltd
Page 99 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
9. Special Notes
This chapter is to remind user who use PMC234/PMS234 series IC in order to avoid frequent errors upon
operation.
9-1. Warning
User must read all application notes of the IC by detail before using it. Please download the related
application notes from the following link:
http://www.padauk.com.tw/tw/technical/index.aspx
9-2. Using IC
9-2-1. IO pin usage and setting
(1) IO pin as digital input
When IO is set as digital input, the level of Vih and Vil would changes with the voltage and
temperature. Please follow the minimum value of Vih and the maximum value of Vil.
The value of internal pull high resistor would also changes with the voltage, temperature and pin
voltage. It is not the fixed value.
(2) Description of PBDIER
There are no PCDIER and PDDIER registers in PMC234/PMS234, therefore, enabling the digital input
of PC/PD pins should be configured through PB pin and share PBDIER register accordingly. For
example:
PC[0:3] and PB.0 are configured by PBDIER.0
PC[4:7] and PB.1 are configured by PBDIER.1
PD[0:1] and PB.2 are configured by PBDIER.2
When PBDIER.0 = 1, certain IOs of PB.0 and PC[0:3] that are configured as digital input and enable
the wake-up function.
(3) IO pin as analog input
Configure IO pin as input
Set PADIER and PBDIER registers to configure corresponding IO as analog input
Set PAPH and PBPH registers to disable corresponding IO pull-up resistor
The functions of PADIER and PBDIER registers of PMC234/PMS234 series IC is contrary to ICE
functions
Please use following program in order to keep ICE emulation consisting with
PMC234/PMS234 series IC procedure.
$ PADIER 0xF0;
$ PBDIER 0x0F;
(4) PA5 as output pin
PA5 can only be Open-Drain output pin. Output high requires adding pull-up resistor.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 100 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
(5) PA5 as PRST# input pin
No internal pull-up resistor for PA5
Configure PA5 as input
Set CLKMD.0=1 to enable PA5 as PRST# input pin
(6) PA5 as input pin to connect with a push button or a switch by a long wire
Needs to put a >10Ω resistor in between PA5 and the long wire
Avoid using PA5 as input
(7) PA7 and PA6 as external crystal oscillator
Configure PA7 and PA6 as input
Disable PA7 and PA6 internal pull-up resistor
Configure PADIER register to set PA6 and PA7 as analog input
EOSCR register bit [6:5] selects corresponding crystal oscillator frequency :
01 : for lower frequency, ex : 32kHz
10 : for middle frequency, ex : 455kHz、1MHz
11 : for higher frequency, ex : 4MHz
Program EOSCR.7 =1 to enable crystal oscillator
Ensure EOSC working well before switching from IHRC or ILRC to EOSC
Note: Please read the PMC-APN013 carefully. According to PMC-APN013,, the crystal oscillator should
be used reasonably. If the following situations happen to cause IC start-up slowly or non-startup,
PADAUK Technology is not responsible for this: the quality of the user's crystal oscillator is not good,
the usage conditions are unreasonable, the PCB cleaner leakage current, or the PCB layouts are
unreasonable.
9-2-2. Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit
Step2: Clear INTRQ register
Step3: In the main program, using ENGINT to enable CPU interrupt function
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine
Step5: After the Interrupt Service Routine being executed, return to the main program
* Use DISGINT in the main program to disable all interrupts
* When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG
register. POPAF instruction is to restore ALU and FLAG register before RETI as below:
void Interrupt (void)
// Once the interrupt occurs, jump to interrupt service
routine
{
// enter DISGINT status automatically, no more interrupt is
accepted
PUSHAF;
…
POPAF;
©Copyright 2018, PADAUK Technology Co. Ltd
Page 101 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
}
// RETI will be added automatically. After RETI being executed, ENGINT
status will be restored
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function
(3) FPPA1 will not be affected by interrupt at all
9-2-3. System clock switching
(1) System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock
and turn off the original clock source at the same time. For example: When switching from clock A to
clock B, please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Case 1 : Switch system clock from ILRC to IHRC/2
CLKMD
=
0x36;
0;
// switch to IHRC, ILRC can not be disabled here
CLKMD.2 =
// ILRC can be disabled at this time
Case 2 : Switch system clock from ILRC to EOSC
CLKMD
=
0xA6;
0;
// switch to EOSC, ILRC can not be disabled here
CLKMD.2 =
// ILRC can be disabled at this time
ERROR. Switch ILRC to IHRC and turn off ILRC simultaneously
CLKMD 0x50; // MCU will hang
=
(2) Please ensure the EOSC oscillation has established before switching from ILRC or IHRC to EOSC.
MCU will not check its status. Please wait for a while after enabling EOSC. System clock can be
switched to EOSC afterwards. Otherwise, MCU will hang. The example for switching system clock from
ILRC to 4MHz EOSC after boot up is as below:
.ADJUST_IC
DISABLE
CLKMD.1 = 0;
// turn off WDT for executing delay instruction.
// 4MHz EOSC start to oscillate.
$
EOSCR
Enable, 4MHz;
delay 255
// Delay for EOSC establishment
CLKMD = 0xA4;
CLKMD.2 = 0;
// ILRC -> EOSC;
// turn off ILRC only if necessary
The delay duration should be adjusted in accordance with the characteristic of the crystal and PCB. To
measure the oscillator signal by the oscilloscope, please select (x10) on the probe and measure through
PA6(X2) pin to avoid the interference on the oscillator.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 102 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
9-2-4. Power down mode, wakeup and watchdog
(1) Watchdog will be inactive once ILRC is disabled
(2) Please turn off watchdog before executing STOPSYS or STOPEXE instruction, otherwise IC will be
reset due to watchdog timeout. It is the same as in ICE emulation.
(3) The clock source of Watchdog is ILRC if the fast wakeup is disabled; otherwise, the clock source of
Watchdog will be the system clock and the reset time becomes much shorter. It is recommended to
disable Watchdog and enable fast wakeup before entering STOPSYS mode. When the system is waken
up from power down mode, please firstly disable fast wakeup function, and then enable Watchdog. It is
to avoid system to be reset after being waken up.
(4) If enable Watchdog during programming and also wants the fast wakeup, the example as below:
CLKMD.En_WatchDog
=
0;
// disable watchdog timer
$ MISC
stopexe;
nop;
Fast_Wake_Up;
$ MISC
Wdreset;
WT_xx;
// Reset Watchdog time to normal wake-up
// enable watchdog timer
CLKMD.En_WatchDog
=
1;
9-2-5. TIMER time out
When select $ INTEGS BIT_R (default value) and T16M counter BIT8 to generate interrupt, if T16M
counts from 0, the first interrupt will occur when the counter reaches to 0x100 (BIT8 from 0 to 1) and the
second interrupt will occur when the counter reaches 0x300 (BIT8 from 0 to 1). Therefore, selecting BIT8
as 1 to generate interrupt means that the interrupt occurs every 512 counts. Please notice that if T16M
counter is restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
If select $ INTEGS BIT_F(BIT triggers from 1 to 0) and T16M counter BIT8 to generate interrupt, the
T16M counter changes to an interrupt every 0x200/0x400/0x600/. Please pay attention to two differences
with setting INTEGS methods.
9-2-6. Using ADC
(1) Configure corresponding IO as input through PXDIER register
(2) The recommended highest ADC conversion frequency is 500kHz and maximum output impedance of
analog signal source is 10KΩ.
(3) Never restart next conversion before completion of last ADC conversion; otherwise, wrong value would
get.
(4) Please pay attention on sequence of operation if the program fits for below conditions,
©Copyright 2018, PADAUK Technology Co. Ltd
Page 103 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
1. Use the FPP (ex. FPPA0) for handling power-save mode to disable ADC.
2. Use the FPP (ex. FPPA1) for handling ADC conversion to enable ADC and wait for completion
of ADC conversion with WAIT1 ADC_Done instruction.
3. Execute above【1】&【2】simultaneously
In case the above sequence is not properly arranged, there may be a chance that FPPA1 can not pass
through WAIT1 ADC_Done instruction because the ADC may be disabled by FPPA0 before WAIT1
ADC_Done instruction being executed.
Recommendation:
Define a Flag which represents the operation of ADC. Every time FPPA1 set the flag when enable the
ADC and reset it when the completion of ADC conversion. FPPA0 checks this flag and decides to enter
power-save and disable ADC if it is reset.
9-2-7. LVR
(1) VDD must reach or above 2.2V for successful power-on process; otherwise IC will be inactive.
(2) The setting of LVR (1.8V, 2.0V, 2.2V etc) will be valid just after successful power-on process.
9-2-8. IHRC
(1) The IHRC frequency calibration is performed when IC is programmed by the writer.
(2) Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the
IHRC frequency (either for package or COB), if the calibration is done before molding process, the
actual IHRC frequency after molding may be deviated or becomes out of spec. Normally , the frequency
is getting slower a bit.
(3) It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not
take any responsibility for this situation.
(4) Users can make some compensatory adjustments according to their own experiences. For example,
users can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
9-2-9. Program writing
There are 8 pins for using the writer to program: PA0,PA3,PA4,PA5,PA6,PA7,VDD, and GND.
User can program PMC234/PMS234 from using PDK3S-P-002. Jumper is in the CN35 at the back of
writer:
(1) Put the PMC234/PMS234-S20/D20 downwards by three spaces from the top of the Textool.
(2) Put the PMC234/PMS234-S24/K24/Y24 downwards by two spaces from the top of the Textool.
(3) Put the PMC234/PMS234-S28/K28 to upwards one space from the top of the Textool.
(4) Other packages could be programmed by user’s way.
All the left signs behind the jumper are the same (there are VDD, PA0, PA3, PA4, PA5, PA6, PA7, and
GND).The following picture is shown:
©Copyright 2018, PADAUK Technology Co. Ltd
Page 104 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
If user use PDK5S-P-003 or above to program, please follow the instruction.
Methods of moving IC up one space from the top of the Textool:
(1) Unplug the Textool;
(2) Rotate the Textool by 180° and re-plug in with shifting 1 pin upward as below:
(3) Put the IC at the top of the Textool
Special notes about voltage and current while Multi-Chip-Package(MCP) or On-Board
Programming
(1) PA5 (VPP) may be higher than 11V.
(2) VDD may be higher than 6.5V, and its maximum current may reach about 20mA.
(3) All other signal pins level (except GND) are the same as VDD.
User should confirm when using this product in MCP or On-Board Programming, the peripheral circuit
or components will not be destroyed or limit the above voltages.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 105 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
9-3. Using ICE
9-3-1. Emulating PMC234/PMS234 series IC on ICE PDK3S-I-001/002/003
PMC234/PMS234 series I/O pin is defined as compatible with P234C series, but it has 4 more I/O pins than
P234C. When using ICE PDK3S-I-001/002 to emulate PMC234/PMS234 series IC, please according to
different number of pin used, use cable labeled CN10 or with jumper wire to connect to CN10 connector on
ICE PDK3S-I-001/002.
(1) Emulating PMC234/PMS234(SOP20/DIP20) : Use cable labeled CN10:P234CS20/CSS20/CD20 to
connect CN10 connector on ICE PDK3S-I-001/002. Connection is shown as below.
(2) Emulating PMC234/PMS234(SOP24/DIP24) : Use cable labeled CN10:P234CS24/CK24 to connect
CN10 connector on ICE PDK3S-I-001/002. Connection is also shown as below.
(3) Emulating PMC234/PMS234(SOP28/DIP28) : Use cable labeled CN10:P234CS24/CK24 to connect
CN10 connector on ICE PDK3S-I-001/002 as (1) and (2). But the extra 4 I/O pins PC6, PC7, PD0 and
PD1 required jumper wire on CN11.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 106 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
PMC234/PMS234 Series
12-bit ADC Enhanced FPPATM Controller
9-3-2. Important Notice for ICE operation
PDK3S-I-001/002/003 does not support emulating below PMC234/PMS234 series IC functions from (a) to
(g). Thus, user needs to take PMC234/PMS234 Real Chip for test. Please notice:In order to avoid the
problems on difference between ICE and Real Chip test procedure, those functions will be temporarily
removed from datasheet before ICE is set to support them. PMC234/PMS234 Real Chip is defaulted with
these functions and performing ordinarily. User is recommended to consider these exceptions and careful
handle whenever doing the test.
(a) PMC234/PMS234 series IC is able to set LVR minimum to 1.8V, total 8 stages 4.0V, 3.5V, 3.0V,
2.75V, 2.5V, 2.2V, 2.0V, 1.8V.
(b) PMC234/PMS234 series IC LVR function can be disabled by register (misc.2).
(c) PMC234/PMS234 series IC is able to support LVR reset and fast-recover by register (misc.3).
(d) PMC234/PMS234 series IC is able to be set as single core operating model.
(e) PMC234/PMS234 series IC supports VDD less than 4V, 3V, 2V voltage level detection and store
detecting result to internal register (rstst).
(f) PMC234/PMS234 series IC supports reset-source detection.
(g) Watch-dog series IC provides watch-dog time out function which is assigned by register misc[1:0]
©Copyright 2018, PADAUK Technology Co. Ltd
Page 107 of 107
PDK-DS-PMX234_V103 – Dec. 19, 2018
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