PMS271 [PADAUK]
Field Programmable Processor Array;
| 型号： | PMS271 |
| 厂家： | 
PADAUK Technology |
| 描述： | Field Programmable Processor Array |
| 文件： | 总90页 (文件大小：1429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PMC271/PMS271 Series
8-bit ADC
Field Programmable Processor Array
(FPPATM) 8-bit Controller
Data Sheet
Version 1.05 – Dec. 18, 2018
Copyright 2018 by PADAUK Technology Co., Ltd., all rights reserved
6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.
TEL: 886-3-572-8688 www.padauk.com.tw
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those that may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,
customers should design a product with adequate operating safeguards.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 2 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Table of Contents
1. Features...............................................................................................................................8
1.1.
1.2.
1.3.
1.4.
Special Features...................................................................................................................8
System Features...................................................................................................................8
CPU Features .......................................................................................................................8
Package Information .............................................................................................................9
2. General Description and Block Diagram ........................................................................10
3. Pin Assignment and Description.....................................................................................11
4. Device Characteristics .....................................................................................................16
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
DC/AC Characteristics ........................................................................................................16
Absolute Maximum Ratings.................................................................................................18
Typical IHRC Frequency vs. VDD (calibrated to 16MHz).....................................................18
Typical ILRC Frequency vs. VDD........................................................................................18
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)........................................19
Typical ILRC Frequency vs. Temperature...........................................................................19
Typical Operating Current vs. VDD and CLK=IHRC/n.........................................................20
Typical Operating Current vs. VDD and CLK=ILRC/n..........................................................20
Typical Lowest Operating Current vs. VDD and CLK=ILRC/n .............................................21
4.10. Typical Operating Current vs. VDD @CLK=32KHz EOSC/n ...............................................22
4.11. Typical Operating Current vs. VDD @CLK=1MHz EOSC/n.................................................23
4.12. Typical Operating Current vs. VDD @CLK=4MHz EOSC/n.................................................24
4.13. Typical IO pull high resistance.............................................................................................25
4.14. Typical IO driving current (IOH) and sink current (IOL) ...........................................................25
4.15. Typical IO input high / low threshold voltage (VIH/VIL) ..........................................................26
4.16. Typical (VDD/2) Bias output voltage....................................................................................26
4.17. Typical power down current (IPD) and power save current (IPS)............................................27
5. Functional Description.....................................................................................................28
5.1.
5.2.
5.3.
Processing Units .................................................................................................................28
5.1.1. Program Counter ......................................................................................................29
5.1.2. Stack Pointer ............................................................................................................29
5.1.3. Single FPP mode......................................................................................................30
Program Memory – OTP .....................................................................................................31
5.2.1. Program Memory Assignment...................................................................................31
5.2.2. Example of Using Program Memory for Two FPP mode...........................................31
5.2.3. Example of Using Program Memory for Single FPP mode........................................32
Program Structure...............................................................................................................33
5.3.1. Program structure of two FPP units mode.................................................................33
5.3.2. Program structure of single FPP mode .....................................................................33
Boot Procedure...................................................................................................................34
Data Memory – SRAM ........................................................................................................35
Arithmetic and Logic Unit ....................................................................................................35
Oscillator and clock.............................................................................................................36
5.4.
5.5.
5.6.
5.7.
5.7.1. Internal High RC oscillator and Internal Low RC oscillator ........................................36
5.7.2. Chip calibration.........................................................................................................36
5.7.3. IHRC Frequency Calibration and System Clock........................................................36
©Copyright 2018, PADAUK Technology Co. Ltd
Page 3 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.7.4. External Crystal Oscillator.........................................................................................38
5.7.5. System Clock and LVR levels ...................................................................................39
5.7.6. System Clock Switching............................................................................................40
16-bit Timer (Timer16) ........................................................................................................41
Watchdog Timer..................................................................................................................42
5.8.
5.9.
5.10. Interrupt ..............................................................................................................................43
5.11. Power-Save and Power-Down ............................................................................................45
5.11.1. Power-Save mode (“stopexe”) ................................................................................45
5.11.2. Power-Down mode (“stopsys”)................................................................................46
5.11.3. Wake-up .................................................................................................................47
5.12. IO Pins................................................................................................................................48
5.13. Reset and LVR....................................................................................................................49
5.13.1. Reset ......................................................................................................................49
5.13.2. LVR reset................................................................................................................49
5.14. LCD Half VDD Bias Voltage................................................................................................49
5.15. Analog-to-Digital Conversion (ADC) module .......................................................................50
5.15.1.The input requirement for AD conversion.................................................................52
5.15.2.ADC clock selection.................................................................................................52
5.15.3.AD conversion .........................................................................................................52
5.15.4.Configuring the analog pins .....................................................................................53
5.15.5.Using the ADC.........................................................................................................53
6. IO Registers.......................................................................................................................54
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
ACC Status Flag Register (flag), IO address = 0x00 ...........................................................54
FPP unit Enable Register (fppen), IO address = 0x01.........................................................54
Stack Pointer Register (sp), IO address = 0x02...................................................................54
Clock Mode Register (clkmd), IO address = 0x03 ...............................................................55
Interrupt Enable Register (inten), IO address = 0x04...........................................................55
Interrupt Request Register (intrq), IO address = 0x05 .........................................................55
Timer 16 mode Register (t16m), IO address = 0x06............................................................56
General Data register for IO (gdio), IO address = 0x07 .......................................................56
External Oscillator setting Register (eoscr, write only), IO address = 0x0a..........................56
6.10. IHRC oscillator control Register (ihrcr, write only), IO address = 0x0b ................................57
6.11. Interrupt Edge Select Register (integs), IO address = 0x0c.................................................57
6.12. Port A Digital Input Enable Register (padier), IO address = 0x0d........................................58
6.13. Port B Digital Input Enable Register (pbdier), IO address = 0x0e........................................59
6.14. Port A Data Registers (pa), IO address = 0x10 ...................................................................60
6.15. Port A Control Registers (pac), IO address = 0x11..............................................................60
6.16. Port A Pull-up Registers (paph), IO address = 0x12............................................................60
6.17. Port B Data Registers (pb), IO address = 0x14 ...................................................................60
6.18. Port B Control Registers (pbc), IO address = 0x15..............................................................60
6.19. Port B Pull-up Registers (pbph), IO address = 0x16............................................................60
6.20. ADC Control Register (adcc), IO address = 0x20................................................................60
6.21. ADC Mode Register (adcm, write only), IO address = 0x21.................................................61
6.22. ADC Result Register (adcr, read only), IO address = 0x22..................................................61
6.23. ADC Reference High Control Register (adcrhc), IO address = 0x1c....................................61
6.24. RESET Status Register (rstst), IO address = 0x25..............................................................62
6.25. MISC Register (misc), IO address = 0x3b ...........................................................................62
7. Instructions.......................................................................................................................63
7.1.
Data Transfer Instructions...................................................................................................64
©Copyright 2018, PADAUK Technology Co. Ltd
Page 4 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
Arithmetic Operation Instructions ........................................................................................69
Shift Operation Instructions.................................................................................................71
Logic Operation Instructions................................................................................................72
Bit Operation Instructions....................................................................................................75
Conditional Operation Instructions ......................................................................................76
System control Instructions .................................................................................................78
Summary of Instructions Execution Cycle ...........................................................................80
Summary of affected flags by Instructions...........................................................................81
8. Code Options ....................................................................................................................82
9. Special Notes....................................................................................................................83
9.1.
9.2.
Warning...............................................................................................................................83
Using IC..............................................................................................................................83
9.2.1.IO pin usage and setting ............................................................................................83
9.2.2.Interrupt .....................................................................................................................84
9.2.3.System clock switching..............................................................................................85
9.2.4.Power down mode, wakeup and watchdog ................................................................86
9.2.5.TIMER time out..........................................................................................................86
9.2.6.Using ADC.................................................................................................................87
9.2.7.LVR……………………………………………………………………………………………..87
9.2.8.IHRC …………………………………………………………………………………………..87
9.2.9.Program writing..........................................................................................................88
Using ICE............................................................................................................................89
9.3.
9.3.1.Emulating PMC271/PMS271 series IC on ICE PDK3S-I-001/002/003 .......................89
9.3.2.Important Notice for ICE operation.............................................................................90
©Copyright 2018, PADAUK Technology Co. Ltd
Page 5 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Revision History:
Revision
0.01
Date
Description
2013/12/10 1ST version
0.02
2014/02/19
2014/12/22
Add chapter 8 Special Notes
0.03
Amend PMS271 operating temperature
1. Amend page 7: PMC271/PMS271 Band-gap mV
2. Amend 1.1 PMS271 series operating temperature range to -20°C ~ 70°C
3. Amend 4.1 Band-gap reference voltage
1. Updated company address & Tel No.
2. Amend Section 1.1, 1.3, 1.4
0.04
2015/06/11
3. Add Chapter 3 Pin Assignment and Description: PMC271-S08, PMC271-D08,
PMS271-S08, PMS271-D08
4. Amend Section 4.1 DC/AC Characteristics
5. Amend Section 4.3 to 4.6, 4.13 to 4.15
6. Add Section 4.17 Typical power down current (IPD) and power save current (IPS)
7. Amend Section 5.2.1 Program Memory Assignment
8. Amend Section 5.7 Oscillator and clock
9. Amend Section 5.7.4, 5.7.5
10. Amend Section 5.8 16-bit Timer
11. Amend Section 5.10 Interrupt
1.05
2018/12/18
12. Amend Section 5.11.1, 5.11.2
13. Add Section 5.15.5 Using the ADC
14. Amend Section 6.7, 6.12, 6.13, 6.23
15. Amend Section 7.8 Summary of Instructions Execution Cycle and delete 8.2.9
16. Add Chapter 8 Code Options
17. Add Section 9.1 Warning
18. Amend Section 9.2.1, 9.2.5
19. Add Section 9.2.8 IHRC
20. Amend Section 9.2.9 Program writing
21. Amend Section 9.3 Using ICE
©Copyright 2018, PADAUK Technology Co. Ltd
Page 6 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Major Differences between PDK22C and PMC271/PMS271
There are many differences between PDK22C and PMC271/PMS271. The table below only shows the major
differences between them.
Item
Function
PDK22C
15 IO + 1 input
PMC271/PMS271
1
IO Pin
16 IO
2
IO capability
15mA@5.0V
10mA@5.0V
+/- 60mV(@1.20V)
after calibration
8 levels LVR setting
Yes
3
Band-gap
N/A
4
5
LVR
5 levels LVR setting
Fast wake up
N/A
6
Single FPPA mode
ADC channel
N/A
Yes
7
4 channels
8 channels
8
T16 clock source
LCD VDD/2 bias voltage
misc register
Support external RC oscillator
Enabled by code option
N/A
Not support
Controlled by misc.4
Yes
9
10
Port digital input
configure registers
IHRC option command
WDT timeout period
11
adcdi register
padier and pbdier
12
13
.ADJUST_OTP_IHRCR
1024 ILRC cycles
.ADJUST_IC
4 selectable periods
Procedure for converting code from PDK22C to PMC271/PMS271
Please follow the below steps for converting codes from PDK22C to PMC271/PMS271:
1. Go through the PMC271/PMS271 datasheet and user guide;
2. Modify the source code engineering file “.pre”; change “.chip PDK22CXXX” to “.chip PMC271” or “.chip
PMS271”
3. Press “Build” and then IDE will show some errors and warnings.
4. Modify the source code correspondingly until all errors have been solved.
5. Save and build the project files again.
6. Write to a real chip and test its functions in detail.
7. Back to the step 3 if necessary.
8. Contact our FAE at fae@padauk.com.tw if you still have any problems.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 7 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
1. Features
1.1. Special Features
PMC271 series:
High EFT series
Operating temperature range: -40°C ~ 85°C
PMS271 series:
General purpose series
Not supposed to use in AC RC step-down powered or high EFT requirement applications.
PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.
Operating temperature range: -20°C ~ 70°C
1.2. System Features
1KW OTP program memory
64 Bytes data RAM
One hardware 16-bit timer
Support fast wake-up
16 IO pins with 10mA capability and optional pull-up resistor
Every IO pin can be configured to enable wake-up function
Band-gap circuit to provide 1.20V reference voltage
Internal High RC Oscillator (IHRC) frequency
Total 8-channel 8-bit ADC, including one channel for band-gap reference voltage input
Built-in half VDD bias voltage generator for LCD application
Operating voltage range: 2.2V ~ 5.5V
Clock sources: internal high RC oscillator, internal low RC oscillator and external crystal oscillator
Eight levels of LVR reset ~ 4.1V, 3.6V, 3.1V, 2.8V, 2.5V, 2.2V, 2.0V, 1.8V
Two external interrupt pins
1.3. CPU Features
Operating modes: Two processing units FPPATM mode or Traditional one processing unit mode
101 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer and adjustable stack level
Direct and indirect addressing modes for data access. Data memories are available for use as an index
pointer of Indirect addressing mode
IO space and memory space are independent
©Copyright 2018, PADAUK Technology Co. Ltd
Page 8 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
1.4. Package Information
PMC271 series
PMC271 - Y20: SSOP20 (150mil);
PMC271 - S20:SOP20 (300mil);
PMC271 - D20:DIP20 (300mil);
PMC271 - S18: SOP18 (300mil) ;
PMC271 - Y16: SSOP16 (150mil);
PMC271 - S16: SOP16 (150mil) ;
PMC271 - D16:DIP16 (300mil);
PMC271 - S14: SOP14 (150mil);
PMC271 - D14: DIP14 (300mil);
PMC271 - S08: SOP8 (150 mil);
PMC271 - D08: DIP8 (300mil)
PMS271 series
PMS271 - Y20: SSOP20 (150mil);
PMS271 - S20:SOP20 (300mil);
PMS271 - D20:DIP20 (300mil);
PMS271 - S18: SOP18 (300mil) ;
PMS271 - Y16: SSOP16 (150mil);
PMS271 - S16: SOP16 (150mil) ;
PMS271 - D16:DIP16 (300mil);
PMS271 - S14: SOP14 (150mil);
PMS271 - D14: DIP14 (300mil);
PMS271 - S08: SOP8 (150 mil);
PMS271 - D08: DIP8 (300mil)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 9 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
2. General Description and Block Diagram
The PMC271/PMS271 series is an ADC-Type of PADAUK’s parallel processing, fully static, OTP-based CMOS
two 8 bit processor array that can execute two peripheral functions in parallel. Besides operated in two
processing units, PMC271/PMS271 can act as traditional MCU in one processing unit. The PMC271/PMS271
employs RISC architecture based on patented FPPA™ (Field Programmable Processor Array) technology and
most the instructions are executed in one cycle except that few instructions are two cycles that handle indirect
memory access.
1KW bits OTP program memory and 64 bytes data SRAM are inside for two FPP units using, PMC271/PMS271
provides one hardware 16-bit timer, one 8 channels 8-bit ADC and hardware circuit to generate half VDD bias
voltage for LCD application. The functions for peripheral devices like UART and PWM can be easily
implemented by using FPPA™ unique architecture.
1KW OTP
&
Task
Interrupt
Control
controller
16-bit Timer
IO Ports
PWM
Function
FPP0
FPP1
I2C
Function
64 Bytes
SRAM
SPI
Function
8-Bit ADC
UART
Function
POR / LVD
Key scan
Function
Watchdog
Timer
LCD
Function
Power
management
©Copyright 2018, PADAUK Technology Co. Ltd
Page 10 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
3. Pin Assignment and Description
PMC271 series
PA2/COM2
PA3/AD5/COM3
PA4/AD6/COM4
PA5/PRST#
GND
1
2
20 PA1/COM1
19 PA0/INT0
PA2/COM2
PA3/AD5/COM3
PA4/AD6/COM4
PA5/PRST#
GND
1
2
3
4
5
6
7
8
9
18 PA1/COM1
17 PA0/INT0
16 PA7/X1
15 PA6/X2
14 VDD
PA7/X1
3
18
4
17 PA6/X2
VDD
NC
5
16
15
14
13
12
11
NC
6
PB7/AD4
PB6
PB0/INT1/AD0
PB1/AD1
13
12
11
10
PB7/AD4
PB6
PB0/INT1//AD0
PB1/AD1
7
8
PB5
PB2/AD2
PB5
9
PB2/AD2
PB4
PB3/AD3
PB4
10
PB3/AD3
PMC271-S18(SOP18-300mil)
PMC271-Y20(SSOP20-150mil)
PMC271-S20(SOP20-300mil)
PMC271-D20(DIP20-300mil)
PA2/COM2
PA3/AD5/COM3
PA4/AD6/COM4
PA5/PRST#
GND
1
2
3
4
5
6
7
14 PA1/COM1
PA2/COM2
PA3/AD5//COM3
PA4/AD6/COM4
PA5/PRST#
GND
PA1/COM1
PA0/INT0
PA7/X1
PA6/X2
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
13 PA0/INT0
12 PA7/X1
11 PA6/X2
10 VDD
PB0/INT1/AD0
PB1/AD1
9
8
PB7/AD4
PB6
PB0/INT1/AD0
PB1/AD1
PB7/AD4
PB6
PB2/AD2
PB5
PMC271-S14(SOP14-150mil)
PMC271-D14(DIP14-300mil)
PMC271-Y16(SSOP16-150mil)
PMC271-S16(SOP16-150mil)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 11 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
PMS271 series
PA2/COM2
PA3/AD5/COM3
PA4/AD6/COM4
PA5/PRST#
GND
1
2
20 PA1/COM1
PA2/COM2
PA3/AD5/COM3
PA4/AD6/COM4
PA5/PRST#
GND
1
2
3
4
5
6
7
8
9
18 PA1/COM1
17 PA0/INT0
16 PA7/X1
15 PA6/X2
14 VDD
19 PA0/INT0
PA7/X1
17 PA6/X2
3
18
4
VDD
NC
5
16
15
14
13
12
11
NC
6
PB7/AD4
PB6
PB0/INT1/AD0
PB1/AD1
13
12
11
10
PB7/AD4
PB6
PB0/INT1//AD0
PB1/AD1
7
8
PB5
PB2/AD2
PB5
9
PB2/AD2
PB4
PB3/AD3
PB4
10
PB3/AD3
PMS271-S18(SOP18-300mil)
PMS271-Y20(SSOP20-150mil)
PMS271-S20(SOP20-300mil)
PMS271-D20(DIP20-300mil)
PA2/COM2
PA3/AD5/COM3
PA4/AD6/COM4
PA5/PRST#
GND
1
2
3
4
5
6
7
14 PA1/COM1
13 PA0/INT0
12 PA7/X1
11 PA6/X2
10 VDD
PA2/COM2
PA3/AD5//COM3
PA4/AD6/COM4
PA5/PRST#
GND
PA1/COM1
PA0/INT0
PA7/X1
PA6/X2
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PB0/INT1/AD0
PB1/AD1
9
8
PB7/AD4
PB6
PB0/INT1/AD0
PB1/AD1
PB7/AD4
PB6
PB2/AD2
PB5
PMS271-S14(SOP14-150mil)
PMS271-D14(DIP14-300mil)
PMS271-Y16(SSOP16-150mil)
PMS271-S16(SOP16-150mil)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 12 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Pin Description
Pin & Buffer
Pin Name
Description
Type
The functions of this pin can be:
(1) Bit 7 of port A. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
PA7 /
X1
ST /
(2) X1 (input) when crystal oscillator is used.
CMOS /
Analog
If this pin is used for crystal oscillator, bit 7 of padier register must be programmed
“0” to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function is also disabled if bit 7 of padier register is “0”.
The functions of this pin can be:
(1) Bit 6 of port A. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
PA6 /
X2
ST /
(2) X2 (output) when crystal oscillator is used.
CMOS /
Analog
If this pin is used for crystal oscillator, bit 6 of padier register must be programmed
“0” to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function is also disabled if bit 6 of padier register is “0”.
The functions of this pin can be:
(1) Bit 5 of port A. It can be configured as digital input or open-drain output pin.
Please notice that there is no pull-up resistor in this pin.
(2) Hardware reset.
IO
PA5 /
ST /
PRST#
This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”.
Please put 33Ω resistor in series to have high noise immunity when this pin is in
input mode.
CMOS
The functions of this pin can be:
(1) Bit 4 of port A. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
PA4 /
AD6 /
COM4
(2) Channel 6 input of ADC.
ST /
(3) COM4 for LCD to provide (1/2 VDD) for LCD bias voltage.
If this pin acts as analog input, bit 4 of padier register must be programmed “0” to
avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 4 of
padier register is “0”
CMOS /
Analog
©Copyright 2018, PADAUK Technology Co. Ltd
Page 13 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Pin Type &
Buffer Type
Pin Name
Description
The functions of this pin can be:
(1) Bit 3 of port A. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
PA3 /
AD5 /
COM3
(2) Channel 5 input of ADC.
ST /
(3) COM3 for LCD to provide (1/2 VDD) for LCD bias voltage.
If this pin acts as analog input, bit 3 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 3 of
padier register is “0”.
CMOS /
Analog
The functions of this pin can be:
(1) Bit 2 of port A. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
PA2 /
ST /
COM2
(2) COM2 for LCD to provide (1/2 VDD) for LCD bias voltage.
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 2 of padier register is “0”.
CMOS
The functions of this pin can be:
(1) Bit 1 of port A. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
PA1 /
ST /
COM1
(2) COM1 for LCD to provide (1/2 VDD) for LCD bias voltage.
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 1 of padier register is “0”.
CMOS
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
PA0 /
INT0
(2) External interrupt line 0. Both rising edge and falling edge are accepted to
request interrupt service.
ST /
CMOS
This pin can be used to wake-up system during sleep mode, however, wake-up
function from this pin is also disabled when bit 0 of padier register is “0”. Both
rising edge and falling edge are accepted to request interrupt service.
The functions of this pin can be:
(1) Bit 7 of port B. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
PB7 /
AD4
ST /
(2) Channel 4 input of ADC.
CMOS /
Analog
If this pin acts as analog input, bit 7 of pbdier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 7 of
pbdier register is “0”.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 14 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Pin Type &
Buffer Type
Pin Name
Description
The function of this pin is Bit 6 of port B. It can be configured as digital input or
two-state output, with pull-up resistor.
IO
PB6
ST /
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 6 of pbdier register is “0”.
CMOS
The function of this pin is Bit 5 of port B. It can be configured as digital input or
two-state output, with pull-up resistor.
IO
PB5
PB4
ST /
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 5 of pbdier register is “0”.
CMOS
The function of this pin is Bit 4 of port B. It can be configured as digital input or
two-state output, with pull-up resistor.
IO
ST /
This pin can be used to wake-up system during sleep mode; however, wake-up
function from this pin is also disabled when bit 4 of pbdier register is “0”.
CMOS
The functions of this pin can be:
(1) Bit 1 of port B. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
PB1 /
AD1
ST /
(2) Channel 1 input of ADC.
CMOS /
Analog
If this pin acts as analog input, bit 1 of pbdier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 1 of
pbdier register is “0”.
The functions of this pin can be:
(1) Bit 0 of port B. It can be configured as digital input or two-state output, with
pull-up resistor.
IO
(2) External interrupt line 1. Both rising edge and falling edge are accepted to
request interrupt service.
PB0 /
INT1 /
AD0
ST /
CMOS /
Analog
(3) Channel 0 input of ADC.
If this pin acts as analog input, bit 0 of pbdier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep
mode; however, wake-up function from this pin is also disabled when bit 0 of
pbdier register is “0”.
VDD
GND
Positive power
Ground
Notes: IO: Input/Output; ST: Schmitt Trigger input; Analog: Analog input pin; CMOS: CMOS voltage level
©Copyright 2018, PADAUK Technology Co. Ltd
Page 15 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4. Device Characteristics
4.1. DC/AC Characteristics
All data are acquired under the conditions of Ta = - 40 oC ~ 85 oC, VDD=5.0V, fSYS=2MHz unless noted.
Symbol
Description
Operating Voltage
Min
Typ
Max
Unit
Conditions
VDD
2.2
5.0
5.5
V
* Subject to LVR tolerance
Under_20ms_Vdd_ok**=Y/N
System clock* =
IHRC/2
0
0
0
8M
4M
2M
V
V
V
V
DD≧3.0V / VDD≧3.3V
DD≧2.5V / VDD≧2.8V
DD≧2.2V / VDD≧2.2V
DD = 5.0V
fSYS
IHRC/4 & crystal oscillator
IHRC/8 & crystal oscillator
ILRC
Hz
24K
1.7
8
mA fSYS=1MIPS@5.0V
uA fSYS=ILRC=12KHz@3.3V
uA fSYS= 0Hz,VDD=5.0V
uA fSYS= 0Hz,VDD=3.3V
VDD=5.0V;
IOP
IPD
Operating Current
Power Down Current
0.7
0.4
(by stopsys command)
Power Save Current
IPS
0.4
mA Band-gap, LVR, IHRC, ILRC,
Timer16 modules are ON.
V
(by stopexe command)
VIL
VIH
Input low voltage for IO lines
Input high voltage for IO lines
IO lines sink current
0
0.7 VDD
7
0.2VDD
VDD
V
IOL
10
-7
13
mA VDD=5.0V, VOL=0.5V
mA VDD=5.0V, VOH=4.5V
V
IOH
IO lines drive current
Input voltage
-5
-9
-0.3
VDD+0.3
1
VIN
VDD+0.3≧VIN≧ -0.3
IINJ (PIN)
Injected current on pin
mA
62
VDD=5.0V
RPH
Pull-up Resistance
100
210
KΩ VDD=3.3V
VDD=2.2V
3.86
3.35
2.84
2.61
2.37
2.04
1.86
1.67
4.15
3.60
3.05
2.80
2.55
2.20
2.00
1.80
4.44
3.85
3.26
3.00
2.73
2.35
2.14
1.93
Low Voltage Reset Voltage *
VLVR
V
(Brown-out voltage)
VDD=2.2V ~ 5.5V
Band-gap Reference Voltage
(before calibration)
1.104*
1.109*
1.200*
1.200*
1.296*
1.291*
-40oC <Ta<85oC*
-20oC <Ta<70oC*
VDD=2.2V ~ 5.5V
-40oC <Ta<85oC*
-20oC <Ta<70oC*
V
VBG
Band-gap Reference Voltage *
1.140*
1.145*
1.200*
1.200*
1.260*
1.255*
(after calibration)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 16 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Symbol
fIHRC
Description
Min
Typ
16*
Max
Unit
Conditions
25oC, VDD=2.2V~5.5V
15.68*
16.32*
MHz
Frequency of IHRC after
VDD=2.2V~5.5V,
-40oC <Ta<85oC*
-20oC <Ta<70oC*
calibration *
14.72*
14.88*
16*
16*
17.28*
17.12*
VDD=5.0V, Ta=25oC
20.4*
27.6*
24*
24*
24*
12*
VDD=5.0V, -40oC <Ta<85oC*
VDD=5.0V, -20oC <Ta<70oC*
VDD=3.3V, Ta=25oC
15.6*
16.8*
32.4*
31.2*
fILRC
Frequency of ILRC *
AD Input Voltage
KHz
10.2*
13.8*
VDD=3.3V, -40oC <Ta<85oC*
VDD=5.0V, -20oC <Ta<70oC*
7.8*
8.4*
16.2*
15.6*
12*
12*
VAD
0
VDD
V
AD DNL AD Differential Non-Linearity*
±0.5*
±1*
LSB
LSB
AD INL
AD Integral Non-Linearity*
(VDD/2) pull-up resistance
(VDD/2) pull-down resistance
Deviation of (VDD/2) output
voltage
6.3
@VDD=5V
R(VDD/2)
KΩ
7.0
@VDD=3.3V
ΔV(VDD/2)
±1%
±3%
@VDD=5V
tINT
Interrupt pulse width
30
ns
V
VDD = 5.0V
VDR
RAM data retention voltage*
1.5
In power-down mode.
2048
4096
misc[1:0]=00 (default)
misc[1:0]=01
Watchdog timeout period
tWDT
TILRC
TILRC
TSYS
(TILRC is the clock period of ILRC)
16384
256
misc[1:0]=10
misc[1:0]=11
System boot-up period from
power-on
Where TILRC is the clock
period of ILRC
tSBP
1024
System wake-up period
Fast wake-up by IO toggle from
STOPEXE suspend
Where TSYS is the time
128
period of system clock
Fast wake-up by IO toggle from
STOPSYS suspend, IHRC is the
system clock
128 TSYS
Where TSIHRC is the stable time
of IHRC from power-on.
TSIHRC = 5us@ VDD=5V
Where TSILRC is the stable time
of ILRC from power-on.
TSILRC = 43ms@ VDD=5V
Where TILRC is the clock
+
TSIHRC
tWUP
Fast wake-up by IO toggle from
STOPSYS suspend, EOSC is
the system clock
128 TSYS
+
TSEOSC
Normal wake-up from
STOPEXE or STOPSYS
suspend
1024
TILRC period of ILRC
tRST
External reset pulse width
120
us @VDD=5V
*These parameters are for design reference, not tested for every chip.
** Under_20ms_VDD_Ok is a checking condition for the VDD rising from 0V to the stated voltage within 20ms.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 17 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.2. Absolute Maximum Ratings
Supply Voltage ……………………………......
Input Voltage …………………………………..
2.2V ~ 5.5V
-0.3V ~ VDD + 0.3V
Operating Temperature ………………………
PMC271 series: -40°C ~ 85°C
PMS271 series: -20°C ~ 70°C
-50°C ~ 125°C
Storage Temperature …………………………
4.3. Typical IHRC Frequency vs. VDD (calibrated to 16MHz)
4.4. Typical ILRC Frequency vs. VDD
©Copyright 2018, PADAUK Technology Co. Ltd
Page 18 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.5. Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)
4.6. Typical ILRC Frequency vs. Temperature
©Copyright 2018, PADAUK Technology Co. Ltd
Page 19 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.7. Typical Operating Current vs. VDD and CLK=IHRC/n
Conditions: ON: Band-gap, LVR, IHRC modules; OFF: ADC, T16, ILRC, EOSC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
Two FPP units mode
One FPP unit mode
Operating Current vs. VDD
Operating Current vs. VDD
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
16MIPS
8MIPS
4MIPS
2MIPS
1MIPS
0.5MIPS
16MIPS
8MIPS
4MIPS
2MIPS
1MIPS
0.5MIPS
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
4.8. Typical Operating Current vs. VDD and CLK=ILRC/n
Conditions: ON: Band-gap, LVR, ILRC modules; OFF: ADC, T16, IHRC, EOSC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
Two FPP units mode
One FPP unit mode
Operation Currentvs. VDD
Operation Current vs. VDD
0.1
0.08
0.06
0.04
0.02
0
0.1
0.08
0.06
0.04
0.02
0
ILRC/1
ILRC/4
ILRC/1
ILRC/4
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 20 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.9. Typical Lowest Operating Current vs. VDD and CLK=ILRC/n
Conditions: ON: ILRC module; OFF: ADC, T16, IHRC, Band-gap, LVR, EOSC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
Two FPP units mode
One FPP unit mode
Operation Currentvs. VDD
Operation Current vs. VDD
0.03
0.03
0.025
0.02
0.015
0.01
0.005
0
ILRC/1
ILRC/4
ILRC/1
ILRC/4
0.025
0.02
0.015
0.01
0.005
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 21 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.10.Typical Operating Current vs. VDD @CLK=32KHz EOSC/n
Conditions: ON: EOSC, Band-gap, LVR modules; OFF: ADC, T16, IHRC, ILRC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
EOSC: High driving current
Two FPP units mode
One FPP unit mode
EOSC(32KHz) Operation Current vs. VDD
EOSC(32KHz) Operation Current vs. VDD
0.14
0.14
0.12
0.1
0.12
0.1
0.08
0.06
0.04
0.02
0
0.08
0.06
0.04
0.02
0
EOSC/1
EOSC/1
EOSC/2
EOSC/4
EOSC/8
EOSC/2
EOSC/4
EOSC/8
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
Conditions: ON: EOSC module; OFF: ADC, T16, IHRC, ILRC, Band-gap, LVR modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
EOSC: Low driving current
Two FPP units mode
One FPP unit mode
EOSC(32KHz) Operation Current vs. VDD
EOSC(32KHz) Operation Current vs. VDD
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
EOSC/1
EOSC/2
EOSC/4
EOSC/8
EOSC/1
EOSC/2
EOSC/4
EOSC/8
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 22 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.11.Typical Operating Current vs. VDD @CLK=1MHz EOSC/n
Conditions: ON: EOSC, Band-gap, LVR modules; OFF: ADC, T16, IHRC, ILRC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
EOSC: High driving current
Two FPP units mode
One FPP unit mode
EOSC(1MHz) Operation Current vs. VDD
EOSC(1MHz) Operation Current vs. VDD
2.5
2
2.5
2
EOSC/1
EOSC/2
EOSC/4
EOSC/8
1.5
1
1.5
1
EOSC/1
EOSC/2
EOSC/4
EOSC/8
0.5
0
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
Conditions: ON: EOSC module; OFF: ADC, T16, IHRC, ILRC, Band-gap, LVR modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
EOSC: Low driving current
Two FPP units mode
One FPP unit mode
EOSC(1MHz) Operation Current vs. VDD
EOSC(1MHz) Operation Current vs. VDD
2
1.5
1
2
1.5
1
EOSC/1
EOSC/2
EOSC/4
EOSC/8
EOSC/1
EOSC/2
EOSC/4
EOSC/8
0.5
0
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 23 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.12.Typical Operating Current vs. VDD @CLK=4MHz EOSC/n
Conditions: ON: EOSC, Band-gap, LVR modules; OFF: ADC, T16, IHRC, ILRC modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
EOSC: High driving current
Two FPP units mode
One FPP unit mode
EOSC(4MHz) Operation Current vs. VDD
EOSC(4MHz) Operation Current vs. VDD
3.5
3
3.5
3
EOSC/1
EOSC/2
EOSC/4
EOSC/8
EOSC/1
EOSC/2
EOSC/4
EOSC/8
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
Conditions: ON: EOSC module; OFF: ADC, T16, IHRC, ILRC, Band-gap, LVR modules;
IO: PA0:0.5Hz output toggle and no loading, others: input and no floating
EOSC: Low driving current
Two FPP units mode
One FPP unit mode
EOSC(4MHz) Operation Current vs. VDD
EOSC(4MHz) Operation Current vs. VDD
3.5
3
3.5
3
EOSC/1
EOSC/2
EOSC/4
EOSC/8
EOSC/1
EOSC/2
EOSC/4
EOSC/8
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
VDD (V)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 24 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.13.Typical IO pull high resistance
4.14.Typical IO driving current (IOH) and sink current (IOL)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 25 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.15.Typical IO input high / low threshold voltage (VIH/VIL)
4.16.Typical (VDD/2) Bias output voltage
Output Voltage
VDD=5V
VDD=3.3V
1.667V
1.667V
1.667V
1.667V
VDD=2.1V
1.048V
1.049V
1.048V
1.047V
PA1
PA2
PA3
PA4
2.531V
2.531V
2.532V
2.531V
©Copyright 2018, PADAUK Technology Co. Ltd
Page 26 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
4.17.Typical power down current (IPD) and power save current (IPS)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 27 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5. Functional Description
5.1. Processing Units
There are two processing units (FPP unit) inside the PMC271/PMS271. In each processing unit, it includes (i)
its own Program Counter to control the program execution sequence (ii) its own Stack Pointer to store or
restore the program counter for program execution (iii) its own accumulator (iv) Status Flag to record the status
of program execution. Each FPP unit has its own program counter and accumulator for program execution, flag
register to record the status, and stack pointer for jump operation. Based on such architecture, FPP unit can
execute its own program independently, thus parallel processing can be expected.
These two FPP units share the same 1Kx16 bits OTP program memory, 64 bytes data SRAM and all the IO
ports, these two FPP units are operated at mutual exclusive clock cycles to avoid interference. One task switch
is built inside the chip to decide which FPP unit should be active for the corresponding cycle. The hardware
diagram and basic timing diagram of FPP units are illustrated in Fig. 1. For FPP0 unit, its program will be
executed in sequence every other system clock, shown as (M-1)th, Mth and (M+1)th instructions. For FPP1 unit,
its program will be also executed in sequence every other system clock, shown as (N-1)th, Nth and (N+1)th
instructions.
System Clock
FPP0
Program Counter 0
Stack Pointer 0
Accumulator 0
Task Switch
Time
(M-1)th
Mth
(M+1)th
1KW OTP
Program
Memory
Flag register 0
FPP0 active
FPP1
Program Counter 1
Stack Pointer 1
Accumulator 1
64 bytes
SRAM
(N-1)th
Nth
(N+1)th
IO Port
Flag register 1
FPP1 active
Fig. 1: Hardware and Timing Diagram of FPP units
©Copyright 2018, PADAUK Technology Co. Ltd
Page 28 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Each FPP unit has half computing power of whole system; for example, FPP0 and FPP1will be operated at
4MHz if system clock is 8MHz. The FPP unit can be enabled or disabled by programming the FPP unit Enable
Register, only FPP0 is enabled after power-on reset. The system initialization will be started from FPP0 and
FPP1 unit can be enabled by user’s program if necessary. Both FPP0 and FPP1 can be enabled or disabled by
using any one FPP unit.
5.1.1. Program Counter
Program Counter (PC) is the unit that contains the address of an instruction to be executed next. The program
counter is automatically incremented at each instruction cycle so that instructions are retrieved sequentially
from the program memory. Certain instructions, such as branches and subroutine calls, interrupt the sequence
by placing a new value in the program counter. The bit length of the program counter is 10 for
PMC271/PMS271. The initial program counter of FPP0 is 0 after hardware reset and 1 for FPP1. Whenever
any interrupt happens, the program counter will jump to ’h10 for interrupt service routine, only FPP0 accept
interrupt and each FPP unit has its own program counter to control the program execution sequence.
5.1.2. Stack Pointer
The stack pointer in each processing unit is used to point the top of the stack area where the local variables
and parameters to subroutines are stored; the stack pointer register (sp) is located in IO address 0x02h. The
stack pointer is 8 bit and so the stack memory cannot be accessed over 64 bytes and should be defined within
64 bytes from 0x00h address. The stack memory of PMC271/PMS271 for each FPP unit can be assigned by
user via stack pointer register, means that the depth of stack pointer for each FPP unit is adjustable in order to
optimize system performance. The following example shows how to define the stack in the ASM (assembly
language) project:
﹒ROMADR
GOTO
GOTO
...
0
FPPA0
FPPA1
﹒RAMADR
WORD
WORD
...
0
// Address must be less than 0x100
// one WORD
// two WORD
Stack0 [1]
Stack1 [2]
FPPA0:
SP =
...
call
...
Stack0;
// assign Stack0 for FPPA0, one level call because of Stack0[1]
// assign Stack1 for FPPA1, two level call because of Stack1[2]
function1
FPPA1:
SP =
Stack1;
...
call
...
function2
In Mini-C project, the stack calculation is done by system software, user will not have effort on it, and the
example is shown as below:
void
FPPA0 (void)
{
...
}
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
User can check the stack assignment in the window of program disassembling, Fig. 2 shows that the status of
stack before FPP0 execution, system has calculated the required stack space and has reserved for the
program.
Fig. 2: Stack Assignment in Mini-C project
5.1.3. Single FPP mode
For traditional MCU user who does not need parallel processing capability, PMC271/PMS271 provides single
FPP mode optional to behave as traditional MCU. After single FPP mode is selected, FPP1 is always disabled
and only FPP0 is active. Fig.3 shows the timing diagram for each FPP unit, FPP1 is always disabled and only
FPP0 active. Please notice that wait and delay instructions are NOT supported when single FPP mode is
chosen.
System Clock
FPP0
Task Switch
Program Counter 0
Time
Stack Pointer 0
(M-1)th
(M+1)
(M+3)th
th (M+2)th
(M+4)th
Mth
1KW OTP
Program
Memory
Accumulator 0
Flag register 0
FPP0 active
FPP1
64 bytes
SRAM
Program Counter 1
Stack Pointer 1
Accumulator 1
Flag register 1
IO Port
FPP1 is always inactive
Fig. 3: Timing Diagram of single FPP mode
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.2. Program Memory – OTP
5.2.1. Program Memory Assignment
The OTP (One Time Programmable) program memory is used to store the program instructions to be executed.
All program codes for each FPP unit are stored in this OTP memory for both FPP0 and FPP1. The OTP
program memory may contains the data, tables and interrupt entry. After reset, the initial address for FPP0 is
‘h0 and ‘h1 for FPP1. The interrupt entry is ‘h10 if used and interrupt function is for FPP0 only, the last eight
addresses are reserved for system using, like checksum, serial number, etc. The OTP program memory for
PMC271/PMS271 is a 1Kx16 bit that is partitioned as Table 1. The OTP memory from address ‘h3F8 to ‘h3FF
is for system using, address space from ‘h002 to ‘h00F and from ‘h011 to ‘h3F7 are user program space. The
address ‘h001 is the FPP1 initial address for two FPP units mode and user program for single FPP unit mode.
In addition, the initial address of FPP0 is' h000 for two FPP units mode or single FPP unit mode.
Address
‘h000
‘h001
‘h002
•
Function
FPP0 reset – goto instruction
FPP1 reset – goto instruction
User program
•
‘h00F
‘h010
‘h011
•
User program
Interrupt entry address
User program
•
‘h3F7
‘h3F8
•
User program
System Using
•
‘h3FF
System Using
Table 1: Program Memory Organization of PMC271/PMS271
5.2.2. Example of Using Program Memory for Two FPP mode
Table 2 shows one example of using program memory which two FPP units are active.
Address
Function
000 FPP0 reset – goto instruction (goto ‘h020)
001 Begin of FPP1 program
• •
00F goto ‘h1A1 to continue FPP1 program
010 Interrupt entry address (FPP0 only)
• •
01F End of ISR
020 Begin of FPP0 user program
• •
1A0 End of FPP0 user program
1A1 Continuing FPP1 program
• •
3F7 End of FPP1 program
3F8 System Using
• •
3FF System Using
Table 2: Example of using Program Memory for two FPP units mode
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.2.3. Example of Using Program Memory for Single FPP mode
The entire user’s program memory can be assigned to FPP0 when single FPP mode is selected. Table 3
shows the example of program memory using for single FPP unit mode.
Address
000 FPP0 reset
Function
001 Begin of user program
002 user program
• •
00F goto instruction (goto ‘h020)
010 Interrupt entry address
011 ISR
• •
01F End of ISR
020 user program
• •
• •
3F7 user program
3F8 System Using
• •
3FF System Using
Table 3: Example of using Program Memory for single FPP mode
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.3. Program Structure
5.3.1. Program structure of two FPP units mode
After power-up, the program starting address of FPP0 is 0x000 and 0x001 for FPP1. The 0x010 is the entry
address of interrupt service routine, which belongs to FPP0 only. The basic firmware structure for
PMC271/PMS271 is shown as Fig. 4, the program codes of two FPP units are placed in one whole program
space. Except for the initial addresses of processing units and entry address of interrupt, the memory location
is not specially specified; the program codes of processing unit can be resided at any location no matter what
the processing unit is. After power-up, the fpp0Boot will be executed first, which will include the system
initialization and other FPP units enabled.
.romadr 0x00
// Program Begin
goto
fpp0Boot;
goto fpp1Boot;
//------Interrpt service Routine-----------------
.romadr 0x010
pushaf ;
t0sn
goto
t0sn
…
intrq.0;
ISR_PA0;
intrq.1;
//PA.0 ISR
//PB.0 ISR
goto
ISR_PB0;
//------End of ISR---------
//------ Begin of FPP0 ----------
fpp0Boot :
//--- Initialize FPP0 SP and so on…
…
fpp0Loop:
…
goto fpp0Loop:
FPP0 function
subroutine
//------ End of FPP0 --------
//------ Begin of FPP1 ----------
fpp1Boot :
//--- Initialize FPP1 SP and so on…
…
FPP1 function
subroutine
fpp1Loop:
…
goto fpp1Loop:
//--------- End of FPP1 --------
Fig. 4: Program Structure of two FPP units mode
5.3.2. Program structure of single FPP mode
After power-up, the program starting address of FPP0 is 0x000, 0x010 is the entry address of interrupt service
routine. For single FPP unit mode, the firmware structure is same as traditional MCU. After power-up, the
program will be executed from address 0x000, then continuing the program sequence.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.4. Boot Procedure
POR (Power-On-Reset) is used to reset PMC271/PMS271 when power up, however, the supply voltage may
be not stable. To ensure the stability of supply voltage after power up, it will wait 1024 ILRC clock cycles before
first instruction being executed, which is tSBP and shown in the Fig. 5.
VDD
t
SBP
POR
Program
Execution
Boot up from Power-On Reset
Fig. 5: Power Up Sequence
Fig. 6 shows the typical program flow after boot up. Please notice that the FPP1 is disabled after reset and
recommend NOT enabling FPP1 before system and FPP0 initialization.
Fig. 6: Boot Procedure
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.5. Data Memory – SRAM
Fig. 7 shows the SRAM data memory organization of PMC271/PMS271, all the SRAM data memory could be
accessed by FPP0 and FPP1 directly with 1T clock cycle, the data access can be byte or bit operation.
Besides data storage, the SRAM data memory is also served as data pointer of indirect access method and
the stack memory for all FPP units.
The stack memory for each processing unit should be independent from each other, and defined in the data
memory. The stack pointer is defined in the stack pointer register of each processing unit; the depth of stack
memory of each processing unit is defined by the user. The arrangement of stack memory fully flexible and can
be dynamically adjusted by the user.
For indirect memory access mechanism, the data memory is used as the data pointer to address the data byte.
All the data memory could be the data pointer; it’s quite flexible and useful to do the indirect memory access.
Since the data width is 8-bit, the memory size of indirect memory access is only 256 bytes only, all the 64 bytes
data memory of PMC271/PMS271 can be accessed by indirect access mechanism.
Address
000h
˙
DATA
˙
Index
˙
DATA
FPP0
FPP1
˙
FPP0 stack
˙
˙
˙
˙
DATA
˙
FPP1 stack
˙
˙
˙
˙
DATA
˙
˙
˙
˙
˙
˙
3Fh
Fig. 7: Data Memory Organization
5.6. Arithmetic and Logic Unit
Arithmetic and Logic Unit (ALU) is the computation element to operate integer arithmetic, logic, shift and other
specialized operations. The operation data can be from instruction, accumulator or SRAM data memory.
Computation result could be written into accumulator or SRAM. FPP0 and FPP1 will share ALU for its
corresponding operation.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.7. Oscillator and clock
There are three oscillator circuits provided by PMC271/PMS271: external crystal oscillator (EOSC), internal
high RC oscillator (IHRC) and internal low RC oscillator (ILRC), and these three oscillators are enabled or
disabled by registers eoscr.7, clkmd.4 and clkmd.2 independently. User can choose one of these three
oscillators as system clock source and use clkmd register to target the desired frequency as system clock to
meet different application.
Oscillator Module
EOSC
Enable/Disable
eoscr.7
IHRC
clkmd.4
ILRC
clkmd.2
5.7.1. Internal High RC oscillator and Internal Low RC oscillator
After boot-up, the IHRC and ILRC oscillators are enabled. The frequency of IHRC can be calibrated to
eliminate process variation by ihrcr register; normally it is calibrated to 16MHz. The frequency deviation can be
within 2% normally after calibration and it still drifts slightly with supply voltage and operating temperature.
Please refer to the measurement chart for IHRC frequency verse VDD and IHRC frequency verse temperature.
The frequency will vary by process, supply voltage and temperature, please refer to DC specification and do
not use for accurate timing application.
5.7.2. Chip calibration
The IHRC frequency and band-gap reference voltage may be different chip by chip due to manufacturing
variation, PMC271/PMS271 provide both the IHRC frequency calibration and band-gap calibration to eliminate
this variation, and this function can be selected when compiling user’s program and the command will be
inserted into user’s program automatically. The calibration command is shown as below:
.ADJUST_IC SYSCLK=IHRC/(p1), IHRC=(p2)MHz, VDD=(p3)V, Bandgap=(p4);
Where,
p1=2, 4, 8, 16, 32; In order to provide different system clock.
p2=16 ~ 18; In order to calibrate the chip to different frequency, 16MHz is the usually one.
p3=2.5 ~ 5.5; In order to calibrate the chip under different supply voltage.
p4= On or Off; Band-gap calibration is On or Off.
5.7.3. IHRC Frequency Calibration and System Clock
During compiling the user program, the options for IHRC calibration and system clock are shown as Table 4:
SYSCLK
○ Set IHRC / 2
○ Set IHRC / 4
○ Set IHRC / 8
○ Set IHRC / 16
○ Set IHRC / 32
○ Set ILRC
CLKMD
IHRCR
Calibrated
Calibrated
Calibrated
Description
= 34h (IHRC / 2)
= 14h (IHRC / 4)
= 3Ch (IHRC / 8)
IHRC calibrated to 16MHz, CLK=8MHz (IHRC/2)
IHRC calibrated to 16MHz, CLK=4MHz (IHRC/4)
IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)
IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)
IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)
IHRC calibrated to 16MHz, CLK=ILRC
= 1Ch (IHRC / 16) Calibrated
= 7Ch (IHRC / 32) Calibrated
= E4h (ILRC / 1)
No change
Calibrated
○ Disable
No Change IHRC not calibrated, CLK not changed, Band-gap OFF
Table 4: Options for IHRC Frequency Calibration
Usually, .ADJUST_IC will be the first command after boot up, in order to set the target operating frequency
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
whenever stating the system. The program code for IHRC frequency calibration is executed only one time that
occurs in writing the codes into OTP memory; after then, it will not be executed again. If the different option for
IHRC calibration is chosen, the system status is also different after boot. The following shows the status of
PMC271/PMS271 for different option:
(1) .ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V, Bandgap=On
After boot up, CLKMD = 0x34：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/2 = 8MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V
(2) .ADJUST_IC
SYSCLK=IHRC/4, IHRC=16MHz, VDD=3.3V, Bandgap=On
After boot up, CLKMD = 0x14：
IHRC frequency is calibrated to 16MHz@VDD=3.3V and IHRC module is enabled
System CLK = IHRC/4 = 4MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V
(3) .ADJUST_IC
SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V, Bandgap=On
After boot up, CLKMD = 0x3C：
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/8 = 2MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V
(4) .ADJUST_IC
SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.5V, Bandgap=On
After boot up, CLKMD = 0x1C：
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/16 = 1MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode, BG=1.2V
(5) .ADJUST_IC
SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V, Bandgap=Off
After boot up, CLKMD = 0x7C：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/32 = 500KHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(6) .ADJUST_IC
SYSCLK=ILRC, IHRC=16MHz, VDD=5V, Bandgap=Off
After boot up, CLKMD = 0XE4：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is disabled
System CLK = ILRC
Watchdog timer is disabled, ILRC is enabled, PA5 is input mode
(7) .ADJUST_IC
DISABLE
After boot up, CLKMD is not changed (Do nothing)：
IHRC is not calibrated and IHRC module is disabled. Bandgap is not calibrated
System CLK = ILRC
Watchdog timer is enabled, ILRC is enabled, PA5 is in input mode
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.7.4. External Crystal Oscillator
If crystal oscillator is used, a crystal or resonator is required between X1 and X2. Fig. 8 shows the hardware
connection under this application; the range of operating frequency of crystal oscillator can be from 32 KHz to
4MHz, depending on the crystal placed on; higher frequency oscillator than 4MHz is NOT supported.
(Select driving current for oscillator)
eoscr[6:5]
(Enable crystal oscillator)
eoscr.7
C1
PA7/X1
System clock = EOSC
PA6/X2
C2
The values of C1 and C2 should depend on
the specification of crystal.
Fig. 8: Connection of crystal oscillator
Besides crystal, external capacitor and options of PMC271/PMS271 should be fine tuned in eoscr (0x0a)
register to have good sinusoidal waveform. The eoscr.7 is used to enable crystal oscillator module, eoscr.6
and eoscr.5 are used to set the different driving current to meet the requirement of different frequency of crystal
oscillator:
eoscr.[6:5]=01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
eoscr.[6:5]=10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
eoscr.[6:5]=11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
Table 5 shows the recommended values of C1 and C2 for different crystal oscillator; the measured start-up
time under its corresponding conditions is also shown. Since the crystal or resonator had its own characteristic,
the capacitors and start-up time may be slightly different for different type of crystal or resonator, please refer to
its specification for proper values of C1 and C2.
Measured
Frequency
C1
C2
Conditions
Start-up time
6ms
4MHz
1MHz
32KHz
4.7pF
10pF
22pF
4.7pF
10pF
22pF
(eoscr[6:5]=11, misc.6=0)
(eoscr[6:5]=10, misc.6=0)
(eoscr[6:5]=01, misc.6=0)
11ms
450ms
Table 5: Recommend values of C1 and C2 for crystal and resonator oscillators
When using the crystal oscillator, user must pay attention to the stable time of oscillator after enabling it, the
stable time of oscillator will depend on frequency ` crystal type ` external capacitor and supply voltage. Before
switching the system to the crystal oscillator, user must make sure the oscillator is stable; the reference
program is shown as below:
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PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
void
{
FPPA0 (void)
.ADJUST_IC SYSCLK=IHRC/16, IHRC=16MHz, VDD=5V, Bandgap=On
// You can write here ‘.ADJUST_IC ......, Bandgap=Off ‘ for band-gap off
...
$
$
EOSCR Enable, 4Mhz;
T16M EOSC, /1, BIT13;
// EOSCR = 0b110_00000;
// T16 receive 2^14=16384 clocks of crystal eosc.,
// Intrq.T16 =>1, crystal eosc. Is stable
WORD
count
=
0;
stt16count;
Intrq.T16 =
0;
wait1
Intrq.T16;
0xB4;
// count from 0x0000 to 0x2000, then set INTRQ.T16
// switch system clock to EOSC;
// disable IHRC
clkmd
=
Clkmd.4 = 0;
...
}
Please notice that the crystal oscillator should be fully turned off before entering the power-down mode, in
order to avoid unexpected wakeup event. If the 32KHz crystal oscillator is used and extremely low operating
current is required, misc.6 can be set to reduce current after crystal oscillator is running normally.
5.7.5. System Clock and LVR levels
The clock source of system clock comes from EOSC, IHRC and ILRC, the hardware diagram of system clock
in the PMC271/PMS271 is shown as Fig. 9.
clkmd[7:5]
÷2, ÷4, ÷8,
÷16, ÷32, ÷64
IHRC
clock
System
clock
CLK
M
U
X
÷1, ÷2, ÷4, ÷8
EOSC
clock
ILRC
clock
÷1 (default), ÷4
Fig. 9: Options of System Clock
User can choose different operating system clock depends on its requirement; the selected operating system
clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be
selected during compilation, and the lowest LVR levels can be chosen for different operating frequencies.
Please refer to Section 4.1.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.7.6. System Clock Switching
After IHRC calibration, user may want to switch system clock to a new frequency or may switch system clock at
any time to optimize the system performance and power consumption. Basically, the system clock of
PMC271/PMS271 can be switched among IHRC, ILRC and EOSC by setting the clkmd register at any time;
system clock will be the new one after writing to clkmd register immediately. Please notice that the original
clock module can NOT be turned off at the same time as writing command to clkmd register. The examples are
shown as below and more information about clock switching, please refer to the “Help Application Note IC
Introduction Register Introduction CLKMD”.
Case 1: Switching system clock from ILRC to IHRC/2
…
// system clock is ILRC
CLKMD
CLKMD.2
…
=
=
0x34； // switch to IHRC/2，ILRC CAN NOT be disabled here
0；
// ILRC CAN be disabled at this time
Case 2: Switching system clock from ILRC to EOSC
…
// system clock is ILRC
xA6； // switch to IHRC，ILRC CAN NOT be disabled here
0； // ILRC CAN be disabled at this time
CLKMD
CLKMD.2
…
=
=
Case 3: Switching system clock from IHRC/2 to ILRC
…
// system clock is IHRC/2
0xF4； // switch to ILRC，IHRC CAN NOT be disabled here
0； // IHRC CAN be disabled at this time
CLKMD
CLKMD.4
…
=
=
Case 4: Switching system clock from IHRC/2 to EOSC
…
// system clock is IHRC/2
0XB0；// switch to EOSC，IHRC CAN NOT be disabled here
0； // IHRC CAN be disabled at this time
CLKMD
CLKMD.4
…
=
=
Case 5: Switching system clock from IHRC/2 to IHRC/4
…
CLKMD
// system clock is IHRC/2, ILRC is enabled here
0X14； // switch to IHRC/4
=
…
Case 6: System may hang if it is to switch clock and turn off original oscillator at the same time
…
// system clock is ILRC
CLKMD
=
0x30； // CAN NOT switch clock from ILRC to IHRC/2 and
// turn off ILRC oscillator at the same time
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.8. 16-bit Timer (Timer16)
PMC271/PMS271 provides a 16-bit hardware timer (Timer16) and its clock source may come from system
clock (CLK), external crystal oscillator (EOSC), internal high RC oscillator (IHRC), internal low RC oscillator
(ILRC), PA0 or PA4. Before sending clock to the 16-bit counter, a pre-scaling logic with divided-by-1, 4, 16 or
64 is selectable for wide range counting. The 16-bit counter performs up-counting operation only, the counter
initial values can be stored from data memory by issuing the stt16 instruction and the counting values can be
loaded to data memory by issuing the ldt16 instruction. The interrupt request from Timer16 will be triggered by
the selected bit which comes from bit[15:8] of this 16-bit counter, rising edge or falling edge can be optional
chosen by register integs.4. The hardware diagram of Timer16 is shown as Fig. 10.
stt16 command
DATA Memory
t16m[7:5]
t16m[4:3]
ldt16 command
CLK
IHRC
EOSC
ILRC
PA0
M
U
X
Pre-
scalar
÷
1, 4,
16, 64
16-bit
up
counter
Bit[15:0]
Data Bus
PA4
Bit[15:8]
M
U
X
To set
interrupt
request flag
or
t16m[2:0]
integs.4
Fig. 10: Hardware diagram of Timer16
When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three parameters
to define the Timer16 using; 1st parameter is used to define the clock source of Timer16, 2nd parameter is used
to define the pre-scalar and the 3rd one is to define the interrupt source.
T16M
IO_RW
0x06
$ 7~5:
STOP, SYSCLK, X, PA4_F, IHRC, EOSC, ILRC, PA0_F
/1, /4, /16, /64
// 1st par.
// 2nd par.
// 3rd par.
$ 4~3:
$ 2~0:
BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15
User can choose the proper parameters of T16M to meet system requirement, examples as below:
$
$
T16M
SYSCLK, /64, BIT15;
// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1
// if system clock SYSCLK = IHRC / 2 = 8 MHz
// SYSCLK/64 = 8 MHz/64 = 8 uS, about every 524 mS to generate INTRQ.2=1
T16M
EOSC, /1, BIT13;
// choose (EOSC/1) as clock source, every 2^14 clock cycle to generate INTRQ.2=1
// if EOSC=32768 Hz, 32768 Hz/(2^14) = 2Hz, every 0.5S to generate INTRQ.2=1
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Page 41 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
$
$
T16M
PA0, /1, BIT8;
// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1
// receiving every 512 times PA0 to generate INTRQ.2=1
T16M
STOP;
// stop Timer16 counting
5.9. Watchdog Timer
The watchdog timer (WDT) is a counter with clock coming from ILRC.
There are four different timeout periods of watchdog timer can be chosen by setting the misc register, it is:
256 ILRC period when misc[1:0]=11
16384 ILRC period when misc[1:0]=10
4096 ILRC period when misc[1:0]=01
2048 ILRC period when misc[1:0]=00 (default)
The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user
should reserve guard band for save operation. WDT can be cleared by power-on-reset or by command
wdreset at any time. When WDT is timeout, PMC271/PMS271 will be reset to restart the program execution.
The relative timing diagram of watchdog timer is shown as Fig. 11. Please notice that the clock source will be
switched to system clock (for example: 4MHz) when fast wakeup is enabled, therefore, it is recommended to
turn off the watchdog timer before enabling the fast wakeup and turn on the watchdog timer after disabling the
fast wakeup.
VDD
t
SBP
WD
Time Out
Program
Execution
Watch Dog Time Out Sequence
Fig. 11: Sequence of Watch Dog Time Out
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.10.Interrupt
There are four interrupt lines for PMC271/PMS271:
External interrupt PA0
External interrupt PB0
ADC interrupt
Timer16 interrupt
Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware
diagram of interrupt function is shown as Fig. 12. All the interrupt request flags are set by hardware and cleared
by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending
on the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable
global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it. Only
FPP0 can accept the interrupt request, other FPP unit will not be interfered by interrupt. The stack memory for
interrupt is shared with data memory and its address is specified by stack register sp. Since the program
counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can use pushaf / popaf
instructions to store or restore the values of ACC and flag register to / from stack memory.
Since the stack memory is shared with data memory, user should manipulate the memory using carefully. By
adjusting the memory location of stack point, the depth of stack pointer for every FPP unit could be fully
specified by user to achieve maximum flexibility of system.
Inten.3
Intrq.3
ADC done
Set Flag
Inten.2
T16 output
Integs.4
PB0
Intrq.2
Edge Select
& Set Flag
Interrupt
to FPP0
Inten.1
Intrq.1
Edge Select
& Set Flag
engint & disgint
Integs[3:2]
PA0
Inten.0
Intrq.0
Edge Select
& Set Flag
Integs[1:0]
Fig. 12: Hardware diagram of Interrupt controller
Once the interrupt occurs, its operation will be:
The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x010.
During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Note: Even if INTEN=0, INTRQ will be still triggered by the interrupt source.
After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will be:
The program counter will be restored automatically from the stack memory specified by register sp.
New sp will be updated to sp-2.
Global interrupt will be enabled automatically.
The next instruction will be the original one before interrupt.
User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and four
bytes for two levels interrupt. For interrupt operation, the following sample program shows how to handle the
interrupt, noticing that it needs four bytes stack memory to handle interrupt and pushaf.
void
{
FPPA0
(void)
...
$
INTEN PA0;
// INTEN =1; interrupt request when PA0 level changed
// clear INTRQ
INTRQ
ENGINT
...
=
0;
// global interrupt enable
DISGINT
...
// global interrupt disable
}
void Interrupt (void)
// interrupt service routine
{
PUSHAF
// store ALU and FLAG register
// If INTEN.PA0 will be opened and closed dynamically,
// user can judge whether INTEN.PA0 =1 or not.
// Example: If (INTEN.PA0 && INTRQ.PA0) {…}
// If INTEN.PA0 is always enable,
// user can omit the INTEN.PA0 judgement to speed up interrupt service routine.
If (INTRQ.PA0)
{
// Here for PA0 interrupt service routine
INTRQ.PA0 = 0;
...
// Delete corresponding bit (take PA0 for example)
}
...
// X : INTRQ = 0;
// It is not recommended to use INTRQ = 0 to clear all at the end of
// the interrupt service routine.
// It may accidentally clear out the interrupts that have just occurred
// and are not yet processed.
POPAF
// restore ALU and FLAG register
}
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.11.Power-Save and Power-Down
There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down
modes. ON mode is the state of normal operation with all functions ON, Power-save mode (“stopexe”) is the
state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is used to
save power deeply. Therefore, Power-save mode is used in the system which needs low operating power with
wake-up occasionally and Power-Down mode is used in the system which needs power down deeply with
seldom wake-up. Fig. 13 shows the differences in oscillator modules between Power-Save mode (“stopexe”)
and Power-Down mode (“stopsys”).
Differences in oscillator modules between STOPSYS and STOPEXE
IHRC
Stop
ILRC
Stop
EOSC
Stop
STOPSYS
STOPEXE
No Change
No Change
No Change
Fig. 13: Differences in oscillator modules between STOPSYS and STOPEXE
5.11.1. Power-Save mode (“stopexe”)
Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all the
oscillator modules active. For CPU, it stops executing; however, for Timer16, counter keep counting if its clock
source is not the system clock. The wake-up sources for “stopexe” can be IO-toggle or Timer16 counts to the
set values when clock sources of Timer16 come from IHRC, ILRC or EOSC modules. Wake-up from input
pins can be considered as a continuation of normal execution, the detail information for Power-Save mode
shows below:
IHRC and EOSC oscillator modules: No change, keep active if it was enabled
ILRC oscillator modules: must remain enabled, need to start with ILRC when be wakening up
System clock: Disable, therefore, CPU stops execution
OTP memory is turned off
Timer16: Stop counting if system clock is selected or the corresponding oscillator module is disabled;
otherwise, it keeps counting.
Wake-up sources: IO toggle in digital mode (PxDIER bit is 1) or Timer16.
The watchdog timer must be disabled before issuing the “stopexe” command, the example is shown as
below:
CLKMD.En_WatchDog
stopexe;
….
=
0;
// disable watchdog timer
// power saving
Wdreset;
CLKMD.En_WatchDog
=
1;
// enable watchdog timer
Another example shows how to use Timer16 to wake-up from “stopexe”:
$ T16M IHRC, /1, BIT8
…
// Timer16 setting
WORD
STT16
stopexe;
…
count
count;
=
0;
The initial counting value of Timer16 is zero and the system will be waken up after the Timer16 counts 256
IHRC clocks.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.11.2. Power-Down mode (“stopsys”)
Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using the
“stopsys” instruction, this chip will be put on Power-Down mode directly. The internal low frequency RC
oscillator must be enabled before entering the Power-Down mode, means that bit 2 of register clkmd (0x03)
must be set to high before issuing “stopsys” command in order to resume the system when wakeup. The
following shows the internal status of PMC271/PMS271 in detail when “stopsys” command is issued:
All the oscillator modules are turned off
Enable internal low RC oscillator (set bit 2 of register clkmd)
OTP memory is turned off
The contents of SRAM and registers remain unchanged
Wake-up sources: IO toggle in digital mode (PxDIER bit is 1)
Wake-up from input pins can be considered as a continuation of normal execution. To minimize power
consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The
reference sample program for power down is shown as below:
CMKMD
CLKMD.4
…
=
=
0xF4;
0;
//
//
Change clock from IHRC to ILRC
disable IHRC
while (1)
{
STOPSYS;
//
//
//
enter power-down
if (…) break;
if wakeup happen and check OK, then return to high speed,
else stay in power-down mode again.
}
CLKMD
=
0x34;
//
Change clock from ILRC to IHRC/2
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.11.3. Wake-up
After entering the Power-Down or Power-Save modes, the PMC271/PMS271 can be resumed to normal
operation by toggling IO pins, Timer16 interrupt is available for Power-Save mode ONLY. Fig. 14 shows the
differences in wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
Yes
T16 Interrupt
STOPSYS
STOPEXE
No
Yes
Yes
Fig. 14: Differences in wake-up sources between Power-Save mode and Power-Down mode
When using the IO pins to wake-up the PMC271/PMS271, registers padier and pbdier should be properly set
to enable the wake-up function for every corresponding pin. The wake-up time for normal wake-up is about
1024 ILRC clocks counting from wake-up event; fast wake-up can be selected to reduce the wake-up time by
misc register. For fast wake-up mechanism, the wake-up time is 128 system clocks from IO toggling if
STOPEXE was issued, and 128 system clocks plus oscillator (IHRC or ILRC) stable time from IO toggling if
STOPSYS was issued. The oscillator stable time is the time for IHRC or ILRC oscillator from power-on,
depending on which oscillator is used as system clock source. Please notice that the fast wake-up will turn off
automatically when EOSC is selected as system clock.
wake-up
mode
system
Suspend mode
wake-up time (tWUP) from IO toggle
clock source
STOPEXE
suspend
128 * TSYS,
fast wake-up
IHRC or ILRC
Where TSYS is the time period of system clock
128 TSYS + TSIHRC
;
STOPSYS
suspend
fast wake-up
IHRC
Where TSIHRC is the stable time of IHRC from
power-on.
128 TSYS + TSILRC
;
STOPSYS
suspend
fast wake-up
fast wake-up
ILRC
Where TSILRC is the stable time of ILRC from
power-on.
STOPSYS or
STOPEXE
suspend
1024 * TILRC
,
EOSC
Where TILRC is the clock period of ILRC
STOPEXE
suspend
normal
wake-up
normal
1024 * TILRC
Where TILRC is the clock period of ILRC
1024 * TILRC
Where TILRC is the clock period of ILRC
,
Any one
Any one
STOPSYS
suspend
,
wake-up
Fig. 15: Wake-up time matching
Please notice that the clock source will be switched to system clock (for example: 4MHz) when fast wakeup is
enabled, therefore, it is recommended to turn off the watchdog timer before enabling the fast wakeup and
turn on the watchdog timer after disabling the fast wakeup.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.12.IO Pins
Other than PA5, all the pins can be independently set into two states output or input by configuring the data
registers (pa, pb), control registers (pac, pbc) and pull-up registers (paph, pbph). All these pins have
Schmitt-trigger input buffer and output driver with CMOS level. When it is set to output low, the pull-up resistor
is turned off automatically. If user wants to read the pin state, please notice that it should be set to input mode
before reading the data port; if user reads the data port when it is set to output mode, the reading data comes
from data register, NOT from IO pad. As an example, Table 6 shows the configuration table of bit 0 of port A.
The hardware diagram of IO buffer is also shown as Fig. 16.
pa.0 pac.0 paph.0
Description
Input without pull-up resistor
X
X
0
1
1
0
0
1
1
1
0
1
X
0
1
Input with pull-up resistor
Output low without pull-up resistor
Output high without pull-up resistor
Output high with pull-up resistor
Table 6: PA0 Configuration Table
RD pull-high latch
WR pull-high latch
D
D
D
Q
(weak P-MOS)
pull-high
latch
Q
Data
latch
Q1
PAD
WR data latch
RD control latch
Q
WR control latch
Control
latch
M
U
X
RD Port
Data Bus
padier.x or pbdier.x
Wakeup module
Interrupt module
(PA0,PB0 only)
Analog Module
Fig. 16: Hardware diagram of IO buffer
Other than PA5, all the IO pins have the same structure; PA5 can is open-drain ONLY when setting to output
mode (without Q1). The corresponding bits in registers padier / pbdier should be set to low to prevent leakage
current for those pins are selected to be analog function. When PMC271/PMS271 is put in power-down or
power-save mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins
needed to wake-up system must be set to input mode and set the corresponding bits of registers padier and
pbdier to high. The same reason, padier.0 should be set high when PA0 is used as external interrupt pin and
pbdier.0 for PB0.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.13. Reset and LVR
5.13.1. Reset
There are many causes to reset the PMC271/PMS271, once reset is asserted, most of all the registers in
PMC271/PMS271 will be set to default values, When reset comes from WDT timeout, gdio register (IO
address 0x7) keeps the same value, system should be restarted once abnormal cases happen, or by jumping
program counter to address ’h0. The data memory is in uncertain state when reset comes from power-up and
LVR; however, the content will be kept when reset comes from PRST# pin or WDT timeout.
5.13.2. LVR reset
By code option, there are many different levels of LVR for reset; usually, user selects LVR reset level to be in
conjunction with operating frequency and supply voltage.
5.14.LCD Half VDD Bias Voltage
This function is used to generate half VDD bias voltage for LCD applications; however, it
is NOT suitable for
those in dire need of power saving products. This function is controlled by bit 4 of misc register, the
PMC271/PMS271 will generate half VDD voltage on PA4 PA3 PA2 PA1 pins after enabling this function.
When these selected pins are going to have half VDD voltage function, user must program the PA4 PA3
PA2 PA1 pins to input mode and PMC271/PMS271 will generate half VDD voltage to the corresponding pin
automatically. If user
、
、
、
、
、
、
wants to output VDD
、
1/2VDD
then output-high (VDD)
17 shows how to use this Function:
、GND three levels voltage, the corresponding pins must be
set half VDD bias voltage and
、input (VDD/2)
、output-low (GND) correspondingly. Fig.
VDD
VDD/2
GND
Pin set to output high
Pin set to input
Pin set to output low
Fig. 17: Using VDD/2 bias voltage generator
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.15.Analog-to-Digital Conversion (ADC) module
adcm[3:0]
adcc [5:2]
ADC clock
selection
1001
1000
system clock
PB0/AD0
PB1/AD1
PB2/AD2
ADCCLK
0111
0110
0101
0100
0011
0010
VIN
signal for conversion
PB3/AD3
PB7/AD4
PA3/AD5
PA4/AD6
A/D
Converter
VDD
Reference
High voltage
Reference
Low voltage
adcrhc[7:4]
MUX
GND
1.2 volt
band-gap
adcrhc[7:4]
adcr[7:0]
1.2 volt
voltage
generator
adcrhc[0]
PB2/AD2
Fig. 18: ADC Block Diagram
There are eight input channels for the analog-to-digital conversion module; it allows conversion of an analog
input signal to a corresponding 8-bit digital number. The hardware block diagram of ADC module is shown as
Fig.18; the output of the sample and hold is the input into the converter which generates the result via
successive approximation. The ADC reference low voltage is always GND.
There are six registers for the ADC module, which are:
ADC Control Register (adcc)
ADC Mode Register (adcm)
ADC Result Register (adcr)
ADC Reference High Control Register (adcrhc)
Port A Digital Input Disable Register (padier)
Port B Digital Input Disable Register (pbdier)
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PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
After the ADC module has been configured as desired and the selected channel has been configured as
analog input. The selected signal should be acquired before conversion, and the AD conversion can be started
after the acquisition time has elapsed. The following steps should be followed to do the AD conversion:
(1) Configure the ADC module:
Configure the voltage reference high by adcrhc register
Select the ADC input channel by adcc register
Configure the AD conversion clock by adcm register
Configure the selected pin as analog input by padier and pbdier registers
Enable the ADC module by adcc register
(2) Configure interrupt for ADC: (if desired)
Clear the ADC interrupt request flag in bit 3 of intrq register
Enable the ADC interrupt request in bit 3 of inten register
Enable global interrupt by issuing engint command
(3) Start AD conversion:
Set ADC process control bit in the adcc register to start the conversion (set1 adcc.6)
(4) Wait for the completion flag of AD conversion, by either:
Waiting for the completion flag by using command “wait1 addc.6”; or
Waiting for the ADC interrupt.
(5) Read the ADC result registers:
Read adcr the result registers
(6) For next conversion, goto step 1 or step 2 as required.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.15.1. The input requirement for AD conversion
For the AD conversion to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed
to fully charge to the voltage reference high level and discharge to the voltage reference low level. The
analog input model is shown as Fig. 19, the signal driving source impedance (Rs) and the internal sampling
switch impedance (Rss) will affect the required time to charge the capacitor CHOLD directly. The internal
sampling switch impedance may vary with ADC supply voltage; the signal driving source impedance will
affect accuracy of analog input signal. User must ensure the measured signal is stable before sampling;
therefore, the maximum signal driving source impedance is highly dependent on the frequency of signal to
be measured. The recommended maximum impedance for analog driving source is about 15KΩ under
500KHz input frequency and 8-bit resolution requirements, and 15MΩ under 500Hz input frequency and
8-bit resolution.
Fig. 19: Analog Input Model
Before starting the AD conversion, the minimum signal acquisition time should be met for the selected
analog input signal. The signal acquisition time (TACQ) of ADC in PMC271/PMS271 series is fixed to one
clock period of ADCLK; the selection of ADCLK must be met the minimum signal acquisition time.
5.15.2. ADC clock selection
The clock of ADC module (ADCLK) can be selected by adcm register; there are 8 possible options for
ADCLK from CLK÷1 to CLK÷128 (CLK is the system clock). Due to the signal acquisition time TACQ is one
clock period of ADCLK, the ADCLK must meet that requirement. The recommended ADC clock is to operate
at 500KHz.
5.15.3. AD conversion
The process of AD conversion starts from setting START/DONE bit (bit 6 of adcc) to high, the
START/DONE flag for read will be cleared automatically, then converting analog signal bit by bit and finally
setting START/DONE high to indicate the completion of AD conversion. If ADCLK is selected, TADCLK is the
period of ADCLK and the AD conversion time will be 12 TADCLK
.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
5.15.4. Configuring the analog pins
The seven external analog input signals for ADC shared the same pins with port A or port B. To avoid
leakage current at the digital circuit, those pins defined for analog input should be set to be analog input via
padier or pbdier register. For those defined analog input pins, the value will be 0 when reading port A or
port B.
5.15.5 Using the ADC
The following example shows how to use ADC with PB0~PB3.
First, defining the selected pins:
PBC
PBPH
PBDIER
=
=
=
0B_XXXX_0000;
0B_XXXX_0000;
0B_XXXX_0000;
// PB0 ~ PB3 as Input
// PB0~PB3 without pull-up resistor
// PB0 ~ PB3 digital input is disabled
Next, setting ADCC register, example as below:
$
$
$
ADCC Enable, PB3;
ADCC Enable, PB2;
ADCC Enable, PB0;
// set PB3 as ADC input
// set PB2 as ADC input
// set PB0 as ADC input
Next, setting ADCM register, example as below:
$
$
ADCM 8BIT, /16;
ADCM 8BIT, /8;
// recommend /16 @System Clock=8MHz
// recommend /8 @System Clock=4MHz
Then, start the ADC conversion:
AD_START
while(!AD_DONE) NULL;
=
1;
// start ADC conversion
// wait ADC conversion result
Finally, it can read ADC result when AD_DONE is high:
BYTE
Data
Data;
ADCR
=
The ADC can be disabled by using the following method:
ADCC Disable;
$
or
ADCC
=
0;
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PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6. IO Registers
6.1. ACC Status Flag Register (flag), IO address = 0x00
Bit Reset R/W
Description
7 - 4
3
-
-
-
Reserved. These four bits are “1” when read.
R/W OV (Overflow). This bit is set whenever the sign operation is overflow.
AC (Auxiliary Carry). There are two conditions to set this bit, the first one is carry out of low
R/W nibble in addition operation, and the other one is borrow from the high nibble into low nibble
in subtraction operation.
2
-
C (Carry). There are two conditions to set this bit, the first one is carry out in addition
R/W operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
1
0
-
-
Z (Zero). This bit will be set when the result of arithmetic or logic operation is zero;
R/W
Otherwise, it is cleared.
6.2. FPP unit Enable Register (fppen), IO address = 0x01
Bit Reset R/W
Description
7 - 2
-
-
Reserved. Please keep 0.
1
0
0
1
W/R FPP1 enable. This bit is used to enable FPP1. 0 / 1: disable / enable
W/R FPP0 enable. This bit is used to enable FPP0. 0 / 1: disable / enable
6.3. Stack Pointer Register (sp), IO address = 0x02
Bit Reset R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer. Please notice that bit 0 should be kept 0 due to program counter is 16 bits.
7 - 0 R/W
-
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PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6.4. Clock Mode Register (clkmd), IO address = 0x03
Bit
Reset R/W
Description
System clock selection:
Type 0, clkmd[3]=0
Type 1, clkmd[3]=1
000: IHRC/4
001: IHRC/2
010: reserved
011: EOSC/4
100: EOSC/2
101: EOSC
000: IHRC/16
001: IHRC/8
010: reserved
011: IHRC/32
100: IHRC/64
101: EOSC/8
11x: reserved.
7 - 5
111
R/W
110: ILRC/4
111: ILRC (default)
4
3
1
0
R/W IHRC oscillator Enable. 0 / 1: disable / enable
Clock Type Select. This bit is used to select the clock type in bit [7:5].
RW
0 / 1: Type 0 / Type 1
2
1
0
1
1
0
R/W ILRC Enable. 0 / 1: disable / enable
R/W Watch Dog Enable. 0 / 1: disable / enable
R/W Pin PA5/PRST# function. 0 / 1: PA5 / PRST#.
6.5. Interrupt Enable Register (inten), IO address = 0x04
Bit Reset R/W
Description
7 - 4
-
-
-
-
-
R/W Reserved.
3
2
1
0
R/W Enable interrupt from ADC. 0 / 1: disable / enable.
R/W Enable interrupt from Timer16 overflow. 0 / 1: disable / enable.
R/W Enable interrupt from PB0. 0 / 1: disable / enable.
R/W Enable interrupt from PA0. 0 / 1: disable / enable.
6.6. Interrupt Request Register (intrq), IO address = 0x05
Bit Reset R/W
Description
7 - 4
-
R/W Reserved.
Interrupt Request from ADC, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
3
-
R/W
R/W
R/W
R/W
Interrupt Request from Timer16, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
2
1
0
-
-
-
Interrupt Request from pin PB0, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PA0, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
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Page 55 of 90
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PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6.7. Timer 16 mode Register (t16m), IO address = 0x06
Bit Reset R/W
Description
Timer Clock source selection
000: Timer 16 is disabled
001: CLK (system clock)
010: reserved
7 - 5
4 - 3
2 - 0
000
R/W 011: PA4 falling edge (from external pin)
100: IHRC
101: EOSC
110: ILRC
111: PA0 falling edge (from external pin)
Internal clock divider.
00: ÷1
00
R/W 01: ÷4
10: ÷16
11: ÷64
Interrupt source selection. Interrupt event happens when selected bit goes high.
0 : bit 8 of Timer16
1 : bit 9 of Timer16
2 : bit 10 of Timer16
R/W 3 : bit 11 of Timer16
4 : bit 12 of Timer16
5 : bit 13 of Timer16
6 : bit 14 of Timer16
7 : bit 15 of Timer16
000
6.8. General Data register for IO (gdio), IO address = 0x07
Bit Reset R/W
Description
General data for IO. This port is the general data buffer in IO space and cleared only when
POR, LVR or pin PRST# is active, NOT cleared by watch-dog timeout reset. It can perform
7 - 0
00
R/W the IO operation, like wait0 gdio.x, wait1 gdio.x and tog gdio.x to take the replace of
operations which instructions are supported in memory space (ex: wait1 mem; wait0 mem;
tog mem).
6.9. External Oscillator setting Register (eoscr, write only), IO address = 0x0a
Bit
Reset R/W
Description
7
0
WO Enable crystal oscillator. 0 / 1 : Disable / Enable
External crystal oscillator selection.
00 : reserved
6 - 5
00
WO 01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator
10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
4 - 1
0
-
-
Reserved. Please keep 0.
0
WO Power-down the Band-gap and LVR hardware modules. 0 / 1: normal / power-down.
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Page 56 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6.10.IHRC oscillator control Register (ihrcr, write only), IO address = 0x0b
Bit
Reset
R/W
Description
Bit [7:0] of internal high RC oscillator for frequency calibration.
For system using only, please user do NOT write this register.
7 - 0
-
WO
6.11.Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
Reset
R/W
Description
7 - 5
-
-
Reserved. Please keep 0.
Timer16 edge selection.
4
0
WO 0 : rising edge to trigger interrupt
1 : falling edge to trigger interrupt
PB0 edge selection.
00 : both rising edge and falling edge to trigger interrupt
WO 01 : rising edge to trigger interrupt
10 : falling edge to trigger interrupt
11 : reserved.
3 - 2
00
PA0 edge selection.
00 : both rising edge and falling edge to trigger interrupt
WO 01 : rising edge to trigger interrupt
10 : falling edge to trigger interrupt
11 : reserved.
1 - 0
00
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Page 57 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6.12.Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset
R/W
Description
Enable PA7 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator
is used. If this bit is set to low, PA7 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PA6 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator
is used. If this bit is set to low, PA6 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PA5 wake-up event. 1 / 0 : enable / disable.
7
1
WO
6
5
4
1
1
1
WO
WO
WO
This bit can be set to low to disable wake-up from PA5 toggling.
Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.
Enable PA4 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PA4 is assigned as AD input to prevent leakage
current. If this bit is set to low, PA4 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PA3 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PA3 is assigned as AD input to prevent leakage
current. If this bit is set to low, PA3 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PA2 wake-up event. 1 / 0 : enable / disable.
3
1
WO
2
1
1
1
WO
WO
This bit can be set to low to disable wake-up from PA2 toggling.
Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.
Enable PA1 wake-up event. 1 / 0 : enable / disable.
This bit can be set to low to disable wake-up from PA1 toggling.
Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.
Enable PA0 wake-up event and interrupt request. 1 / 0 : enable / disable.
This bit can be set to low to disable wake-up from PA0 toggling and interrupt request
from this pin.
0
1
WO
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6.13.Port B Digital Input Enable Register (pbdier), IO address = 0x0e
Bit
Reset
R/W
Description
Enable PB7 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PB7 is assigned as AD input to prevent leakage
current. If this bit is set to low, PB7 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PB6 wake-up event. 1 / 0 : enable / disable.
7
1
WO
6
5
4
1
1
1
WO
WO
WO
This bit can be set to low to disable wake-up from PB6 toggling.
Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.
Enable PB5 wake-up event. 1 / 0 : enable / disable.
This bit can be set to low to disable wake-up from PB5 toggling.
Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.
Enable PB4 wake-up event. 1 / 0 : enable / disable.
This bit can be set to low to disable wake-up from PB4 toggling.
Note: For ICE emulation, wakeup is disabled when this bit is “1” and “0” is enabled.
Enable PB3 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PB3 is assigned as AD input to prevent leakage
current. If this bit is set to low, PB3 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PB2 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PB2 is assigned as AD input to prevent leakage
current. If this bit is set to low, PB2 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PB1 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PB1 is assigned as AD input to prevent leakage
current. If this bit is set to low, PB1 can NOT be used to wake-up the system.
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
Enable PB0 digital input, wake-up event and interrupt request. 1 / 0 : enable / disable.
This bit should be set to low when PB0 is assigned as AD input to prevent leakage
current. If this bit is set to low, PB0 can NOT be used to wake-up the system and
interrupt request from this pin.
3
2
1
1
1
1
WO
WO
WO
0
1
WO
Note: For ICE emulation, the function is disabled when this bit is “1” and “0” is enabled.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 59 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6.14.Port A Data Registers (pa), IO address = 0x10
Bit Reset R/W
Description
7 - 0 8’h00 R/W Data registers for Port A.
6.15.Port A Control Registers (pac), IO address = 0x11
Bit Reset R/W
Description
Port A control registers. This register is used to define input mode or output mode for each
corresponding pin of port A. 0 / 1: input / output.
7 - 0 8’h00 R/W
6.16.Port A Pull-up Registers (paph), IO address = 0x12
Bit Reset R/W
Description
Port A pull-up registers. This register is used to enable the internal pull-up device on each
7 - 0 8’h00 R/W corresponding pin of port A. 0 / 1 : disable / enable
Please note that the PA5 does not have pull-up resistor.
6.17.Port B Data Registers (pb), IO address = 0x14
Bit Reset R/W
Description
7 - 0 8’h00 R/W Data registers for Port B.
6.18.Port B Control Registers (pbc), IO address = 0x15
Bit Reset R/W
Description
Port B control registers. This register is used to define input mode or output mode for each
corresponding pin of port B. 0 / 1: input / output
7 - 0 8’h00 R/W
6.19.Port B Pull-up Registers (pbph), IO address = 0x16
Bit Reset R/W
Description
Port B pull-up registers. This register is used to enable the internal pull-up device on each
corresponding pin of port B. 0 / 1 : disable / enable
7 - 0 8’h00 R/W
6.20.ADC Control Register (adcc), IO address = 0x20
Bit Reset R/W
Description
7
6
0
0
R/W Enable ADC function. 0/1: Disable/Enable.
ADC process control bit.
R/W Write “1” to start AD conversion, and the completion flag is cleared automatically;
Read “1” to indicate the completion of AD conversion.
Channel selector. These four bits are used to select input signal for AD conversion.
0000:PB0
0001:PB1
0010:PB2
0011:PB3.
5 - 2 0000 R/W
0111:PB7
1000:PA3
1001:PA4
1111: 1.20V band-gap reference voltage
Others: reserved
1 - 0
-
-
Reserved, please keep 0.
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Page 60 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6.21.ADC Mode Register (adcm, write only), IO address = 0x21
Bit Reset R/W
Description
7 - 5
-
-
Reserved
ADC clock source selection.
0000: CLK÷1
0001:CLK÷2
0010:CLK÷4
0011:CLK÷8
4 - 1 0000 WO 0100:CLK÷16
0101:CLK÷32
0110:CLK÷64
0111:CLK÷128,
Others: reserved.
Where, CLK is the system clock.
Reserved
0
-
-
6.22.ADC Result Register (adcr, read only), IO address = 0x22
Bit Reset R/W
Description
7 - 0 RO These eight read-only bits will be the bit [7:0] of AD conversion result.
-
6.23.ADC Reference High Control Register (adcrhc), IO address = 0x1c
Bit
7:4
3:1
Reset
0000
-
R/W
WO
-
Description
ADC Reference high selection:
0000: Reference high is VDD voltage level.
0001: Reference high is PB1 voltage level.
Note: PB1≦(2/3)VDD is required to keep the accuracy of AD conversion.
0010: Reference high is band-gap voltage level.
Others: reserved, please keep as 0.
Reserved. (please keep as 0)
Enable ADC Reference high voltage output to PB2.
0 / 1 : disable / enabled
Notes:
(1) If this bit is enabled, must set PB2 as input mode and NOT drive this pin externally.
(2) The ADC reference high which is sent to PB2 comes from PB1 input or band-gap
reference voltage only, please see the block diagram.
(3) If band-gap reference voltage is sent to PB2 and AD conversion input signal at the
same time, the conversion result may not be correct, please do NOT use
simultaneously.
0
0
WO
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
6.24. RESET Status Register (rstst), IO address = 0x25
Reset
Bit
R/W
Description
(POR only)
7 - 4
-
-
Reserved. Please don’t use..
MCU reset from external reset pin (PA5)? This bit is set to high whenever reset
3
2
1
0
-
-
-
-
R/W occurs from PA5 pin, and reset only when writing “0” to clear this bit or POR
(power-on-reset) happens. 0 / 1 : No / Yes.
VDD had been lower than 4V? This bit is set to high whenever VDD under 4V and
R/W reset only when writing “0” to clear this bit or POR (power-on-reset) happens.
0 / 1 : No / Yes.
VDD had been lower than 3V? This bit is set to high whenever VDD under 3V and
R/W reset only when writing “0” to clear this bit or POR (power-on-reset) happens.
0 / 1 : No / Yes.
VDD had been lower than 2V? This bit is set to high whenever VDD under 2V and
R/W reset only when writing “0” to clear this bit or POR (power-on-reset) happens.
0 / 1 : No / Yes.
6.25. MISC Register (misc), IO address = 0x3b
Bit
Reset
R/W
Description
7
0
-
Reserved
Enable extremely low current for 32KHz crystal oscillator AFTER oscillation.
WO 0: Normal.
1: Low driving current for 32KHz crystal oscillator.
6
0
Enable fast Wake-up. Fast wake-up is NOT supported when EOSC is enabled.
0: Normal wake-up.
The wake-up time is 1024 ILRC clocks
1: Fast wake-up. (for
The wake-up time is 128 CLKs (system clock) + oscillator stable time.
If wake-up from STOPEXE suspend, there is no oscillator stable time;
If wake-up from STOPSYS suspend, it will be IHRC or ILRC stable time from
power-on.
5
4
0
0
WO
Please notice that the clock source will be switched to system clock
(for example: 4MHz) when fast wakeup is enabled, therefore,
it is recommended to turn off the watchdog timer before enabling the fast wakeup
and turn on the watchdog timer after disabling the fast wakeup.
Enable to generate half VDD on PA0/PA1/PA2/PA3 pins.
0 / 1 : Disable / Enable
WO
Recover time from LVR reset.
3
2
0
0
WO 0: Normal. The system will take about 1024 ILRC clocks to boot up from LVR reset.
1: Fast. The system will take about 64 ILRC clocks to boot up from LVR reset.
WO Disable LVR function.0 / 1 : Enable / Disable
Watch dog time out period
00: 2048 ILRC clock period
1 - 0
00
WO 01: 4096 ILRC clock period
10: 16384 ILRC clock period
11: 256 ILRC clock period
©Copyright 2018, PADAUK Technology Co. Ltd
Page 62 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7. Instructions
Symbol
Description
ACC
a
Accumulator
Accumulator
Stack pointer
sp
flag
I
ACC status flag register
Immediate data
&
Logical AND
|
Logical OR
←
^
Movement
Exclusive logic OR
+
Add
－
〜
〒
OV
Z
Subtraction
NOT (logical complement, 1’s complement)
NEG (2’s complement)
Overflow (The operational result is out of range in signed 2’s complement number system)
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction
in unsigned number system)
C
AC
Auxiliary Carry (If there is a carry out from low nibble after the result of ALU operation, this bit is
set to 1)
pc0
pc1
Program counter for FPP0
Program counter for FPP1
©Copyright 2018, PADAUK Technology Co. Ltd
Page 63 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7.1. Data Transfer Instructions
mov
mov
mov
mov
mov
nmov
a, I
Move immediate data into ACC.
Example: mov a, 0x0f;
Result: a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
M, a
a, M
Move data from ACC into memory
Example: mov
MEM, a;
Result: MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
a, MEM ;
Result: a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, IO
Move data from IO into ACC
Example: mov
a, pa ;
Result: a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
IO, a
M, a
Move data from ACC into IO
Example: mov
Result: pb ← a
pb, a;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Take the negative logic (2’s complement) of ACC to put on memory
Example: mov
MEM, a;
Result: MEM ← 〒a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
a, 0xf5 ;
ram9, a;
// ACC is 0xf5
nmov
// ram9 is 0x0b, ACC is 0xf5
------------------------------------------------------------------------------------------------------------------------
Take the negative logic (2’s complement) of memory to put on ACC
nmov
a, M
Example: mov
a, MEM ;
Result: a ← 〒MEM; Flag Z is set when 〒MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
nmov
a, 0xf5 ;
ram9, a ;
a, ram9 ;
// ram9 is 0xf5
// ram9 is 0xf5, ACC is 0x0b
------------------------------------------------------------------------------------------------------------------------
©Copyright 2018, PADAUK Technology Co. Ltd
Page 64 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
ldtabh index
Load high byte data in OTP program memory to ACC by using index as OTP address. It needs
2T to execute this instruction.
Example: ldtabh index;
Result:
a ← {bit 15~8 of OTP [index]};
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
ROMptr ;
// declare a pointer of ROM in RAM
mov
mov
mov
mov
…
a, la@TableA ;
lb@ROMptr, a ;
a, ha@TableA ;
// assign pointer to ROM TableA (LSB)
// save pointer to RAM (LSB)
// assign pointer to ROM TableA (MSB)
hb@ROMptr, a ; // save pointer to RAM (MSB)
ROMptr ; // load TableA MSB to ACC (ACC=0X02)
dc 0x0234, 0x0042, 0x0024, 0x0018 ;
ldtabh
….
TableA :
------------------------------------------------------------------------------------------------------------------------
ldtabl index
Load low byte data in OTP to ACC by using index as OTP address. It needs 2T to execute this
instruction.
Example: ldtabl index;
Result:
a ← {bit7~0 of OTP [index]};
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
ROMptr ;
// declare a pointer of ROM in RAM
mov
mov
mov
mov
…
a, la@TableA ;
// assign pointer to ROM TableA (LSB)
lb@ROMptr, a ; // save pointer to RAM (LSB)
a, ha@TableA ; // assign pointer to ROM TableA (MSB)
hb@ROMptr, a ; // save pointer to RAM (MSB)
ldtabl
….
ROMptr ;
// load TableA LSB to ACC (ACC=0x34)
TableA :
dc
0x0234, 0x0042, 0x0024, 0x0018 ;
------------------------------------------------------------------------------------------------------------------------
©Copyright 2018, PADAUK Technology Co. Ltd
Page 65 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
ldt16 word
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
clear
clear
stt16
…
lb@ T16val ;
hb@ T16val ;
T16val ;
// clear T16val (LSB)
// clear T16val (MSB)
// initial T16 with 0
set1
…
t16m.5 ;
// enable Timer16
set0
ldt16
….
t16m.5 ;
T16val ;
// disable Timer 16
// save the T16 counting value to T16val
------------------------------------------------------------------------------------------------------------------------
Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
stt16 word
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
T16val ;
// declare a RAM word
mov
mov
mov
mov
stt16
…
a, 0x34 ;
lb@ T16val , a ; // move 0x34 to T16val (LSB)
a, 0x12 ;
hb@ T16val , a ; // move 0x12 to T16val (MSB)
T16val ;
// initial T16 with 0x1234
----------------------------------------------------------------------------------------------------------------------
©Copyright 2018, PADAUK Technology Co. Ltd
Page 66 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
idxm a, index Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
idxm
a, RAMIndex ; // mov memory data in address 0x5B to ACC
------------------------------------------------------------------------------------------------------------------------
Idxm index, a Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
word
…
RAMIndex ;
// declare a RAM pointer
mov
mov
mov
mov
…
a, 0x5B ;
// assign pointer to an address (LSB)
// save pointer to RAM (LSB)
lb@RAMIndex, a ;
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
hb@RAMIndex, a ; // save pointer to RAM (MSB)
mov
idxm
a, 0xA5 ;
RAMIndex, a ;
// mov 0xA5 to memory in address 0x5B
------------------------------------------------------------------------------------------------------------------------
©Copyright 2018, PADAUK Technology Co. Ltd
Page 67 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
xch
M
Exchange data between ACC and memory
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
pushaf
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
.romadr 0x10 ;
// ISR entry address
pushaf ;
…
// put ACC and flag into stack memory
// ISR program
…
// ISR program
popaf ;
reti ;
// restore ACC and flag from stack memory
------------------------------------------------------------------------------------------------------------------------
Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
popaf
Result:
sp ← sp - 2
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
;
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7.2. Arithmetic Operation Instructions
add
add
add
a, I
Add immediate data with ACC, then put result into ACC
Example: add a, 0x0f ;
Result: a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
M, a
Add data in memory with ACC, then put result into ACC
Example: add
a, MEM ;
Result: a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into memory
Example: add
MEM, a;
Result: MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc a, M
addc M, a
Add data in memory with ACC and carry bit, then put result into ACC
Example: addc
a, MEM ;
Result: a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into memory
Example: addc
MEM, a ;
Result: MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
addc
addc
a
Add carry with ACC, then put result into ACC
Example: addc
a ;
Result: a ← a + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Add carry with memory, then put result into memory
Example: addc
MEM ;
Result: MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
nadd a, M
nadd M, a
Add negative logic (2’s complement) of ACC with memory
Example: nadd
a, MEM ;
Result: a ← 〒a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add negative logic (2’s complement) of memory with ACC
Example: nadd
MEM, a ;
Result: MEM ← 〒MEM + a
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
sub
sub
a, I
Subtraction immediate data from ACC, then put result into ACC.
Example: sub
a, 0x0f;
Result: a ← a - 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, M
Subtraction data in memory from ACC, then put result into ACC
Example: sub
Result: a ← a - MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a, MEM ;
©Copyright 2018, PADAUK Technology Co. Ltd
Page 69 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
sub
M, a
Subtraction data in ACC from memory, then put result into memory
Example: sub MEM, a;
Result: MEM ← MEM - a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc a, M
subc M, a
Subtraction data in memory and carry from ACC, then put result into ACC
Example: subc
a, MEM;
Result: a ← a – MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction ACC and carry bit from memory, then put result into memory
Example: subc
MEM, a ;
Result: MEM ← MEM – a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
subc
subc
inc
a
Subtraction carry from ACC, then put result into ACC
Example: subc
a;
Result: a ← a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Subtraction carry from the content of memory, then put result into memory
Example: subc
MEM;
Result: MEM ← MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment the content of memory
Example: inc
MEM ;
Result: MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
dec
M
Decrement the content of memory
Example: dec
MEM;
Result: MEM ← MEM - 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
clear
M
Clear the content of memory
Example: clear
Result: MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
MEM ;
©Copyright 2018, PADAUK Technology Co. Ltd
Page 70 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7.3. Shift Operation Instructions
sr
a
Shift right of ACC
Example: sr a ;
Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of ACC with carry
src
sr
a
Example: src a ;
Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory
M
Example: sr MEM ;
Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of memory with carry
src
sl
M
Example: src MEM ;
Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC
a
Example: sl a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC with carry
slc
sl
a
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory
M
Example: sl MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry
slc
M
Example: slc MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC
swap
swap
a
Example: swap
a ;
Result: a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
M
Swap the high nibble and low nibble of memory
Example: swap
MEM ;
Result: MEM (b3,b2,b1,b0,b7,b6,b5,b4) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 71 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7.4. Logic Operation Instructions
and
and
and
or
a, I
a, M
M, a
a, I
Perform logic AND on ACC and immediate data, then put result into ACC
Example: and a, 0x0f ;
Result: a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC
Example: and
a, RAM10 ;
Result: a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory
Example: and
MEM, a ;
Result: MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and immediate data, then put result into ACC
Example: or
a, 0x0f ;
Result: a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
a, M
Perform logic OR on ACC and memory, then put result into ACC
Example: or
a, MEM ;
Result: a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
or
M, a
a, I
Perform logic OR on ACC and memory, then put result into memory
Example: or
MEM, a ;
Result: MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
xor
xor
Perform logic XOR on ACC and immediate data, then put result into ACC
Example: xor
a, 0x0f ;
Result: a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
a, IO
Perform logic XOR on ACC and IO register, then put result into ACC
Example: xor
a, pa ;
Result: a ← a ^ pa ; // pa is the data register of port A
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
xor
IO, a
Perform logic XOR on ACC and IO register, then put result into IO register
Example: xor
pa, a ;
Result: pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
xor
xor
a, M
M, a
Perform logic XOR on ACC and memory, then put result into ACC
Example: xor
a, MEM ;
Result: a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 72 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
not
a
Perform 1’s complement (logical complement) of ACC
Example: not a ;
Result: a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
not
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC7
------------------------------------------------------------------------------------------------------------------------
Perform 1’s complement (logical complement) of memory
not
M
Example: not
MEM ;
Result: MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
not
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC7
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of ACC
neg
a
Example: neg
a;
Result: a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
neg
a, 0x38 ;
a ;
// ACC=0X38
// ACC=0XC8
------------------------------------------------------------------------------------------------------------------------
Perform 2’s complement of memory
neg
M
Example: neg
MEM;
Result: MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
neg
a, 0x38 ;
mem, a ;
mem ;
// mem = 0x38
// mem = 0xC8
------------------------------------------------------------------------------------------------------------------------
©Copyright 2018, PADAUK Technology Co. Ltd
Page 73 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
comp
a, I
Compare ACC with immediate data
Example: comp a, 0x55;
Result: Flag will be changed by regarding as ( a - 0x55 )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
a, 0x38 ;
a, 0x38 ;
a, 0x42 ;
a, 0x24 ;
a, 0x6a ;
comp
comp
comp
comp
// Z flag is set
// C flag is set
// C, Z flags are clear
// C, AC flags are set
------------------------------------------------------------------------------------------------------------------------
Compare ACC with the content of memory
comp
a, M
Example: comp
a, MEM;
Result: Flag will be changed by regarding as ( a - MEM )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
mov
mov
comp
mov
mov
mov
comp
a, 0x38 ;
mem, a ;
a, mem ; // Z flag is set
a, 0x42 ;
mem, a ;
a, 0x38 ;
a, mem ; // C flag is set
------------------------------------------------------------------------------------------------------------------------
Compare ACC with the content of memory
comp
M, a
Example: comp
MEM, a;
Result: Flag will be changed by regarding as ( MEM - a )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 74 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7.5. Bit Operation Instructions
set0 IO.n
set1 IO.n
tog IO.n
Set bit n of IO port to low
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of IO port to high
Example: set1 pb.5 ;
Result: set bit 5 of port B to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Toggle bit state of bit n of IO port
Example: tog pa.5 ;
Result: toggle bit 5 of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to low
set0 M.n
set1 M.n
swapc IO.n
Example: set0 MEM.5 ;
Result: set bit 5 of MEM to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to high
Example: set1 MEM.5 ;
Result: set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Swap the nth bit of IO port with carry bit
Example: swapc
IO.0;
Result: C ← IO.0 , IO.0 ← C
When IO.0 is a port to output pin, carry C will be sent to IO.0;
When IO.0 is a port from input pin, IO.0 will be sent to carry C;
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Application Example (serial output) :
------------------------------------------------------------------------------------------------------------------------
…
set1
…
pac.0 ;
// set PA.0 as output
set0
swapc
set1
swapc
…
flag.1 ;
pa.0 ;
// C=0
// move C to PA.0 (bit operation), PA.0=0
// C=1
flag.1 ;
pa.0 ;
// move C to PA.0 (bit operation), PA.0=1
------------------------------------------------------------------------------------------------------------------------
©Copyright 2018, PADAUK Technology Co. Ltd
Page 75 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7.6. Conditional Operation Instructions
ceqsn a, I
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a - I)
Example: ceqsn
a, 0x55 ;
MEM ;
error ;
inc
goto
Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
ceqsn a, M
Example: ceqsn
a, MEM;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
ceqsn M, a
cneqsn a, M
Example: ceqsn
MEM, a;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are not equal.
Flag will be changed like as (a ← a - M)
Example: cneqsn
a, MEM;
Result: If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
cneqsn M, a
Compare memory with ACC and skip next instruction if both are not equal.
Flag will be changed like as (M ← M - a)
Example: cneqsn
MEM, a;
Result: If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
cneqsn a, I
Compare ACC with immediate data and skip next instruction if both are no equal.
Flag will be changed like as (a ← a - I)
Example: cneqsn
a,0x55 ;
MEM ;
error ;
inc
goto
Result: If a≠0x55, then “goto error”; Otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Check IO bit and skip next instruction if it’s low
t0sn IO.n
t1sn IO.n
Example: t0sn
pa.5;
Result: If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check IO bit and skip next instruction if it’s high
Example: t1sn
pa.5 ;
Result: If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 76 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
t0sn M.n
t1sn M.n
Check memory bit and skip next instruction if it’s low
Example: t0sn MEM.5 ;
Result: If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high
EX: t1sn MEM.5 ;
Result: If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Increment ACC and skip next instruction if ACC is zero
izsn
dzsn
izsn
dzsn
a
Example: izsn
Result:
a;
a
←
a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
a
Decrement ACC and skip next instruction if ACC is zero
Example: dzsn
Result:
a;
A
←
A - 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Increment memory and skip next instruction if memory is zero
Example: izsn
Result: MEM
MEM;
MEM + 1, skip next instruction if MEM= 0
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
M
Decrement memory and skip next instruction if memory is zero
Example: dzsn
Result: MEM
MEM;
MEM - 1, skip next instruction if MEM = 0
←
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Go next instruction until bit n of IO port is low, otherwise, wait here.
Example: wait0 pa.5;
wait0 IO.n
wait1 IO.n
Result:
Wait bit 5 of port A low to execute next instruction;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Note: This instruction is not supported in single FPP mode.
Go next instruction until bit n of IO port is high, otherwise, wait here.
Example: wait1 pa.5;
Result:
Wait bit 5 of port A high to execute next instruction;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Note: This instruction is not supported in single FPP mode.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 77 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7.7. System control Instructions
call
label
Function call, address can be full range address space
Example: call function1;
Result: [sp]
←
pc + 1
pc
sp
←
←
function1
sp + 2
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
goto label
Go to specific address which can be full range address space
Example: goto
error;
Result: Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
delay
delay
delay
I
Delay the (N＋1) cycles which N is specified by the immediate data, the timing is based on the
executing FPP unit. After the delay instruction is executed, the ACC will be zero.
Example: delay
0x05;
Result: Delay 6 cycles here
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Notes:
(1) Because ACC is the temporarily buffer for counting, please make sure that it will not
be interrupted when executing this instruction. Otherwise, it may be not the expected
delay time.
(2) This instruction is not supported in single FPP mode.
Delay the (N＋1) cycles which N is specified by the content of ACC, the timing is based on the
executing FPP unit. After the delay instruction is executed, the ACC will be zero.
a
Example: delay
a;
Result: Delay 16 cycles here if ACC=0fh
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Notes:
(1) Because ACC is the temporarily buffer for counting, please make sure that it will not be
interrupted when executing this instruction. Otherwise, it may be not the expected delay
time.
(2) This instruction is not supported in single FPP mode.
Delay the (N＋1) cycles which N is specified by the content of memory, the timing is based on
the executing FPP unit. After the delay instruction is executed, the ACC will be zero.
M
Example: delay
M;
Result: Delay 256 cycles here if M=ffh
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Notes:
(1) Because ACC is the temporarily buffer for counting, please make sure that it will not be
interrupted when executing this instruction. Otherwise, it may be not the expected delay
time.
(2) This instruction is not supported in single FPP mode.
Place immediate data to ACC, then return
ret
I
Example: ret 0x55;
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 78 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
ret
Return to program which had function call
Example: ret;
Result: sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
reti
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
nop
No operation
Example: nop;
Result: nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
pcadd
a
Next program counter is current program counter plus ACC.
Example: pcadd a;
Result: pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
------------------------------------------------------------------------------------------------------------------------
…
mov
pcadd
goto
goto
goto
goto
…
a, 0x02 ;
a ;
// PC <- PC+2
// jump here
err1 ;
correct ;
err2 ;
err3 ;
correct:
// jump here
…
------------------------------------------------------------------------------------------------------------------------
Enable global interrupt enable
engint
disgint
Example: engint;
Result: Interrupt request can be sent to FPP0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Disable global interrupt enable
Example: disgint ;
Result: Interrupt request is blocked from FPP0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 79 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
stopsys
stopexe
System halt.
Example: stopsys;
Result: Stop the system clocks and halt the system
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
CPU halt. The oscillator module is still active to output clock, however, system clock is disabled
to save power.
Example: stopexe;
Result: Stop the system clocks and keep oscillator modules active.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset the whole chip, its operation will be same as hardware reset.
Example: reset;
reset
Result: Reset the whole chip.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Reset Watchdog timer.
wdreset
Example: wdreset ;
Result: Reset Watchdog timer.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
7.8. Summary of Instructions Execution Cycle
Instruction
Condition
1 FPPA
2T
2 FPPA
1T
goto, call
Condition is fulfilled
2T
1T
ceqsn, cneqsn, t0sn, t1sn, dzsn,
izsn
Condition is not fulfilled
1T
1T
ldtabh, ldtabl, idxm, pcadd, ret, reti
2T
2T
Others
1T
1T
©Copyright 2018, PADAUK Technology Co. Ltd
Page 80 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
7.9. Summary of affected flags by Instructions
Instruction
mov a, I
Z
-
C
-
AC OV Instruction
Z
-
C
-
AC OV Instruction
Z
Y
-
C
-
AC OV
-
-
-
-
mov M, a
mov IO, a
ldtabh index
stt16 index
idxm index, a
popaf
-
-
-
-
-
-
mov a, M
-
-
-
-
mov a, IO
nmov a, M
ldt16 index
idxm a, index
pushaf
Y
Y
-
-
-
-
nmov M, a
ldtabl index
-
-
-
-
-
-
-
-
-
-
-
-
-
xch
M
-
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
-
wdreset
-
-
-
-
-
-
-
-
add a, I
addc a, M
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add a, M
addc M, a
nadd a, M
sub a, M
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
add M, a
addc
a
addc
M
nadd M, a
sub M, a
sub a, I
subc a, M
subc M, a
subc
dec
src
a
subc
clear
M
M
inc
sr a
src
sl
M
M
M
a
sr
M
-
Y
Y
-
-
-
-
-
-
sl
a
-
-
-
slc
a
-
-
-
M
-
-
-
slc
and
M
-
-
-
swap
and
a
-
-
-
swap
and
M
-
-
-
a, I
Y
Y
Y
Y
Y
Y
-
-
-
a, M
Y
Y
Y
-
-
-
-
M, a
Y
Y
Y
Y
Y
Y
-
-
-
-
or a, I
-
-
-
or a, M
-
-
-
or M, a
-
-
-
xor
a, I
-
-
-
xor
a, M
-
-
-
xor
M, a
-
-
-
xor
a, IO
M
-
-
-
xor
IO, a
a
-
-
-
not
a
-
-
-
not
-
-
-
neg
comp
Y
Y
-
-
-
-
neg
comp
M
-
-
-
comp
a, I
Y
-
Y
-
Y
-
a, M
Y
-
Y
-
Y
-
M, a
Y
-
Y
-
Y
-
set0 IO.n
set0 M.n
ceqsn a, I
cneqsn a, I
t0sn IO.n
t1sn M.n
set1 IO.n
set1 M.n
tog IO.n
-
-
-
-
-
-
-
-
swapc IO.n
ceqsn M, a
cneqsn M, a
t0sn M.n
-
Y
Y
Y
-
-
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
ceqsn a, M
cneqsn a, M
t1sn IO.n
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
-
-
-
-
izsn
dzsn
call
a
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
dzsn
a
Y
-
Y
-
Y
-
Y
-
izsn
wait1 IO.n
delay
M
Y
-
Y
-
Y
-
Y
-
M
wait0 IO.n
goto label
label
I
-
-
-
-
a
-
-
-
-
delay
ret
-
-
-
-
delay
reti
M
-
-
-
-
ret
I
-
-
-
-
-
-
-
-
-
-
-
-
nop
-
-
-
-
pcadd
a
-
-
-
-
engint
reset
-
-
-
-
disgint
-
-
-
-
stopsys
-
-
-
-
-
-
-
-
stopexe
-
-
-
-
©Copyright 2018, PADAUK Technology Co. Ltd
Page 81 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
8. Code Options
Option
Selection
Description
Enable
Disable
4.1V
Security Enable
Security
Security Disable
Select LVR = 4.1V
Select LVR = 3.6V
Select LVR = 3.1V
Select LVR = 2.8V
Select LVR = 2.5V
Select LVR = 2.2V
Select LVR = 2.0V
Select LVR = 1.8V
3.6V
3.1V
2.8V
LVR
2.5V
2.2V
2.0V
1.8V
Yes
reach normal operating voltage quickly within 20 mS
can’t reach normal operating voltage quickly within 20 mS
Single FPP unit mode
Under_20mS_VDD_OK
FPPA
No
1-FPPA
2-FPPA
Two FPP units mode
©Copyright 2018, PADAUK Technology Co. Ltd
Page 82 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
9. Special Notes
This chapter is to remind user who use PMC271/PMS271 series IC in order to avoid frequent errors upon
operation.
9.1. Warning
User must read all application notes of the IC by detail before using it. Please download the related application
notes from the following link:
http://www.padauk.com.tw/tw/technical/index.aspx
9.2. Using IC
9.2.1. IO pin usage and setting
(1) IO pin as digital input
When IO is set as digital input, the level of Vih and Vil would changes with the voltage and
temperature. Please follow the minimum value of Vih and the maximum value of Vil.
The value of internal pull high resistor would also changes with the voltage, temperature and pin
voltage. It is not the fixed value.
(2) IO pin as analog input
Configure IO pin as input
Set PADIER and PBDIER registers to configure corresponding IO as analog input
Set PAPH and PBPH registers to disable corresponding IO pull-up resistor
The functions of PADIER and PBDIER registers of PMC271/PMS271 series IC is contrary to ICE
functions. Please use following program in order to keep ICE emulation consisting with
PMC271/PMS271 series IC procedure.
$ PADIER 0xF0;
$ PBDIER 0x0F;
(3) PA5 as input pin
PA5 can only be Open-Drain output pin. Output high requires adding pull-up resistor
(4) PA5 as PRST# input
No internal pull-up resistor for PA5
Configure PA5 as input
Set CLKMD.0=1 to enable PA5 as PRST# input pin
(5) PA4/PA5 as input pin to connect with a push button or a switch by a long wire
Needs to put a >10Ω resistor in between PA4/PA5 and the long wire
Avoid using PA5 as input
(6) PA7 and PA6 as external crystal oscillator pin
Configure PA7 and PA6 as input
Disable PA7 and PA6 internal pull-up resistor
©Copyright 2018, PADAUK Technology Co. Ltd
Page 83 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
Configure PADIER register to set PA6 and PA7 as analog input
EOSCR register bit [6:5] selects corresponding crystal oscillator frequency :
01 : for lower frequency, ex : 32kHz
10 : for middle frequency, ex : 455kHz, 1MHz
11 : for higher frequency, ex : 4MHz
Program EOSCR.7 =1 to enable crystal oscillator
Ensure EOSC working well before switching from IHRC or ILRC to EOSC.
Note: Please read the PMC-APN013 carefully. According to PMC-APN013,, the crystal oscillator should
be used reasonably. If the following situations happen to cause IC start-up slowly or non-startup, PADAUK
Technology is not responsible for this: the quality of the user's crystal oscillator is not good, the usage
conditions are unreasonable, the PCB cleaner leakage current, or the PCB layouts are unreasonable.
9.2.2. Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit
Step2: Clear INTRQ register
Step3: In the main program, using ENGINT to enable CPU interrupt function
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine
Step5: After the Interrupt Service Routine being executed, return to the main program
* Use DISGINT in the main program to disable all interrupts
* When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG
register. POPAF instruction is to restore ALU and FLAG register before RETI as below:
void Interrupt (void)
// Once the interrupt occurs, jump to interrupt service routine
// enter DISGINT status automatically, no more interrupt is
{
accepted
PUSHAF;
…
POPAF;
}
// RETI will be added automatically. After RETI being executed, ENGINT status
will be restored
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function
(3) FPPA1 will not be affected by interrupt at all
©Copyright 2018, PADAUK Technology Co. Ltd
Page 84 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
9.2.3. System clock switching
(1) System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock and
turn off the original clock source at the same time. For example: When switching from clock A to clock B,
please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Case 1 : Switch system clock from ILRC to IHRC/2
CLKMD
=
0x36;
0;
// switch to IHRC, ILRC can not be disabled here
CLKMD.2 =
// ILRC can be disabled at this time
Case 2 : Switch system clock from ILRC to EOSC
CLKMD
=
0xA6;
0;
// switch to EOSC, ILRC can not be disabled here
CLKMD.2 =
// ILRC can be disabled at this time
ERROR. Switch ILRC to IHRC and turn off ILRC simultaneously
CLKMD 0x50; // MCU will hang
=
(2) Please ensure the EOSC oscillation has established before switching from ILRC or IHRC to EOSC. MCU
will not check its status. Please wait for a while after enabling EOSC. System clock can be switched to
EOSC afterwards. Otherwise, MCU will hang. The example for switching system clock from ILRC to 4MHz
EOSC after boot up as below:
.ADJUST_IC
DISABLE
CLKMD.1 = 0;
// turn off WDT for executing delay instruction.
// 4MHz EOSC start to oscillate.
// Delay for EOSC establishment
// ILRC -> EOSC;
$
EOSCR
Enable, 4MHz;
delay 255
CLKMD = 0xA4;
CLKMD.2 = 0;
// turn off ILRC only if necessary
The delay duration should be adjusted in accordance with the characteristic of the crystal and PCB. To
measure the oscillator signal by the oscilloscope, please select (x10) on the probe and measure
through PA6(X2) pin to avoid the interference on the oscillator.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 85 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
9.2.4. Power down mode, wakeup and watchdog
(1) Watchdog will be inactive once ILRC is disabled
(2) Please turn off watchdog before executing STOPSYS or STOPEXE instruction, otherwise IC will be reset
due to watchdog timeout. It is the same as in ICE emulation.
(3) The clock source of Watchdog is ILRC if the fast wakeup is disabled; otherwise, the clock source of
Watchdog will be the system clock and the reset time becomes much shorter. It is recommended to disable
Watchdog and enable fast wakeup before entering STOPSYS mode. When the system is waken up from
power down mode, please firstly disable fast wakeup function, and then enable Watchdog. It is to avoid
system to be reset after being waken up.
(4) If enable Watchdog during programming and also wants the fast wakeup, the example as below:
CLKMD.En_WatchDog
=
0;
// disable watchdog timer
$ MISC
stopexe;
nop;
Fast_Wake_Up;
$ MISC
Wdreset;
WT_xx;
// Reset Watchdog time to normal wake-up
// enable watchdog timer
CLKMD.En_WatchDog
=
1;
9.2.5. TIMER time out
When select $ INTEGS BIT_R (default value) and T16M counter BIT8 to generate interrupt, if T16M counts
from 0, the first interrupt will occur when the counter reaches to 0x100 (BIT8 from 0 to 1) and the second
interrupt will occur when the counter reaches 0x300 (BIT8 from 0 to 1). Therefore, selecting BIT8 as 1 to
generate interrupt means that the interrupt occurs every 512 counts. Please notice that if T16M counter is
restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
If select $ INTEGS BIT_F(BIT triggers from 1 to 0) and T16M counter BIT8 to generate interrupt, the T16M
counter changes to an interrupt every 0x200/0x400/0x600/. Please pay attention to two differences with
setting INTEGS methods.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 86 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
9.2.6. Using ADC
(1) Configure corresponding IO as input through PXDIER register
(2) The recommended highest ADC conversion frequency is 500kHz and maximum output impedance of
analog signal source is 15KΩ.
(3) Never restart next conversion before completion of last ADC conversion; otherwise, wrong value would get.
(4) Please pay attention on sequence of operation if the program fits for below conditions,
1. Use the FPP (ex. FPPA0) for handling power-save mode to disable ADC.
2. Use the FPP (ex. FPPA1) for handling ADC conversion to enable ADC and wait for completion of
ADC conversion with WAIT1 ADC_Done instruction.
3. Execute above【1】&【2】simultaneously
In case the above sequence is not properly arranged, there may be a chance that FPPA1 can not pass
through WAIT1 ADC_Done instruction because the ADC may be disabled by FPPA0 before WAIT1
ADC_Done instruction being executed.
Recommendation:
Define a Flag which represents the operation of ADC. Every time FPPA1 set the flag when enable the ADC
and reset it when the completion of ADC conversion. FPPA0 checks this flag and decides to enter
power-save and disable ADC if it is reset.
9.2.7. LVR
(1) VDD must reach or above 2.2V for successful power-on process; otherwise IC will be inactive.
(2) The setting of LVR (1.8V, 2.0V, 2.2V etc) will be valid just after successful power-on process.
9.2.8. IHRC
(1) The IHRC frequency calibration is performed when IC is programmed by the writer.
(2) Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the IHRC
frequency (either for package or COB), if the calibration is done before molding process, the actual IHRC
frequency after molding may be deviated or becomes out of spec. Normally , the frequency is getting slower
a bit.
(3) It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not take
any responsibility for this situation.
(4) Users can make some compensatory adjustments according to their own experiences. For example, users
can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 87 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
9.2.9. Program writing
There are 8 pins for using the writer to program: PA0, PA3, PA4, PA5, PA6, PA7, VDD, and GND.
Please use PDK3S-P-002 to program and put the PMC271/PMS271-SOP20/18/16/14, DIP20/18/16/14 at the
top of the textool and put jumper over the CN40. Other packages could be programmed by user’s way. All the
left signs behind the jumper are the same (there are VDD, PA0, PA3, PA4, PA5, PA6, PA7, and GND).The
following picture is shown:
If user uses PDK5S-P-003 or above to program, please follow the instruction.
Special notes about voltage and current while Multi-Chip-Package(MCP) or On-Board Programming
(1) PA5 (VPP) may be higher than 11V.
(2) VDD may be higher than 6.5V, and its maximum current may reach about 20mA.
(3) All other signal pins level (except GND) are the same as VDD.
User should confirm when using this product in MCP or On-Board Programming, the peripheral circuit or
components will not be destroyed or limit the above voltages.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 88 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
9.3. Using ICE
9.3.1. Emulating PMC271/PMS271 series IC on ICE PDK3S-I-001/002/003
PMC271/PMS271 series I/O pin is defined as compatible with PDK22C series. When user use ICE
PDK3S-I-001/002/003 to emulate PMC271/PMS271 series IC, please connect the cable labeled CN12 or
CN17 with CN12 or CN17 connectors on PDK3S-I-001/002/003 by matching each assembled pins
respectively.
(1) Emulating PMC271/PMS271(SOP14) : Use cable labeled CN17:P211CS14/CD14 to connect CN17
connector on PDK3S-I-001/002/003. Connection is shown in illustration 1-1.
(2) Emulating PMC271/PMS271(SOP16/SSOP16) : Use cable labeled CN17:PDK82C12, PDK82C16 to
connect CN 17 connector on PDK3S-I-001/002/003. Connection is shown in illustration 1-1.
(3) Emulating PMC271/PMS271(SOP18) : Use cable labeled CN17:PDK82C15, P221CS18/CD18 to connect
CN 17 connector on PDK3S-I-001/002/003. Connection is shown in illustration 1-1.
(4) Emulating PMC271/PMS271(SSOP20/DIP20) : Use cable labeled CN12:82C13-D to connect CN12
connector on PDK3S-I-001/002/003. Connection is shown in illustration 1-2
©Copyright 2018, PADAUK Technology Co. Ltd
Page 89 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
PMC271/PMS271 Series
8-bit ADC FPPATM 8-bit Controller
9.3.2. Important Notice for ICE operation
(1) EV3-0101D-CON ICE board is required when emulate PMC271/PMS271 series IC LCD 1/2 VDD function.
Details please refer to “ PDK3S-I-001/002/003 ICE user’s manual” section 8.
(2) ICE PDK3S-I-001/001/002 does not support emulating below PMC271/PMS271 series IC functions from (a)
to (k). Thus, user needs to take PMC271/PMS271 Real Chip for test. Please notice：In order to avoid the
problems on difference between ICE and Real Chip test procedure, those functions will be temporarily
removed from datasheet before ICE is set to support them. PMC271/PMS271 Real Chip is defaulted with
these functions and performing ordinarily. Please refer to V0.08 datasheet. Customer is recommended to
consider these exceptions and careful handle whenever doing the test.
(a) PMC271/PMS271 series IC is able to set Band-Gap voltage as ADC reference voltage (Vref).
(b) PMC271/PMS271 series IC is able to set Band-Gap voltage output to PB2.
(c) PMC271/PMS271 series IC is able to set LVR minimum to 1.8V, 8 stages at all 4.0V, 3.5V, 3.0V, 2.75V,
2.5V, 2.2V, 2.0V, 1.8V.
(d) PMC271/PMS271 series IC LVR function can be disabled by register (misc.2).
(e) PMC271/PMS271 series IC is able to support LVR reset and fast-recover by register (misc.3).
(f) PMC271/PMS271 series IC is able to output voltage from PB1 I/O pin to PB2.
(g) PMC271/PMS271 series IC is able to be set as single core operating model.
(h) PMC271/PMS271 series IC supports VDD less than 4V, 3V, 2V voltage level detection and store
detecting result to internal register (rstst).
(i) PMC271/PMS271 series IC support reset-source detection.
(j) PMC271/PMS271 series IC Timer 16 Clock Source supports external PA4 signal input.
(k) PMC271/PMS271 series IC provides watch-dog time out function which is assigned by register
misc[1:0]
©Copyright 2018, PADAUK Technology Co. Ltd
Page 90 of 90
PDK-DS-PMX271-EN_V105 – Dec. 18, 2018
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