MN66271RA [PANASONIC]
Signal Processing LSI for Compact Disc Players; 信号处理LSI的光盘播放
| 型号： | MN66271RA |
| 厂家： | 
PANASONIC |
| 描述： | Signal Processing LSI for Compact Disc Players |
| 文件： | 总6页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
For Audio Equipment
MN66271RA
Signal Processing LSI for Compact Disc Players
Overview
The MN66271RA is a CD signal processing LSI that,
on a single chip, combines optics servos for the CD player
(focus, tracking, and traverse servos), digital signal
processing (EFM demodulation and error correction),
digital servo processing for the spindle motor, digital
filter, and D/A converter, so thus covers all signal
processing functions from the head's RF amplifier onward.
(Spindle motor servo)
CLV digital servo
(Audio circuits)
Digital filter using 8 times oversampling
Built-in D/A converter (1-bit D/A converter)
Built-in differential operational amplifier (±PWM
output)
Features
(Optics servo)
(Other)
Focus, tracking, and traverse servos
Automatic adjustment functions for FO/TR gain,
FO/TR offset, and FO/TR balance
Built-in D/A converter for drive voltage output
Built-in dropout countermeasures
Anti-shock functions
Built-in playback pitch control function (±13%)
Operating voltage 4.5 to 5.5 V
Applications
CD Players
Built-in track cross counter
Support for both linear motor and screw-based
traverse mechanisms
Support for 3- and 1-beam systems Digital Signal
Processing
(Digital signal processing)
Built-in DSL and PLL
Frame synchronization detection, holding, and
insertion
Subcode data processing
Subcode Q data CRC check
Built-in subcode Q data register
CIRC error detection and correction
C1 decoder: duplex error correction
C2 decoder: triplex error correction
Built-in 16-K bits of RAM for use in de-
interleaving
Audio data interpolation
Averaging or retention of previous values
Soft muting
Digital attenuation (256 levels)
Software attenuation (256 levels)
Audio data peak level detection function
Automatic cuing detection function
Digital audio interface (EIAJ format)
Audio data serial interface
MN66271RA
For Audio Equipment
Pin Assignment
BYTCK
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
LDON
BDO
RFDET
TRCRS
OFT
CLDCK
FCLK
IPFLAG
FLAG
CLVS
CRC
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDET
RFENV
TE
DEMPH
RESY
RST2
FE
TBAL
FBAL
VREF
FOD
TEST
AVDD1
OUTL
AVSS1
OUTR
RSEL
CSEL
PSEL
TRD
KICK
ECS
ECM
PC
TVD
TRV
MSEL
SSEL
(TOP VIEW)
QFS080-P-1414
For Audio Equipment
MN66271RA
Block Diagram
75
51
AVSS2
50
OUTR
AVDD2
73
OUTL
66
CLVS
67
74
AVSS1
72
CRC
13
AVDD1
BLKCK
62
CLDCK
56
65
SBCK
55
FLAG
64
SUBC
68
IPFLAG
DEMPH
69
RESY
6
TX
80
14
15
SSEL
SQCK
SUBQ
24
ECM
53
PCK
52
23
PC
EFM
48
2
3
PLLF
47
LRCK
DSLF
45
SRDATA
1
IREF
46
BCLK
16
DRF
44
DMUTE
ARF
76
21
TRV
26
RSEL
78
KICK
29
PSEL
VREF
25
9
MLD
7
ECS
22
MCLK
8
TVD
27
MDATA
TRD
28
49
VCOF
61
FOD
31
BYTCK
19
TBAL
30
SMCK
63
FBAL
41
FCLK
20
TES
12
PMCK
77
TLOCK
11
CSEL
79
FLOCK
42
MSEL
59
PLAY
40
X2
X1
LDON
58
43
WVEL
10
17
STAT
SENSE
SERVO
TIMING GENERATOR
A/D CONVERTER
INPUT PORT
MN66271RA
For Audio Equipment
Pin Descriptions
Pin No.
Symbol
I/O
Function Description
SRDATA bit clock output
1
BCLK
O
2
3
LRCK
SRDATA
DVDD1
DVSS1
O
O
I
Left/right channel discrimination signal output
Serial data output
4
Power supply for digital circuits
Ground for digital circuits
5
I
6
TX
O
I
Digital audio interface output signal
7
MCLK
MDATA
MLD
Microcomputer command clock input (Data is latched at rising edge.)
Microcomputer command data input
8
I
9
I
Microcomputer command load signal input. "L" level: load.
Sense signal output (OFT, FESL, NACEND, NAJEND, POSAD, and SFG)
10
11
12
13
14
15
16
17
18
19
SENSE
FLOCK
TLOCK
BLKCK
SQCK
SUBQ
DMUTE
STAT
O
O
O
O
I
Focus servo convergence signal.
Tracking servo convergence signal.
"L" level: convergence.
"L" level: convergence.
Subcode block clock signal (fBLKCK=75 Hz, normal playback)
External clock input for subcode Q register
Subcode Q data output
O
I
Muting input.
Status signal (CRC, CUE, CLVS, TTSTOP, FCLV, and SQOK)
Reset input. "L" level: reset.
"H" level: muting.
O
I
RST
SMCK
O
If MSEL is at "H" level, 8.4672 MHz clock signal output.
If MSEL is at "L" level, 4.2336 MHz clock signal output.
88.2 kHz clock signal output
20
21
22
23
24
25
26
27
28
29
PMCK
TRV
TVD
PC
O
O
O
O
O
O
O
O
O
I
Traverse forced feed output
Traverse drive output
Spindle motor ON signal.
"L" level: ON.
3-State
ECM
ECS
Spindle motor drive signal (forced mode output)
Spindle motor drive signal (servo error signal output)
Kick pulse output
KICK
TRD
FOD
VREF
Tracking drive output
Focus drive output
Reference voltage for DA output (TVD, ECS, TRD, FOD, FBAL, and
TBAL)
30
31
32
33
34
35
36
37
38
39
40
FBAL
TBAL
FE
O
O
I
Focus balance adjustment output
Tracking balance adjustment output
Focus error signal input (analog input)
Tracking error signal input (analog input)
RF envelope signal input (analog input)
TE
I
RFENV
VDET
OFT
I
I
Vibration detection signal input.
Offtrack signal input.
"H" level: vibration detected.
"H" level: offtrack.
I
TRCRS
RFDET
BDO
I
Track cross signal input
RF detection signal input.
Dropout signal input.
I
"L" level: detected.
"H" level: dropout.
"H" level: ON.
I
LDON
O
Laser ON signal output.
For Audio Equipment
MN66271RA
Pin Descriptions (continued)
Pin No.
Symbol
I/O
Function Description
Tracking error shunt signal. "H" level: shunt.
Play signal output. "H" level: play.
41
TES
O
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
PLAY
WVEL
ARF
O
O
I
Double-speed status signal output. "L" level: double-speed.
RF signal input
IREF
I
Reference current input pin
DRF
I
DSL bias pin
DSLF
PLLF
VCOF
AVDD2
AVSS2
EFM
I/O
I/O
I/O
I
DSL loop filter pin
PLL loop filter pin
VCO loop filter pin for pitch control
Power supply for analog circuits (DSL, PLL, and D/A converter output)
Ground for analog circuits (DSL, PLL, and D/A converter output)
EFM signal output
I
O
O
O
O
I
PCK
PLL derived clock output with fPCK=4.3218 MHz
Phase comparator output for EFM and PCK signals
Subcode serial output data output
PDO
SUBC
SBCK
VSS
Serial clock input for subcode serial output
Ground for oscillator circuit
I
X1
I
Crystal oscillator circuit input pin. f=16.9344 MHz.
Crystal oscillator circuit output pin. f=16.9344 MHz.
Power supply for oscillator circuit
X2
O
I
VDD
BYTCK
CLDCK
FCLK
IPFLAG
FLAG
CLVS
O
O
O
O
O
O
Byte clock signal output
Subcode frame clock signal output pin (fCLDCK=7.35 kHz)
Crystal frame clock signal output (fFCLK=7.35 kHz)
Interpolation flag signal output.
Flag signal output
"H" level: interpolation.
Spindle servo phase synchronization signal output. "H" level: CLV.
"L" level: rough servo.
67
68
69
CRC
DEMPH
RESY
O
O
O
Subcode CRC check result output.
De-emphasis detection signal output.
Frame resynchronization signal.
"H" level: OK. "L" level: no good.
"H" level: ON.
"H" level: synchronized.
"L" level: out of sync.
70
71
72
RST2
TEST
AVDD1
I
I
I
Reset pin for stopping operation of circuits past D/A converter
Test pin.
Keep this pin at "H" level.
Power supply for analog circuits (common use for by left and right channel
audio outputs)
73
74
OUTL
AVSS1
O
I
Left channel audio output
Ground for analog circuits (common use for left and right channel audio
outputs)
75
76
OUTR
RSEL
O
I
Right channel audio output
RF signal polarity selection pin. "H" level: bright level is "H.
"L" level: bright level is "L.
77
CSEL
I
Test pin.
Keep this pin at "L" level.
MN66271RA
For Audio Equipment
Pin Descriptions (continued)
Pin No.
78
Symbol
PSEL
I/O
Function Description
I
I
Test pin.
Frequency selection pin for SMCK pin output.
"H" level: SMCK=8.4672 MHz.
Keep this pin at "L" level.
79
MSEL
"L" level: SMCK=4.2336 MHz.
80
SSEL
I
SUBQ pin output mode selection pin. "H" level: buffered subcode Q mode.
Package Dimensions (Unit: mm)
QFS080-P-1414
16.2±0.2
14.0±0.2
60
41
40
61
80
21
1
20
1.1±0.1
+0.10
0.65
-0.05
0.3
0.15
SEATING PLANE
0.55±0.1
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