R-1515K [PANASONIC]
Low CTE IC substrate materials Designed to Improve Reliability;
| 型号： | R-1515K |
| 厂家： | 
PANASONIC |
| 描述： | Low CTE IC substrate materials Designed to Improve Reliability |
| 文件： | 总1页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Circuit Board Materials
電子回路基板材料
Panasonic Electronic Materials Division launches a new product brand for the Semiconductor Device Materials business. The IC substrate materials' brand is transitioning from MEGTRON GX to LEXCM GX.
パナソニック 電子材料事業部は、新たに半導体デバイス材料の製品ブランドをLE X C M（ レ ク シ ム ）としてスタートします。それに伴い、半導体パッケージ基 板材料はMEGTRON GXからLEXCM GXへ変更いたします。
Low CTE IC substrate materials
Designed to Improve Reliability
Laminate R-1515V(Low CTE glass cloth)
低熱膨張・高実装信頼性半導体パッケージ基板材料
Laminate R-1515K(Normal glass cloth)
Applications ⽤途
IC substrate
FC-BGA (CPU, GPU, FPGA, ASIC, etc.)
半導体パッケージ基板（CPU、GPU、FPGA、ASICなどのFC-BGAパッケージ）
Package
半 導 体 パッケージ
Low CTE reduces warping and addresses a critical challenge with the IC packaging process. Flexibility and buffering features
through a stress relaxation technology improves the reliability of the assembly process. Offering excellent thickness tolerances.
低熱膨張性で反りを抑制し、IC チップの一次実装の不具合を低減、さらに樹脂の伸縮性と緩衝性を合わせ持つ応力緩和技術により二次実装
の信頼性を向上させます。板厚 精度に優れ、サブストレートと IC チップとの接合を安定化。
CTE x,y-axis 3-5ppm/℃
(Low CTE glass cloth)
Stress Relaxation
Good Thickness Variation
■ IC Pakage Warpage パッケージ基板反り評価結果
●
Sample
●
Result
250
Core Thickness
Package size
700μmt (12-12μm)
200
35ｘ35mm (Die size 15ｘ15mm)
R-1515V
150
Panasonic
CV5300AM
Low CTE glass cloth
●
PKG Construction
100
50
0
300μm
340μm
R-1515V
770μm(Core:700μm)
30
75
125 175 220 260 220 175 125
75
30
-50
-100
-150
-200
■ A wide range of Thickness Line-up 豊富な板厚 をラインアップ
R-1515W
Normal glass cloth
R-1515V (Low CTE glass cloth)
0.21～1.8mm
R-1515K (Normal glass cloth)
Temperature（℃）
■ Designed to Improve Reliability 高い実装信頼性
Low thermal expansion coefficient (CTE): close to
that of silicon IC chips, which reduces warping
and addresses a critical challenge with the IC chip
packaging process.
Low Warpage
Cu Pillar
Low CTE
Semiconductor (IC chip)
Substrate (core material)
4ppm/℃
Combines flexibility and buffering features while
retaining low thermal expansion properties
through a stress relaxation technology, improving
the reliability of the assembly process.
Stress
Relaxation
Low Stress on solder balls
Mother board
15ppm/℃
■ General propertiesꢀ一般特性
R-1515V
R-1515K
Conventional
Item
Test method
Condition
A
Unit
Low CTE glass cloth Normal glass cloth
Normal glass cloth
Glass transition temp.(Tg)
CTE x-axis
DMA*2
TMA*2
℃
260
260
260
8-10
8-10
4.8
3-5
3-5
4.4
7
7
α1
A
ppm/℃
CTE y-axis
Dielectric constant(Dk)*1
Dissipation factor(Df)*1
4.6
0.015
27
1GHz
IPC-TM-650 2.5.5.9
IPC-TM-650 2.4.4*3
C-24/23/50
－
0.016
30
0.015
33
25℃
250℃
A
Elastic modulus*1
Peel strength
GPa
14
12
21
1/3oz(12μｍ) IPC-TM-650 2.4.8
kN/m
0.6
0.6
0.9
The sample thickness is 100μm. *1 700μm *2 Measurement in tensile mode.
*3 The IPC standard determines the test sample size, methods and conditions, etc. but there is no formula for calculating the elastic modulus. Therefore, we quantified it according to JIS C 6481.
ꢀ
Our Halogen-free materials are based on JPCA-ES-01-2003 standard and others. 当社ハロゲンフリー材料は、JPCA-ES-01-2003 などの定義によるものです。
The above data are typical values and not guaranteed values. 上記データは当社測定による代表値であり、保証値ではありません。
Please see the page for “Notes before you use” 商品のご採用に当たっての注意事項は こちら
2021
202109
industrial.panasonic.com/ww/electronic-materials
panasonic R-1515V
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