PJESDZ6V8-2G [PANJIT]
E.S.D. Dual Protection Diode Array; 等效球径双重保护二极管阵列
| 型号： | PJESDZ6V8-2G |
| 厂家： | 
PAN JIT INTERNATIONAL INC. |
| 描述： | E.S.D. Dual Protection Diode Array |
| 文件： | 总3页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PJESDZ6V8-2G
E.S.D. Dual Protection Diode Array
This Dual Unidirectional ESD Protector Array family have been designed to protect
sensitive equipment against ESD in high speed transmission buses, operating at
5V. This dual array offers an integrated solution to protect up to
2 data lines in a unidirectional mode or, 1 data line in a bi-directional mode, in
application where the board space is a premium, in our SOT523 package
version.
PANJIT SOT523
3
SPECIFICATION FEATURES
1
IEC61000-4-2 ESD 15kV air, 8kV Contact Compliance
Low Leakage Current, Maximum of 0.5µA at rated voltage
Maximum Capacitance of 10pF per device at 0Vdc 1MHz
Peak Power Dissipation of 20W 8/20µs Waveform
2
3
Pin to pin compatible with standard SOT523
Lead Free Package 100% Tin Plating, Matte finish
Low profile, Max height of 0.55mm
APPLICATIONS
2
1
Mobile Phones
Digital Cameras
Notebooks PC's
MAXIMUM RATINGS (Per Device)
Units
Rating
Symbol
Value
P
Peak Pulse Power (8/20µs Waveform)
Peak Pulse Current (8/20µs Waveform)
ESD Voltage (HBM Per MIL STD883C - Method 3015-6)
Operating Temperature Range
20
PP
W
I
2
PPM
A
kV
°C
°C
V
20
ESD
T
J
-55 to +125
-55 to +150
T
Storage Temperature Range
stg
ELECTRICAL CHARACTERISTICS (Per Device)
Tj = 25°C
Parameter
Conditions
Min Typical Max
Units
Symbol
Reverse Stand-Off Voltage
V
5.0
V
V
WRM
V
I
=
=
=
1mA
5V
6.2
7.2
0.5
10
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
BR
BR
I
V
R
µA
R
V
c
I
2A
V
pp
0 Vdc Bias f = 1MHz
between pin 1, 2 to 3 (Gnd)
Off State Junction Capacitance*
Cj
9
10
pF
* Capacitance between pins 1 and 2 is half of the value, in a bi-directional configuration.
12/9/2008
Page
1
www.panjit.com
PJESDZ6V8-2G
Tj = 25°C
TYPICAL CHARACTERISTIC CURVES (Per Device)
Clamping Voltage vs 8/20µs Ipp
Pulse Waveform
9.5
9
100
90
80
70
60
50
40
30
20
10
0
50% of Ipp @ 20µs
8.5
8
7.5
7
Rise time 10-90% - 8µs
6.5
0
0.5
1
1.5
2
0
5
10
15
20
25
30
time, µsec
Peak Current, A 8/20µs
Off-State Capacitance vs DC Bias
10
9
8
7
6
5
4
0
1
2
3
4
5
Vdc Bias, V
12/9/2008
Page 2
www.panjit.com
PJESDZ6V8-2G
PACKAGE DIMENSIONS AND SUGGESTED PAD LAYOUT
12/9/2008
Page 3
www.panjit.com
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