EP9306 [PCA]
14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines; 14引脚DIP 5点薄型TTL兼容主动延迟线
| 型号： | EP9306 |
| 厂家： | 
PCA ELECTRONICS INC. |
| 描述： | 14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines |
| 文件： | 总1页 (文件大小：40K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14 Pin DIP 5 Tap Low-Profile TTL Compatible
Active Delay Lines
TAP DELAYS
5ꢀ or ꢁ nSꢂ
TOTAL DELAYS
5ꢀ or ꢁ nSꢂ
PART
TAP DELAYS
5ꢀ or ꢁ nSꢂ
TOTAL DELAYS
5ꢀ or ꢁ nSꢂ
PART
NUMBER
NUMBER
80, 160, 240, 320
84, 168, 252, 336
88, 176, 264, 352
90, 180, 270, 360
94, 188, 282, 376
100, 200, 300, 400
110, 220, 330, 440
120, 240, 360, 480
130, 260, 390, 520
140, 280, 420, 560
150, 300, 450, 600
160, 320, 480, 640
400
420
440
450
470
500
550
600
650
700
750
800
EP9308
EP9318
EP9322
EP9309
EP9323
EP9310
EP9330
EP9324
EP9331
EP9325
EP9329
EP9326
5, 10, 15, 20
6, 12, 18, 24
25
30
EP9300
EP9313
7, 14, 21, 28
35
EP9314
8, 16, 24, 32
9, 18, 27, 36
40
45
EP9315
EP9316
10, 20, 30, 40
50
60
EP9301
EP9311
EP9317
EP9302
EP9319
EP9303
EP9320
EP9304
EP9321
EP9305
EP9306
EP9307
12, 24, 36, 48
15, 30, 45, 60
75
20, 40, 60, 80
100
125
150
175
200
225
250
300
350
25, 50, 75, 100
30, 60, 90, 120
35, 70, 105, 140
40, 80, 120, 160
45, 90, 135, 180
50, 100, 150, 200
60, 120, 180, 240
70, 140, 210, 280
170, 340, 510, 680
180, 360, 540, 720
850
900
EP9332
EP9327
190, 380, 570, 760
200, 400, 600, 800
950
EP9333
EP9328
1000
†Whichever is greater.
Delay times referenced from input to leading edges at 25°C, 5.0V, with no load.
Schematic
DC Electrical Characteristics
Parameter
Test Conditions
Min Max Unit
V
V
V
High-Level Output Voltage
Low-Level Output Voltage
Input Clamp Voltage
V
V
V
V
V
= min. V = max. I
= max 2.7
V
OH
OL
IK
CC
CC
CC
CC
CC
CC
CC
IL OH
= min. V = min. I = max
IH OL
0.5
-1.2
50
V
= min. I = II
V
I
K
14
12
4
10
6
8
OUTPUT
VCC
I
High-Level Input Current
= max. V = 2.7V
IN
µA
mA
IH
= max. V = 5.25V
1.0
IN
I
I
Low-Level Input Current
V
V
= max. V = 0.5V
IN
-2
mA
mA
IL
INPUT 1
Short Circuit Output Current
= max. V
= 0.
OUT
-40 -100
OS
(One output at a time)
GROUND
I
I
High-Level Supply Current
Low-Level Supply Current
Output Rise Time
V
V
= max. V = OPEN
IN
75
75
4
5
mA
mA
nS
nS
7
CCH
CCL
CC
CC
= max. V = 0
IN
T
Td ≤ 500 nS (0.75 to 2.4 Volts)
RO
Td > 500 nS
N
Fanout High-Level Output
Fanout Low-Level Output
V
V
= max. V
= max. V
= 2.7V
= 0.5V
20 TTL LOAD
10 TTL LOAD
H
CC
CC
OH
OL
N
L
Package Dimensions
Recommended
Operating Conditions
Min Max Unit
V
V
V
I
Supply Voltage
4.75
2.0
5.25
V
CC
IH
IL
.200
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Current
High-Level Output Current
Low-Level Output Current
Pulse Width of Total Delay
Duty Cycle
V
0.8
-18
-1.0
20
V
PCA
EP93XX
Date Code
.300
White Dot
mA
mA
mA
%
.280
IK
Pin#1
I
I
Max.
OH
OL
P
*
40
W
.100
d*
40
+125
%
°C
T
A
Operating Free-Air Temperature
-55
.780 Max.
*These two values are inter-dependent.
.015
Typ.
.165
Max.
Input Pulse Test Conditions @ ꢁ5° C
Unit
.010
Typ.
.100 Min.
E
P
Pulse Input Voltage
3.2
110
2.0
1.0
100
5.0
Volts
%
IN
W
.020
Typ.
.365
Max.
Pulse Width % of Total Delay
Pulse Rise Time (0.75 - 2.4 Volts)
Pulse Repetition Rate @ Td ≤ 200 nS
Pulse Repetition Rate @ Td > 200 nS
Supply Voltage
T
nS
RI
P
MHz
KHz
Volts
RR
CC
V
QAF-CSO1 Rev. B 8/25/94
DSD93XX Rev. A 2/5/96
Unless Otherwise Noted Dimensions in Inches
Tolerances:
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
Fractional = 1/32
E L E C T R O N I C S I N C .
.XX = .030
.XXX = .010
FAX: (818) 894-5791
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