EPF8076 [PCA]
High Speed LAN Interface Module; 高速LAN接口模块
| 型号： | EPF8076 |
| 厂家： | 
PCA ELECTRONICS INC. |
| 描述： | High Speed LAN Interface Module |
| 文件： | 总2页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed LAN Interface Module
EPF8076
E L E C T R O N I C S I N C .
• Optimized for ML6673 •
• Recommended for 10/100, 100 BX, 155 Mb/s applications •
(requiring 1:1 magnetics)
• Guaranteed to operate with 8 mA DC bias at 70°C •
• Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards •
Electrical Parameters @ 25° C
OCL
@ 70°C
Insertion Loss
Return Loss
Common Mode Rejection
(dB Max.)
(dB Min.)
(dB Min.)
1-80
MHz
80-100
MHz
100-150
MHz
1-32
MHz
32-62
MHz
62-100
MHz
50
100
200
100 KHz, 0.1 Vrms
8 mA DC Bias
MHz
MHz
MHz
Xmit
-40
Xmit
-1
Xmit
-1
Xmit
-3
Xmit
-20
Xmit
-17
Xmit
-12
Xmit
-50
Xmit
-45
Cable Side
350µH
•
Isolation : 1500 Vrms
•
Impedance : 100 W • Rise Time : 3.0 nS Max. •
Schematic
1
6
No pin 4
2
3
7
1:1
5
Dimensions
Package
(Inches)
Dim. Min. Max. Nom.
(Millimeters)
Min.
Max. Nom.
A
B
C
D
E
F
G
H
I
.790
.180
.300
.700
.020
.090
.810
.200
.320
Typ.
.030
Typ.
20.07 20.57
A
4.57
7.62
5.08
8.13
B
17.78 Typ.
.508
2.54
.762
Typ.
Pin 1 I.D.
.090
2.29
.016
.008
.065
.125
.022
.012
Typ.
.145
.406
.203
1.65
3.18
.559
.305
Typ.
3.68
PCA
EPF8076
Date Code
E
J
C
J
K
K
I
F
H
D
G
CSF8076a Rev. - 8/22/97
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pcainc.com
Product performance is limited to specified parameters. Data is subject to change without prior notice.
High Speed LAN Interface Module
EPF8076
E L E C T R O N I C S I N C .
The circuit below is a guideline for interconnecting PCA’s EPF8076 with a typical 100 BX PHY chip for 100 Mb/s applications
over UTP cable. Further details of system design, such as chip pin-out, etc. should be obtained from the specific chip
manufacturer. The package is a minature SIP, built for convenience of dense board designs for both NIC’s and multiport
applications. Each port requires two such devices.
Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded
signals in 100/155 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust
the specific chip preset template control resistors to get at least 2.12V pk-pk across the transmit side input pins.
It is recommended that system designers do not ground the receiver side center tap, via a capacitor. This may worsen
EMI, specifically if the secondary “common mode termination” is pulled to chassis ground as shown.
Pulling unused pins on the RJ45 to chassis via 50 W has been known to suppress unwanted radiation that unused wires
pick up from the immediate environment. Their placement and use are to be considered carefully before a design is
finalized.
The “common mode termination” load of 75 Wshown from the center taps of the secondary may be taken to chassis ground
via a suitable cap. This depends upon the user’s design, EMI margin, etc.
It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit
the plane off at least 0.05 inches away from pins of EPF8076 the chip side. There need not be any ground plane beyond
this point.
For best results, the PCB designer should design the outgoing traces preferably to be 50 W, balanced and well coupled to
achieve minimum radiation from these traces.
Typical Application Circuit for 100 BX over UTP
1
RX+
RX-
1
2
7
6
5
Rcv
2
3
6
75W
RJ45*
.01 µƒ
2 kV
100BX
PHY
EPF8076
EPF8076
7
6
5
1
2
TX+
TX-
75W
.01 µƒ
2 kV
Vcc
Notes : * Pin-outs shown are for DCE configurations : e.g. Hubs, Repeaters
CSF8076b Rev. - 8/22/97
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pcainc.com
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