PI4IOE5V9537UEX [PERICOM]
interrupt and reset;
| 型号： | PI4IOE5V9537UEX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | interrupt and reset |
| 文件： | 总13页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI4IOE5V9537
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4-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Features
Description
Operation power supply voltage from 2.3V to 5.5V
4-bit I2C-bus GPIO with interrupt and reset
5V tolerant I/Os
The PI4IOE5V9537 provides 4 bits of General
Purpose parallel Input/Output (GPIO) expansion for
I2C-bus/ SMBus applications. It includes the features
such as higher driving capability, 5V tolerance, lower
power supply, individual I/O configuration, and
smaller packaging. It provides a simple solution when
additional I/O is needed for ACPI power switches,
sensors, push buttons, LEDs, fans, etc.
Active Low interrupt output
Active Low reset input
Polarity inversion register
Low current consumption
0Hz to 1MHz clock frequency
Noise filter on SCL/SDA inputs
Power-on reset
The PI4IOE5V9537 consists of a 4-bit register to
configure the I/Os as either inputs or outputs, and a 4-
bit polarity register to change the polarity of the input
port register data. The data for each input or output is
kept in the corresponding Input port or Output port
register. All registers can be read by the system master.
ESD protection (4KV HBM and 1KV CDM)
Package offered: MSOP-10L
The PI4IOE5V9537 open-drain interrupt output
(INT) is activated when any input state and is used to
indicate the system master that an input state has
changed.
Pin Configuration
The power-on reset sets the registers to their
default values and initializes the device state machine.
The Reset pin causes the same reset/initialization to
occur without de-powering the device.
Figure 1: MSOP-10
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PI4IOE5V9537
4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Pin Description
Table 1. Pin configuration
* I = Input; O = Output; P = Power; G = Ground
Pin
1
Name
IO0
Type
I/O
Description
input/output 0
2
3
IO1
IO2
I/O
I/O
I/O
G
input/output 1
input/output 2
input/output 3
Supply Ground
Reset pin
4
IO3
5
GND
6
I
RESET
INT
7
O
Interrupt output (open-drain)
Serial clock line
Serial data line
Power supply
8
SCL
I
9
SDA
VCC
I/O
P
10
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4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Maximum Ratings
Note:
Powersupply......................................................................................................-0.5Vto+6.0V
Voltageonan I/Opin..........................................................................GND-0.5Vto +6.0V
Inputcurrent.....................................................................................................................±20mA
Outputcurrenton anI/Opin ......................................................................................±50mA
Supplycurrent....................................................................................................................85mA
Groundsupplycurrent...................................................................................................100mA
Totalpowerdissipation................................................................................................200mW
Operationtemperature...............................................................................................-40~85℃
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Storagetemperature ................................................................................................-65~150℃
Maximum Junctiontemperature,Tj(max) ................................................................125℃
Static characteristics
VCC = 2.3 V to 5.5 V; GND = 0 V; Tamb= -40 °C to +85 °C; unless otherwise specified.
Table 2: Static characteristic
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Power supply
VCC
ICC
Supply voltage
Supply current
2.3
-
5.5
175
1
V
μA
μA
μA
V
Operating mode; VCC = 5.5 V; no load;
fSCL= 100 kHz
Standby mode; VCC = 5.5 V; no load;
VI = GND; fSCL= 0 kHz; I/O = inputs
Standby mode; VCC = 5.5 V; no load;
VI = VCC; fSCL= 0 kHz; I/O = inputs
-
104
0.25
0.25
1.16
Istb
Standby current
-
Istb
Standby current
1
[1]
VPOR
-
1.41
Power-on reset voltage
Input SCL, input/output SDA
Low level input voltage
V
IL
-0.5
-
-
+0.3VCC
V
V
V
High level input voltage
Low level output current
Leakage current
0.7VCC
5.5
-
IH
IOL
IL
VOL=0.4V
3
-1
-
7
-
mA
μA
pF
VI=VCC=GND
VI =GND
1
Ci
Input capacitance
5
10
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4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Conditions
Symbol
I/Os
Parameter
Min.
Typ.
Max.
Unit
VIL
VIH
Low level input voltage
High level input voltage
-0.5
+1.8
8
-
-
+0.81
V
V
5.5
-
VCC = 2.3 V; VOL = 0.5 V[2]
VCC = 2.3 V; VOL = 0.7 V[2]
VCC = 3.0 V; VOL = 0.5 V[2]
VCC = 3.0 V; VOL = 0.7 V[2]
VCC = 4.5 V; VOL = 0.5 V[2]
VCC =4.5 V; VOL = 0.7 V[2]
IOH=-8mA;VCC=2.3V[3]
10
13
14
19
17
24
-
mA
10
8
-
mA
mA
-
IOL
Low level output current
mA
mA
mA
10
8
-
-
10
1.8
1.7
2.6
2.5
4.1
4.0
-1
-
-
V
V
IOH=-10mA;VCC=2.3V[3]
IOH=-8mA;VCC=3.0V[3]
-
-
-
-
V
VOH
High level output voltage
IOH=-10mA;VCC=3.0V[3]
IOH=-8mA;VCC=4.75V[3]
IOH=-10mA;VCC=4.75V[3]
VCC=3.6V; VI=VCC=GND
-
-
V
-
-
V
-
-
V
ILI
Ci
input leakage current
Input capacitance
-
1
10
μA
pF
-
3.7
Interrupt
IOL
INT
Low level output current
High level output current
VOL=0.4V
VOL=0.4V
3
13
-
mA
uA
IOH
-1
+1
Select inputs A0,A1 and
RESET
VIL
VIH
IL
Low level input voltage
High level input voltage
Input leakage current
-0.5
+1.8
-1
-
-
+0.81
5.5
1
V
V
VI=VCC=GND
μA
Note:
[1]: VCC must be lowered to 0.2 V for at least 5 us in order to reset part.
[2]: Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3]: The total current sourced by all I/Os must be limited to 85 mA.
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4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Dynamic Characteristics
Table 3: Dynamic characteristics
Standard
mode I2C
Fast mode
I2C
Fast mode
Plus I2C
Unit
Test
Conditions
Symbol
Parameter
Min
Max
Min
0
Max
Min
Max
fSCL
tBUF
SCL clock frequency
0
4.7
4.0
4.7
4.0
-
100
400
0
0.5
0.26
0.26
0.26
-
1000
kHz
μs
μs
μs
μs
μs
ns
us
ns
μs
μs
ns
ns
bus free time between a STOP
and START condition
hold time (repeated) START
condition
set-up time for a repeated
START condition
-
1.3
0.6
-
-
tHD;STA
tSU;STA
tSU;STO
-
-
-
-
-
0.6
0.6
-
-
-
-
set-up time for STOP condition
data valid acknowledge time
data hold time
-
0.45
-
[1]
tVD;ACK
3.45
-
0.9
-
[2]
tHD;DAT
0
0
0
tVD;DAT
tSU;DAT
tLOW
tHIGH
tf
data valid time
-
3.45
-
0.9
-
-
0.45
-
data set-up time
250
-
100
1.3
0.6
-
50
0.5
0.26
-
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
-
-
-
-
-
-
-
fall time of both SDA and SCL
signals
rise time of both SDA and SCL
signals
300
1000
300
300
120
120
tr
-
-
-
pulse width of spikes that must
be
tSP
-
50
-
50
50
ns
suppressed by the input filter
Port timing
tv(Q)
Data output valid time[3]
Data input set-up time
Data input hold time
-
200
-
100
1
200
-
100
1
200
ns
ns
μs
tsu(D)
100
1
-
-
-
-
-
-
th(D)
Interrupt timing
tv(INT)
-
-
4
4
-
-
4
4
-
-
4
4
μs
μs
Valid time on pin
Reset time on pin
INT
INT
trst(INT)
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4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Standard
mode I2C
Fast mode
I2C
Fast mode
Plus I2C
Uint
Test
Conditions
Symbol
Parameter
Min
Max
Min
Max
Min
Max
RESET
timing
tw(rst)
tvrec(rst)
trst
Reset pulse width
Reset recovery time[4]
Reset time
25
-
25
0
-
-
-
25
-
ns
ns
us
0
1
-
-
0
1
-
-
1
Note:
[1]: tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]: tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]: tv(Q)measured from 0.7VCC on SCL to 50% I/O output.
[4]: To reset the device while actively communicating on the bus may cause glitches or errant STOP conditions. Upon reset, the
full delay will be the sum of trst and RC time constant of SDA bus.
Figure 2: timing parameters for INT signal
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PI4IOE5V9537
4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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PI4IOE5V9537 Block Diagram
Fig 3: Block diagram of PI4IOE5V9537
Note: All I/Os are set to inputs at reset.
Details Description
a. Device address
Table 4: Device address
b7(MSB) b6
b5
0
b4
1
b3
0
b2
0
b1
1
b0
Address Byte
1
0
R/W
Note: Read “1”, Write “0”
b. Registers
i. Command byte
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine
which of the following registers will be written or read.
Table 5: Command byte
Command
Register
0
1
2
3
Input port register
Output port register
Polarity inversion register
Configuration register
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4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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ii.Register 0: input port registers
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an
input or an output by Register 2. Writes to this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 6: Input port 0 register
Bit
7
I7
1
6
I6
1
5
I5
1
4
I4
1
3
2
1
0
Symbol
Default
I3
X
I2
X
I1
X
I0
X
iii. Register 1:Output port register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 3. Bit values
in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop
controlling the output selection, not the actual pin value.
Table 8: Output port 0 register
Bit
7
6
5
4
3
2
1
0
Symbol
O7
1
O6
1
O5
1
O4
1
O3
1
O2
1
O1
1
O0
1
Default
iv. Register 2: Polarity inversion register
This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’),
the Input port data polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 10: Polarity Inversion port 0 register
Bit
7
N7
0
6
N6
0
5
N5
0
4
N4
0
3
N3
0
2
N2
0
1
N1
0
0
N0
0
Symbol
Default
v.Register 3: Configuration registers
This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the corresponding port pin
is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with ‘0’), the corresponding
port pin is enabled as an output. At reset, the IOs are configured as inputs.
Table 12: Configuration port 0 register
Bit
7
C7
1
6
C6
1
5
C5
1
4
C4
1
3
C3
1
2
C2
1
1
C1
1
0
C0
1
Symbol
Default
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low power I/O port with interrupt and reset
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c. Power-on reset
When power is applied to VCC, an internal power-on reset holds the PI4IOE5V9537 in a reset condition until VCC has
reached VPOR. At that point, the reset condition is released and the PI4IOE5V9537 registers and SMBus state machine will
initialize to their default states. Thereafter, VCC must be lowered below 0.2 V to reset the device. For a power reset cycle, VCC
must be lowered below 0.2 V and then restored to the operating voltage.
d. Interrupt output
The open-drain interrupt output (INT) is activated when one of the port pins changes state and the pin is configured as an
input. The interrupt is de-activated when the input returns to its previous state or the Input Port register is read.
Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match
the contents of the input Port register .
e. I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be
raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should
be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists
between the pin and either VCC or GND.
Figure 4: Simplified schematic of I/Os
After power-on reset, all registers return to default values.
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4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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f. Bus Transaction
Data is transmitted to the PI4IOE5V9537 using the Write mode as shown in Figure 5.Data is read from the PI4IOE5V9537
using the read mode as shown in Figure 7.These devices do not implement an auto-increment function, so once a command byte
has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent.
Figure 5: Write to output registers
Figure 6: Write to polarity inversion registers
Figure 7: Read from registers
Note: Transfer can be stopped at any time by a STOP condition.
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4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Figure 8: Read Input port register
Note: Transfer of data can be stopped at any moment by a STOP condition. It is assumed that the command byte has previously been set to ‘00’ (read
Input Port register).
Application design-in information
Figure 9: Typical application
IO0 configured as outputs.
IO1, IO2, IO3 configured as inputs.
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low power I/O port with interrupt and reset
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Minimizing ICC when the I/Os are used to control LEDS
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in Figure 10. Since
the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VCC. The supply current, ICC, increases as VI
becomes lower than VCC.
Designs need minimize current consumption, such as battery power applications, should consider maintaining the I/O pins
greater than or equal to VCC when the LED is off. Figure 10 shows a high value resistor in parallel with the LED. Figure 11
shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VCC and
prevent additional supply current consumption when the LED is off.
Figure 10: High value resistor in parallel with the LED
Figure 11: Device supplied by a lower voltage
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4-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Mechanical Information
MSOP-10(U)
Ordering Information
Part No.
Package Code
Package
PI4IOE5V9537UE
U
10-PIN MINI SMALL OUTLINE PACKAGE(MSOP)
10-PIN MINI SMALL OUTLINE PACKAGE(MSOP),
Tape & Reel
PI4IOE5V9537UEX
U
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
2016-01-0029
PT0565-1
02/15/16
13
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