PI4IOE5V9539LEX [PERICOM]
interrupt and reset;
| 型号： | PI4IOE5V9539LEX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | interrupt and reset |
| 文件： | 总17页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI4IOE5V9539
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16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
higher driving capability, 5V tolerance, lower power
supply, individual I/O configuration, and smaller
packaging. It provides a simple solution when additional
I/O is needed for ACPI power switches, sensors, push
buttons, LEDs, fans, etc.
Features
Operation power supply voltage from 2.3V to 5.5V
16-bit I2C-bus GPIO with interrupt and reset
5V tolerant I/Os
The PI4IOE5V9539 consists of two 8-bit registers to
configure the I/Os as either inputs or outputs, and two 8-
bit polarity registers to change the polarity of the input
port register data. The data for each input or output is
kept in the corresponding Input port or Output port
register. All registers can be read by the system master.
The PI4IOE5V9539 open-drain interrupt output is
activated and indicate to the system when any input state
has changed. The power-on reset sets the registers to
their default values and initializes the device state
machine. The RESET pin causes the same reset/default
I/O input configuration to occur without de-powering the
device, holding the registers and I2C-bus state machine
in their default state until the RESET input is once again
HIGH.
Polarity inversion register
Active LOW interrupt output
Active LOW reset input
Low current consumption
0Hz to 400KHz clock frequency
Noise filter on SCL/SDA inputs
Power-on reset
ESD protection (4KV HBM and 1KV CDM)
Offered in two different packages: TSSOP-24 and
TQFN 4x4-24
Two hardware pins (A0, A1) vary the fixed I2C-bus
address and allow up to four devices to share the same
I2C-bus/SMBus.
Description
The PI4IOE5V9539 provide 16 bits of General
Purpose parallel Input/Output (GPIO) expansion for I2C-
bus/ SMBus applications. It includes the features such as
Pin Configuration
Figure 2: TQFN 4x4-24 ( Top View )
Figure 1: TSSOP-24 ( Top View )
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PI4IOE5V9539
16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Pin Description
Table 1: Pin Description
Pin
Name
Type
Description
Interrupt input (open-drain)
Address input 1
TSSOP24
TQFN24
1
22
O
I
INT
2
23
A1
Active low reset pin. Driving this pin LOW causes:
PI4IOE5V9539 to reset its state machine and register.
3
24
1
I
RESET
4
IO0_0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G
Port 0 input/output 0
Port 0 input/output 1
Port 0 input/output 2
Port 0 input/output 3
Port 0 input/output 4
Port 0 input/output 5
Port 0 input/output 6
Port 0 input/output 7
Ground
5
2
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
GND
6
3
7
4
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
A0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Port 1 input/output 0
Port 1 input/output 1
Port 1 input/output 2
Port 1 input/output 3
Port 1 input/output 4
Port 1 input/output 5
Port 1 input/output 6
Port 1 input/output 7
Address input 0
SCL
I
Serial clock line input
Serial data line open-drain
Supply voltage
SDA
I
VCC
P
* I = Input; O = Output; P = Power; G = Ground
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16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Maximum Ratings
Note:
Powersupply......................................................................................................-0.5Vto+6.0V
Voltageonan I/Opin..........................................................................GND-0.5Vto +6.0V
Inputcurrent.....................................................................................................................±20mA
Outputcurrenton anI/Opin ......................................................................................±50mA
Supplycurrent.................................................................................................................160mA
Groundsupplycurrent...................................................................................................200mA
Totalpowerdissipation................................................................................................200mW
Operationtemperature...............................................................................................-40~85℃
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Storagetemperature ................................................................................................-65~150℃
Maximum Junctiontemperature,Tj(max) ................................................................125℃
Static characteristics
VCC = 2.3 V to 5.5 V; GND = 0 V; Tamb= -40 °C to +85 °C; unless otherwise specified.
Table 2: Static characteristics
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Power supply
VCC
ICC
Supply voltage
Supply current
2.3
-
5.5
200
1
V
μA
uA
μA
V
Operating mode; VCC = 5.5 V; no load;
fSCL= 100 kHz
Standby mode; VCC = 5.5 V; no load;
VI = GND; fSCL= 0 kHz; I/O = inputs
Standby mode; VCC = 5.5 V; no load;
VI = VCC; fSCL= 0 kHz; I/O = inputs
-
-
-
-
135
0.25
0.25
1.16
Istb
Standby current
1
[1]
VPOR
1.41
Power-on reset voltage
Input SCL, input/output SDA
Low level input voltage
V
IL
-0.5
-
-
+0.3VCC
V
V
V
High level input voltage
Low level output current
Leakage current
0.7VCC
5.5
-
IH
IOL
IL
VOL=0.4V
3
-1
-
-
mA
μA
pF
VI=VCC=GND
VI =GND
-
1
Ci
Input capacitance
6
10
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16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Conditions
Symbol
I/Os
Parameter
Min.
Typ.
Max.
Unit
VIL
VIH
Low level input voltage
High level input voltage
-0.5
+1.8
8
-
-
+0.81
V
V
5.5
VCC = 2.3 V to 5.5 V; VOL = 0.5 V[2]
VCC = 2.3 V to 5.5 V; VOL = 0.7 V[2]
IOH=-8mA;VCC=2.3V[3]
9
11
-
-
-
-
-
-
-
-
-
mA
mA
V
IOL
Low level output current
10
1.8
1.7
2.6
2.5
4.1
4.0
IOH=-10mA;VCC=2.3V[3]
-
V
IOH=-8mA;VCC=3.0V[3]
-
V
VOH
High level output voltage
IOH=-10mA;VCC=3.0V[3]
-
V
IOH=-8mA;VCC=4.75V[3]
-
V
IOH=-10mA;VCC=4.75V[3]
-
V
High level input leakage
current
Low level input leakage
current
ILIH
ILIL
VCC=5.5V; VI=VCC
VCC=5.5V; VI=GND
-
-
-
-
1
μA
μA
-1
Ci
Input capacitance
Output capacitance
-
-
3.7
3.7
10
10
pF
pF
Co
Interrupt
INT
Low level output current
IOL
VOL=0.4V
3
-
-
mA
Select inputs A0,A1 and
RESET
VIL
VIH
IL
Low level input voltage
High level input voltage
Input leakage current
-0.5
+1.8
-1
-
-
+0.81
5.5
1
V
V
μA
Note:
[1]: VCC must be lowered to 0.2 V for at least 20 us in order to reset part.
[2]: Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be
limited to a maximum current of 100 mA for a device total of 200 mA.
[3]: The total current sourced by all I/Os must be limited to 160 mA.
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16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Dynamic Characteristics
Table 3: Dynamic characteristics
Standard
Fast mode I2C
Unit
mode I2C
Symbol
Parameter
Test Conditions
Min
Max
Min
0
Max
fSCL
tBUF
SCL clock frequency
0
4.7
4.0
4.7
4.0
-
100
400
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
ns
ns
ns
bus free time between a STOP and
START condition
-
1.3
0.6
0.6
0.6
-
-
-
tHD;STA
tSU;STA
tSU;STO
hold time (repeated) START condition
-
set-up time for a repeated START
condition
-
-
-
set-up time for STOP condition
data valid acknowledge time
data hold time
-
[1]
tVD;ACK
3.45
-
0.9
-
[2]
tHD;DAT
0
0
tVD;DAT
tSU;DAT
tLOW
data valid time
-
3.45
-
0.9
-
data set-up time
250
4.7
4.0
-
-
100
1.3
0.6
-
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
-
-
tHIGH
tf
-
-
300
1000
50
300
300
50
tr
-
-
pulse width of spikes that must be
suppressed by the input filter
tSP
-
-
Port timing
tv(Q)
Data output valid time[3]
Data input set-up time
Data input hold time
-
150
1
200
-
150
1
200
ns
ns
μs
tsu(D)
-
-
-
-
th(D)
Interrupt timing
tv(INT)
-
-
4
4
-
-
4
4
μs
μs
Valid time on pin
Reset time on pin
INT
INT
trst(INT)
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PI4IOE5V9539
16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Standard
Fast mode I2C
Unit
mode I2C
Symbol
Parameter
Test Conditions
Min
Max
Min
Max
RESET
timing
tw(rst)
tvrec(rst)
trst
Reset pulse width
Reset recovery time[4]
Reset time
25
0
-
-
-
25
0
-
-
-
ns
ns
us
1
1
Note:
[1]: tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]: tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]: tv(Q)measured from 0.7VCC on SCL to 50% I/O output.
[4]: Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
Upon reset, the full delay will be the sum of trst and RC time constant of SDA bus.
Figure 3: timing parameters for INT signal
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PI4IOE5V9539
16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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PI4IOE5V9539 Block Diagram
Figure 4: Block diagram of PI4IOE5V9539
Note: All I/Os are set to inputs at reset.
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16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Details Description
a. Device address
Table 4: Device address
b7(MSB) b6
b5
1
b4
0
b3
1
b2
b1
b0
Address Byte
1
1
A1
A0
R/W
Note: Read “1”, Write “0”
b. Registers
i. Command byte
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine
which of the following registers will be written or read.
Table 5: Command byte
Command
Register
0
1
2
3
4
5
6
7
Input port 0
Input port 1
Output port 0
Output port 1
Polarity inversion port 0
Polarity inversion port 1
Configuration port 0
Configuration port 1
ii.Register 0 and 1: input port registers
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an
input or an output by Register 3. Writes to this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 6: Input port 0 register
Bit
7
I0.7
X
6
I0.6
X
5
I0.5
X
4
I0.4
X
3
I0.3
X
2
I0.2
X
1
I0.1
X
0
I0.0
X
Symbol
Default
Table 7: Input port 1 register
Bit
7
6
5
4
3
2
1
0
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
iii. Register 2 and 3:Output port registers
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 6 and 7. Bit
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PI4IOE5V9539
16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-
flop controlling the output selection, not the actual pin value.
Table 8: Output port 0 register
Bit
7
O0.7
1
6
O0.6
1
5
O0.5
1
4
O0.4
1
3
O0.3
1
2
O0.2
1
1
O0.1
1
0
O0.0
1
Symbol
Default
Table 9: Output port 1 register
Bit
7
O1.7
1
6
O1.6
1
5
O1.5
1
4
O1.4
1
3
O1.3
1
2
O1.2
1
1
O1.1
1
0
O1.0
1
Symbol
Default
iv. Register 4 and 5: Polarity inversion registers
This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’),
the Input port data polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 10: Polarity Inversion port 0 register
Bit
7
N0.7
0
6
N0.6
0
5
N0.5
0
4
N0.4
0
3
N0.3
0
2
N0.2
0
1
N0.1
0
0
N0.0
0
Symbol
Default
Table 11: Polarity Inversion port 1 register
Bit
7
N1.7
0
6
N1.6
0
5
N1.5
0
4
N1.4
0
3
N1.3
0
2
N1.2
0
1
N1.1
0
0
N1.0
0
Symbol
Default
v.Register 6 and 7: Configuration registers
This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the corresponding port pin
is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with ‘0’), the corresponding
port pin is enabled as an output. At reset, the IOs are configured as inputs.
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PI4IOE5V9539
16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Table 12: Configuration port 0 register
Bit
7
C0.7
1
6
C0.6
1
5
C0.5
1
4
C0.4
1
3
2
C0.2
1
1
C0.1
1
0
C0.0
1
Symbol
C.3
Default
1
Table 13: Configuration port 1 register
Bit
7
C1.7
1
6
C1.6
1
5
C1.5
1
4
C1.4
1
3
C1.3
1
2
C1.2
1
1
C1.1
1
0
C1.0
1
Symbol
Default
c. Power-on reset
When power is applied to VCC, an internal power-on reset holds the PI4IOE5V9539in a reset condition until VCC has reached
VPOR. At that point, the reset condition is released and the PI4IOE5V9539 registers and SMBus state machine will initialize to
their default states. Thereafter, VCC must be lowered below 0.2 V to reset the device. For a power reset cycle, VCC must be
lowered below 0.2 V and then restored to the operating voltage.
d. RESET pin
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). In the PI4IOE5V9539 the registers
and SMBus/I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input
typically requires a pull-up to VCC.
e. I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be
raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should
be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists
between the pin and either VCC or GND.
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PI4IOE5V9539
16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Figure 5: Simplified schematic of I/Os
After power-on reset, all registers return to default values.
f. Bus Transaction
i. Writing to the port registers
Data is transmitted to the PI4IOE5V9539 by sending the device address and setting the least significant bit to a logic 0. The
command byte is sent after the address and determines which register will receive the data following the command byte. The eight
registers within the PI4IOE5V9539 are configured to operate as four register pairs. The four pairs are Input ports, Output ports,
Polarity inversion ports, and Configuration ports. After sending data to one register, the next data byte will be sent to the other
register in the pair. For example, if the first byte is sent to Output port 1 (register 3), then the next byte will be stored in Output
port 0(register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
Figure 6: Write to output registers
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Figure 7: Write to configuration registers
ii. Reading the port registers
In order to read data from the PI4IOE5V9539, the bus master must first send thePI4IOE5V9539 address with the least
significant bit set to a logic 0. The command byte is sent after the address and determines which register will be accessed. After a
restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by
the command byte will then be sent by the PI4IOE5V9539. Data is clocked into the register on the falling edge of the acknowledge
clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other
register in the pair. For example, if you read Input port 1, then the next byte read would be Input port 0. There is no limitation on
the number of data bytes received in one read transmission.
Figure 8: Read from registers
Note: Transfer can be stopped at any time by a STOP condition.
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Figure 9: Read Input port register
Note: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output
mode). It is assumed that the command byte has previously been set to ‘00’ (read Input Port register).
The interrupt is deactivated when the input returns to its previous state or the Input Port register is read. A pin configured as
an output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared
by a read of Port 1 or the other way around.
Note: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match
the contents of the Input Port register.
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Application design-in information
Figure 10: Typical application
Device address configured as 1110 100xb for this example.
IO0_0, IO0_4, IO0_5 configured as outputs.
IO0_1, IO0_2, IO0_3 configured as inputs.
IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs.
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Minimizing ICC when the I/Os are used to control LEDS
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in Figure 11. Since
the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VCC. The supply current, ICC, increases as VI
becomes lower than VCC.
Designs need minimize current consumption, such as battery power applications, should consider maintaining the I/O pins
greater than or equal to VCC when the LED is off. Figure 11 shows a high value resistor in parallel with the LED. Figure 12shows
VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VCC and prevent
additional supply current consumption when the LED is off.
Figure 11: High value resistor in parallel with the LED
Figure 12: Device supplied by a lower voltage
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Mechanical Information
TSSOP-24(L)
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TQFN 4x4-24(ZD)
Ordering Information
Part No.
Package Code
Package
Lead free and Green 24-pin TSSOP24 (173mil wide),
Tape & Reel
PI4IOE5V9539LE
L
PI4IOE5V9539LEX
PI4IOE5V9539ZDEX
Note:
L
ZD
Lead free and Green 24-pin TSSOP24 (173mil wide)
Lead free and Green 24-pin TQFN4.0x4.0, Tape & Reel
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
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