PI4IOE5V9557WE [PERICOM]
SMBus I/O port with reset;
| 型号： | PI4IOE5V9557WE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | SMBus I/O port with reset |
| 文件： | 总15页 (文件大小：597K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI4IOE5V9557
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8-bit I2C-bus and SMBus I/O port with reset
Features
Description
Operation power supply voltage from 2.3V to 5.5V
8-bit I2C-bus GPIO with interrupt and reset
The PI4IOE5V9557 provide 8 bits of General Purpose
parallel Input/Output (GPIO) expansion for I2C-
bus/SMBus applications. It includes the features such as
higher driving capability, 5V tolerance, lower power
supply, individual I/O configuration, and smaller
packaging. It provides a simple solution when additional
I/O is needed for ACPI power switches, sensors, push
buttons, LEDs, fans, etc.
The PI4IOE5V9557 consists of an 8-bit register to
configure the I/Os as either inputs or outputs, and an 8-
bit polarity register to change the polarity of the input
port register. The data for each input or output is kept in
the corresponding Input port or Output port register. All
registers can be read by the system master.
5V tolerant I/Os
Polarity inversion register
Active LOW Reset Pin
Low current consumption
0Hz to 400KHz clock frequency
Noise filter on SCL/SDA inputs
Power-on reset
ESD protection (4KV HBM and 1KV CDM)
Offered in three different packages:SOIC-16,
TSSOP-16 and TQFN 4x4-16
The power-on reset sets the registers to their default
values and initializes the device state machine. The
RESET pin causes the same reset/default I/O input
configuration to occur without de-powering the device,
holding the registers and I2C-bus state machine in their
default state until the RESET input is once again HIGH.
Three hardware pins (A0, A1, A2) vary the fixed
I2C-bus address and allow up to eight devices to share
the same I2C-bus/SMBus.
Pin Configuration
Figure 2: TQFN 4x4-16 ( Top view )
Figure 1: SOIC-16/TSSOP-16 ( Top View )
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Pin Description
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Table 1: Pin Description
Pin
Name
SCL
SCA
A0
Type
I
Description
SO16 TSSOP16 TQFN16
1
15
16
1
Serial clock line
Serial data line
Address input 0
Address input 1
Address input 2
2
I
3
I
4
2
A1
I
5
3
A2
I
6
4
IO0
IO1
GND
IO2
IO3
IO4
IO5
IO6
IO7
I/O
I/O
G
input/output 0 (open-drain)
input/output 1
7
5
8
6
Supply ground
9
7
I/O
I/O
I/O
G
input/output 2
10
11
12
13
14
15
16
8
input/output 3
9
input/output 4
10
11
12
13
14
input/output 5
I/O
I/O
I
input/output 6
input/output 7
Active LOW reset input
Supply voltage
RESET
VCC
P
* I = Input; O = Output; P = Power; G = Ground
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Maximum Ratings
Note:
Powersupply......................................................................................................-0.5Vto+6.0V
Voltageonan I/Opin..........................................................................GND-0.5Vto +6.0V
Inputcurrent.....................................................................................................................±20mA
Outputcurrenton anI/Opin ......................................................................................±50mA
Supplycurrent...............................................................................................................±160mA
Groundsupplycurrent...................................................................................................200mA
Totalpowerdissipation................................................................................................400mW
Operationtemperature...............................................................................................-40~85℃
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Storagetemperature ................................................................................................-65~150℃
MaximumJunctiontemperature,Tj(max) ................................................................125℃
Static characteristics
VCC = 2.3 V to 5.5 V; GND = 0 V; Tamb= -40 °C to +85 °C; unless otherwise specified.
Table 2: Static characteristics
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Power supply
VCC
ICC
Supply voltage
Supply current
2.3
-
5.5
25
1
V
μA
uA
μA
mA
V
Operating mode; VCC = 5.5 V; no load;
fSCL= 100 kHz
-
-
-
-
-
19
Standby mode; VCC = 5.5 V; no load;
VI = GND; fSCL= 0 kHz; I/O = inputs
Standby mode; VCC = 5.5 V; no load;
VI = VCC; fSCL= 0 kHz; I/O = inputs
Standby mode; VCC = 5.5 V; every LED I/O at
VI=4.3V; fSCL= 0 kHz;
0.25
0.25
0.8
Istb
Standby current
1
Additional standby current
1
∆Istb
[1]
VPOR
1.16
1.41
Power-on reset voltage
Input SCL, input/output SDA
V
Low level input voltage
High level input voltage
Low level output current
Leakage current
-0.5
-
-
+0.3VCC
V
V
IL
V
IH
0.7VCC
5.5
-
IOL
IL
VOL=0.4V; VCC=2.3V
VI=VCC or GND
VI =GND
3
-1
-
-
mA
μA
pF
-
1
Ci
Input capacitance
6
10
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Conditions
Symbol
I/Os
Parameter
Min.
Typ.
Max.
Unit
VIL
VIH
IOL
Low level input voltage
High level input voltage
Low level output current
-0.5
-
-
+0.81
V
V
+1.8
5.5
-
VCC =2.3 V; VOL = 0.5 V[2]
Except pin IO0; VOH=2.4V[3]
pin IO0; VOH=4.6V[3]
8
4
-
10
-
mA
mA
uA
uA
-
IOH
High level output current
-
1
pin IO0; VOH=3.3V[3]
-
-
1
Low level input leakage
current
ILI
VCC=5.5V; VI=GND
-1
-
1
μA
Ci
Input capacitance
Output capacitance
-
-
3.7
3.7
10
10
pF
pF
Co
Select inputs A0,A1,A2 and
RESET
VIL
VIH
IL
Low level input voltage
High level input voltage
Input leakage current
-0.5
+1.8
-1
-
-
+0.81
5.5
1
V
V
μA
Note:
[1]: VCC must be lowered to 0.2 V for at least 20us in order to reset part.
[2]: The total mount sunk by all I/Os must be limited to 100mA and 25 mA per bit.
[3]: The total current sourced by all I/Os must be limited to85mA and 20mA to bit
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Dynamic Characteristics
Table 3: Dynamic characteristics
Standard
mode I2C
Fast mode I2C
Unit
Symbol
Parameter
Test Conditions
Min
Max
Min
0
Max
fSCL
tBUF
SCL clock frequency
0
4.7
4.0
4.7
4.0
-
100
400
kHz
μs
μs
μs
μs
μs
ns
us
ns
μs
μs
ns
ns
ns
bus free time between a STOP and
START condition
-
1.3
0.6
0.6
0.6
-
-
-
tHD;STA
tSU;STA
tSU;STO
hold time (repeated) START condition
-
set-up time for a repeated START
condition
-
-
set-up time for STOP condition
data valid acknowledge time
data hold time
-
3.45
-
-
[1]
tVD;ACK
0.9
-
[2]
tHD;DAT
0
0
tVD;DAT
data valid time
-
3.45
-
-
0.9
-
tSU;DAT
data set-up time
250
4.7
4.0
-
100
1.3
0.6
-
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
-
-
tHIGH
-
-
tf
300
1000
50
300
300
50
tr
-
-
pulse width of spikes that must be
suppressed by the input filter
tSP
-
-
Port timing
Pin IO0
-
-
250
200
-
-
-
250
200
-
ns
ns
ns
ns
tv(Q)
Data output valid time[3]
Pin IO1 to IO7
tsu(D)
th(D)
Data input set-up time
Data input hold time
0
0
200
-
200
-
Reset timing
tw(rst)
Reset pulse width
Reset recovery time
Reset time
25
0
-
-
-
25
0
-
-
-
ns
ns
us
trec(rst)
trst
1
1
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Note:
[1]: tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]: tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]: tv(Q)measured from 0.7VCC on SCL to 50% I/O output.
PI4IOE5V9557Block Diagram
Figure3: Block diagram
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Figure 4: Simplified schematic of IO0
Figure 5: Simplified schematic of IO1 to IO7
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Details Description
a. Device address
Following a START condition the bus master must output the address of the slave it is accessing. The address of the
PI4IOE5V9557 is shown in. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address
pins and they must be pulled HIGH or LOW.
Table 4: Device address
b7(MSB) b6
b5
1
b4
1
b3
b2
b1
b0
Address Byte
0
0
A2
A1
A0
R/W
Note: Read “1”, Write “0”
b. Control register
Following the successful acknowledgement of the slave address, the bus master will send a byte to the PI4IOE5V9557, which
will be stored in the control register. This register can be written and read via the I2C-bus.
Table 5: Control register
b7(MSB) b6
b5
b4
b3
b2
b1
b0
Address Byte
0
0
0
0
0
0
D1
D0
Table 6: D0 and D1 definition
D1
0
D0 Name
Access
Description
0
1
0
1
Register 0
Read-only
Read/write
Read/write
Read/write
Input port register
Output port register
0
Register 1
Register 2
Register 3
1
Polarity inversion register
Configuration register
1
c. Register description
i. Register 0: Input port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an
input or an output by the Configuration register. Writes to this register have no effect.
Table 7: Input port register
Bit
7
6
5
4
3
2
1
0
Symbol
I7
I6
I5
I4
I3
I2
I1
I0
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ii.Register 1: Output port register
This register reflects the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this
register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling
the output selection, not the actual pin value.
Table 8: Output port register
Bit
7
6
5
4
3
2
1
0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Default
0
0
0
0
0
0
0
0
iii. Register 2: Polarity inversion register
This register enables polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set
(written with logic 1), the corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with logic 0), the
corresponding port pin’s original polarity is retained.
Table 9: Polarity inversion register
Bit
7
6
5
4
3
2
1
0
Symbol
N7
N6
N5
N4
N3
N2
N1
N0
Default
1
1
1
1
0
0
0
0
iv. Register 3: Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an
input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output.
Table 10: Configuration register
Bit
7
C7
1
6
C6
1
5
C5
1
4
C4
1
3
C3
1
2
C2
1
1
C1
1
0
C0
1
Symbol
Default
d. Power-on reset
When power is applied to VCC, an internal Power-On Reset (POR) holds the PI4IOE5V9557 in a reset condition until VCC
has reached VPOR. At that point, the reset condition is released and the PI4IOE5V9557 registers and I2C-bus/SMBus state
machine will initialize to their default states. Thereafter, VCC must be lowered below 0.2 V to reset the device.
e. RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). ThePI4IOE5V9557 registers and
SMBus/I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input requires a
pull-up resistor to VCC if no active connection is used.
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i. Bus transactions
Data is transmitted to the PI4IOE5V9557 registers using Write Byte transfers. Data is read from the PI4IOE5V9557 registers
using Read and Receive Byte transfers.
Figure 6: Write to output registers
Figure 7: Write to I/O configuration or polarity inversion registers
Figure 8: Read from register
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Figure 9: Read input port register
Note: This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge
phase is valid (output mode). Input data is lost.
Application design-in information
Figure 10: Typical application
Device address configured as 0011100x for this example.
IO0, IO4, IO5 configured as outputs.
IO1, IO2, IO3 configured as inputs.
IO6, IO07 are not used.
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Minimizing ICC when the I/Os are used to control LEDS
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in Figure 11. Since
the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VCC. The supply current, ICC, increases as VI
becomes lower than VCC.
Designs need minimize current consumption, such as battery power applications, should consider maintaining the I/O pins
greater than or equal to VCC when the LED is off. Figure 11 shows a high value resistor in parallel with the LED. Figure 12shows
VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VCC and prevent
additional supply current consumption when the LED is off.
Figure 11: High value resistor in parallel with the LED
Figure 12: Device supplied by a lower voltage
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Mechanical Information
SOIC-16(W)
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TSSOP-16(L)
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TQFN 4x4-16(ZY)
Ordering Information
Part No.
PI4IOE5V9557WE
PI4IOE5V9557WEX
PI4IOE5V9557LE
Package Code
Package
16-Pin,150 mil Wide SOIC
16-Pin,150 mil Wide SOIC,Tape & Reel
Lead free and Green 16-pin TSSOP16(173mil wide)
Lead free and Green 16-pin TSSOP16(173mil wide)
Tape &Reel
W
W
L
PI4IOE5V9557LEX
L
PI4IOE5V9557ZYEX
ZY
Lead free and Green 16-pin TQFN4.0x4.0, Tape & Reel
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
2015-07-0028
PT0552-2
8/18/15
15
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