PI4ULS5V102UE [PERICOM]
2-Bit Universal Bi-directional Level Shifter with Automatic Direction Control & Advance Package Solution;
| 型号： | PI4ULS5V102UE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | 2-Bit Universal Bi-directional Level Shifter with Automatic Direction Control & Advance Package Solution 光电二极管 逻辑集成电路 |
| 文件： | 总12页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI4ULS5V102
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2-Bit Universal Bi-directional Level Shifter
with Automatic Direction Control & Advance Package Solution
Features
Description
This 2-bit non-inverting translator uses two separate
configurable power-supply rails. The A port is designed
to track VCCA. VCCA accepts any supply voltage from
1.2V to 3.6V. The B port is designed to track VCCB. VCCB
accepts any supply voltage from 1.65V to 5.5V. This
allows for universal low-voltage bidirectional translation
between any of the 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, and
1.2V to 3.6V on A Port and 1.65V to 5.5V on B Port
(VCCA ≤ VCCB
VCC Isolation Feature – If Either VCC Input Is at
GND, All Outputs Are in the High-Impedance State
OE Input Circuit Referenced to VCCA
Low Power Consumption, 5 μA Max ICC
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100mA Per JESD
78, Class II
)
5V voltage nodes. VCCA should not exceed VCCB
.
When the output-enable (OE) input is low, all outputs
are placed in the high-impedance state.
ESD Protection Exceeds JESD 22
A Port
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through
the device when it is powered down.
2500-V Human-Body Model (A114-F)
200-V Machine Model (A115-A)
1500-V Charged-Device Model (C101D)
B Port
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pull-
down resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
15-kV Human-Body Model (A114-F)
200-V Machine Model (A115-A)
1500-V Charged-Device Model (C101D)
Pin Assignment
Function Block Diagram
1
2
OE
D
C
B
A
1
A2
2
A1
OE
A2
B2
D
C
B
A
Channel 2
VCCA
GND VCCB
B2 B1
A1
B1
Channel 1
CSP-8 (Bottom View)
Pin Description
Pin Name
Description
B1, B2
GND
Input/output B. Referenced to VCCB
Ground.
.
A port supply voltage. 1.2 V ≤VCCA≤ 3.6 V and
VCCA≤VCCB.
Input/output A. Referenced to VCCA.
3-State output. Pull OE low to place all outputs in
VCCA
A1, A2
OE
3-state mode. Referenced to VCCA
.
VCCB
B port supply voltage. 1.65 V ≤VCCB≤ 5.5 V.
MSOP-8 (Top View)
2015-09-0011
PT0334-4
10/20/15
1
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Maximum Ratings*1
Min
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
Max
4.6
6.5
4.6
6.5
Unit
VCCA
VCCB
Supply voltage range
Input voltage range
V
A port
B port
A port
B port
A port
B port
VI
VO
VO
V
V
V
4.6
6.5
VCCA + 0.5
VCCB + 0.5
-50
Voltage range applied to any output in the high-impedance or
power-off state
Voltage range applied to any output in the high or low state*2
IIK
IOK
IO
Input clamp current, VI < 0
Output clamp current, VO < 0
Continuous output current
mA
mA
mA
mA
℃
-50
±50
±100
150
IO
Tstg
Continuous current through VCCA, VCCB, or GND
Storage temperature range
-65
*1 Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
*2 The value of VCCA and VCCB are provided in the recommended operating conditions table.
Recommend Operation Conditions(1)(2)
Parameter
VCCA
Description
VCCA
-
-
VCCB
-
-
Min
1.2
1.65
Max
3.6
5.5
Unit
Supply voltage
V
VCCB
Data
inputs
1.2V to
3.6V
1.2V to
3.6V
1.2V to
3.6V
1.2V to
3.6V
1.2V to
3.6V
1.65V to
5.5V
1.65V to
5.5V
1.65V to
5.5V
1.65V to
5.5V
VCCI *
VCCI
5.5
0.65(3)
VIH
High-level input voltage
Low-level input voltage
V
VCCA
0.7
*
OE input
Data
inputs
VCCI *
0
0
0.35(3)
VIL
VO
V
V
VCCA
0.3
*
OE input
A port
B port
0
0
3.6
5.5
Voltage range applied to any output in the
high-impedance or power-off state
1.65V to
5.5V
A
inputs
port 1.2V to
3.6V
1.65V to
5.5V
1.65V to
3.6V
4.5V to
5.5V
-
-
40
40
Input transition rise or fall rate
ns/V
△t/△v
B
inputs
port 1.2V to
3.6V
-
30
85
TA
Operating free-air temperature
-
-
-40
℃
(1) The A and B sides of an unused data I/O pair must be held in the same state, i.e., both at VCCI or both at GND.
(2) VCCA must be less than or equal to VCCB and must not exceed 3.6 V.
(3) VCCI is the supply voltage associated with the input port.
2015-09-0011
PT0334-4
10/20/15
2
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
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DC Electrical Characteristics(1)(2)
TA = 25℃
-40 to 85℃
Parameter
Test Conditions
VCCA
VCCB
Unit
Min
Typ
Max
Min
Max
1.2V
1.0
1.1
1.2
-
-
VOHA
IOH = -20μA
-
-
V
VCCA
- 0.4
-
1.4V to 3.6V
-
-
-
-
1.2V
1.4V to 3.6V
0.0
-
0.09
-
0.4
-
-
0.4
V
V
VOLA
IOL = 20μA
-
VCCB
- 0.4
-
VOHB
VOLB
IOH = -20μA
-
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
-
-
-
-
-
-
-
-
IOL = 20μA
VI = VCCI or
GND
VI or VO = 0 to
3.6V
-
0.4
±2
V
II
OE
1.2 to 3.6V
±1
-
-
-
-
μA
A port
B port
0V
0V to 5.5V
0V
-
-
-
-
-
-
±1
±1
±1
±2
±2
±2
Ioff
μA
μA
μA
VI or VO = 0 to
5.5V
0 to 3.6V
1.2 to 3.6V
A or B
port
IOZ
OE = GND
1.65V to 5.5V
1.2V
1.4V to 3.6V
3.6V
0V
1.2V
1.4V to 3.6V
3.6V
0V
1.2V
1.4V to 3.6V
1.65V to 5.5V
1.65V to 5.5V
0V
0.0
-
-
-
0
-
-
-
0.0
-
0.06
-
-
-
2.3
-
-
-
2.4
-
5.0
-
-
-
5.0
-
-
-
8.0
-
-
-
-
-
-
-
-
-
-
-
-
5
2
-2
-
5
-2
2
-
VI = VCCI or
GND, Io = 0
ICCA
5.5V
1.65V to 5.5V
1.65V to 5.5V
0V
5.5V
1.65V to 5.5V
1.65V to 5.5V
VI = VCCI or
GND, Io = 0
ICCB
μA
VI = VCCI or
GND, Io = 0
ICCA + ICCB
μA
μA
8
VI = VCCI or
GND, Io = 0, OE
= GND
1.2V
1.4V to 3.6V
1.2V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
0.0
-
0.05
0.4
-
-
-
-
-
-
3
-
ICCZA
-
2.3
-
VI = VCCI or
GND, Io = 0, OE
= GND
0.0
-
5.0
-
ICCZB
μA
1.4V to 3.6V
1.2 to 3.6V
1.65V to 5.5V
1.65V to 5.5V
5
Ci
Cio
OE
A port
B port
-
-
-
-
-
2.5
5
11
-
-
-
-
-
-
3
6
14
pF
pF
1.2 to 3.6V
1.65V to 5.5V
(1) VCCI is the supply voltage associated with the input port.
(2) VCCO is the supply voltage associated with the output port.
2015-09-0011
PT0334-4
10/20/15
3
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
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AC Electrical Characteristics
Timing requirements
a. TA = 25℃, VCCA = 1.2V
VCCB = 1.8V
VCCB = 2.5V
VCCB = 3.3V
VCCB = 5V
Unit
TYP
20
50
TYP
20
50
TYP
20
50
TYP
20
50
Data rate
Mbps
ns
tW
Pulse duration
Data inputs
b. TA = 25℃, VCCA = 1.5±0.1V
VCCB=1.8±0.15V
VCCB=2.5±0.2V
VCCB=3.3±0.3V
VCCB=5±0.5V
Unit
MIN
-
MAX
40
-
MIN
-
MAX
40
-
MIN
-
MAX
40
-
MIN
MAX
Data rate
-
25
40
-
Mbps
ns
tW
Pulse duration
Data inputs
25
25
25
c. TA = 25℃, VCCA = 1.8±0.15V
VCCB=1.8±0.15V
VCCB=2.5±0.2V
VCCB=3.3±0.3V
MIN MAX
VCCB=5±0.5V
MIN MAX
Unit
MIN
-
MAX
60
-
MIN
-
MAX
60
-
Data rate
-
60
-
60
Mbps
ns
tW
Pulse duration
Data inputs
17
17
17
-
17
-
d. TA = 25℃, VCCA = 2.5±0.2V
VCCB=2.5±0.2V
VCCB=3.3±0.3V
VCCB=5±0.5V
Unit
MIN
-
MAX
100
-
MIN
-
MAX
100
-
MIN
-
MAX
100
-
Data rate
Mbps
ns
tW
Pulse duration
Data inputs
10
10
10
e. TA = 25℃, VCCA = 3.3±0.3V
VCCB=3.3±0.3V
VCCB=5±0.5V
MAX
Unit
MIN
MAX
MIN
-
10
Data rate
-
10
100
-
100
-
Mbps
ns
tW
10
-
Switching characteristics
a. TA = 25℃, VCCA = 1.2V
VCCB=1.8V
TYP
6.9
VCCB=2.5V
TYP
5.7
VCCB=3.3V
VCCB=5V
TYP
5.5
From
To
Parameter
Unit
ns
(INPUT) (OUTPUT)
TYP
5.3
6
0.2
0.2
0.4
0.2
A
B
B
A
A
B
A
B
tpd
ten
7.4
0.2
0.2
0.4
6.4
0.2
0.2
0.4
5.8
0.2
0.2
0.4
OE
OE
μs
tdis
μs
0.2
0.2
0.2
A-port rise and fall
times
B-port rise and fall
trA, tfA
trB, tfB
4.2
2.1
4.2
1.5
4.2
1.2
4.2
1.1
ns
ns
times
Channel-to-channel
tSK(O)
0.5
20
0.5
20
0.5
20
1.4
20
ns
skew
-
Max data rate
Mbps
2015-09-0011
PT0334-4
10/20/15
4
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
b. TA = 25℃, VCCA = 1.5±0.1V
VCCB=1.8±0.15V VCCB = 2.5±0.2V VCCB=3.3±0.3V VCCB = 5±0.5V
From
To
Parameter
tpd
Unit
ns
(INPUT) (OUTPUT)
MIN
1.4
0.9
-
-
-
-
MAX
12.9
14.2
0.5
MIN
1.2
0.7
-
-
-
-
MAX
10.1
12
MIN
1.1
0.4
-
-
-
-
MAX MIN
MAX
9.9
13.7
0.5
A
B
B
A
A
B
A
B
10
0.8
11.7
0.5
0.5
0.5
0.5
0.3
0.5
-
-
-
-
ten
OE
OE
μs
0.5
0.5
0.5
0.5
0.5
0.5
tdis
μs
0.5
0.5
0.5
A-port rise and fall
times
B-port rise and fall
times
trA, tfA
trB, tfB
1.4
0.9
5.1
4.5
1.4
0.6
5.1
3.2
1.4
0.5
5.1
2.8
1.4
0.4
5.1
2.7
ns
ns
Channel-to-channel
skew
tSK(O)
-
0.5
-
-
0.5
-
-
0.5
-
-
0.5
-
ns
Max data rate
40
40
40
40
Mbps
c. TA = 25℃, VCCA = 1.8±0.15V
VCCB=1.8±0.15V VCCB=2.5±0.2V
VCCB=3.3±0.3V
VCCB=5±0.5V
From
To
Parameter
tpd
Unit
ns
(INPUT) (OUTPUT)
MIN
1.6
MAX
11
MIN
1.4
MAX
7.7
MIN
1.3
1
MAX
6.8
7.6
MIN
1.2
MAX
6.5
A
B
B
A
A
B
A
B
1.5
12
1.3
8.4
0.9
7.1
-
-
-
-
0.3
0.3
0.5
0.5
-
-
-
-
0.25
0.25
0.5
0.25
0.25
0.5
-
-
-
-
0.25
0.25
0.5
ten
OE
OE
μs
tdis
μs
0.5
0.5
0.5
A-port rise and fall
times
B-port rise and fall
times
trA, tfA
trB, tfB
1
4.2
4.5
1
4.1
3.2
1
4.1
2.8
1
4.1
2.7
ns
0.9
0.6
0.5
0.4
ns
Channel-to-channel
skew
tSK(O)
-
0.5
-
-
0.5
-
-
0.5
-
-
0.5
-
ns
Max data rate
60
60
60
60
Mbps
d. TA = 25℃, VCCA = 2.5±0.2V
VCCB=2.5±0.2V
VCCB=3.3±0.3V
VCCB=5±0.5V
From
To
Parameter
Unit
(INPUT) (OUTPUT)
MIN
1.1
MAX
6.3
MIN
1.0
MAX
5.2
MIN
0.9
MAX
4.7
A
B
B
A
A
B
A
B
tpd
ten
ns
μs
μs
ns
ns
1.2
6.6
1.1
5.1
0.9
4.4
-
-
-
-
0.25
0.25
0.5
-
-
-
-
0.2
0.2
0.4
0.4
-
-
-
-
0.2
0.2
035
0.35
OE
OE
tdis
0.5
A-port rise and fall
times
B-port rise and fall
times
trA, tfA
trB, tfB
0.8
0.7
3.0
3.0
0.8
0.5
3.0
2.8
0.8
0.4
3.0
2.7
Channel-to-channel
skew
tSK(O)
-
0.5
-
-
0.5
-
-
0.5
-
ns
Max data rate
100
100
100
Mbps
2015-09-0011
PT0334-4
10/20/15
5
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
e. TA = 25℃, VCCA = 3.3±0.3V
VCCB=3.3±0.3V
VCCB=5±0.5V
From
To
Parameter
tpd
Unit
ns
(INPUT) (OUTPUT)
MIN
0.9
MAX
4.7
MIN
0.8
MAX
4.0
A
B
B
A
A
B
A
B
1.0
4.9
0.9
3.8
-
-
-
-
0.2
0.2
0.3
0.3
-
-
-
-
0.2
0.2
0.3
0.3
ten
OE
OE
μs
tdis
μs
A-port rise and fall
times
B-port rise and fall
times
trA, tfA
trB, tfB
0.7
0.5
2.8
2.7
0.7
0.4
2.8
2.7
ns
ns
Channel-to-channel
skew
tSK(O)
-
0.5
-
-
0.5
-
ns
Max data rate
100
100
Mbps
Operating characteristics
VCCA
1.2V
5V
1.2V
1.5V
1.8V
1.8V
VCCB
2.5V
2.5V
2.5V
5V
3.3V
Parameter
Test Conditions
Unit
3.3V
to
1.8V
1.8V
5.5V
TYP
9
TYP
7.8
12
TYP
10
11
TYP
9
11
TYP
8
11
TYP
8
11
TYP
8
11
A-port input, B-port output.
CpdA
CL=0, f=10 MHz,
tr = tf =1ns,
B-port input, A-port output.
11
OE=VCCA
(outputs enabled)
A-port input, B-port output.
B-port input, A-port output.
A-port input, B-port output.
B-port input, A-port output.
A-port input, B-port output.
B-port input, A-port output.
38.1
25.4
0.01
0.01
0.01
0.01
28
18
0.01
0.01
0.01
0.01
28
18
0.01
0.01
0.01
0.01
28
18
0.01
0.01
0.01
0.01
29
18
0.01
0.01
0.01
0.01
30
21
0.01
0.01
0.01
0.02
30
21
0.01
0.01
0.03
0.04
CpdB
pF
CL=0, f =10 MHz,
tr = tf =1ns,
OE=GND
(outputs disabled)
CpdA
CpdB
2015-09-0011
PT0334-4
10/20/15
6
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Test circuit
1> Load circuit for Max data rate, pulse duration propagation delay output rise and fall time measurement
From Output
Under Test
1MΩ
15pF
2> Load circuit for enable/disable time measurement
2*Vcco
Open
50kΩ
S1
From Output
Under Test
TEST
S1
50kΩ
15pF
tPZL/tPLZ 2*Vcco
tPHL/tPHZ
Open
3> Timing Definitions for Propagation Delays and Enable/Disable Measurement
4> Voltage waveforms pulse duration
tw
VCCI
Input
VCCI/2
VCCI/2
0V
5> Notes
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR_10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. tPLH and tPHL are the same as tpd.
E. VCCI is the VCC associated with the input port.
F. VCCO is the VCC associated with the output port.
G. All parameters and waveforms are not applicable to all devices.
2015-09-0011
PT0334-4
10/20/15
7
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Principles of operation
Applications
Power Up
The PI4ULS5V102 can be used in level-translation
applications for interfacing devices or systems operating at
different interface voltages with one another.
During operation, ensure that VCCA ≤ VCCB at all times. During
power-up sequencing, VCCA ≥ VCCB does not damage the
device, so any power supply can be ramped up first. The
PI4ULS5V102 has circuitry that disables all output ports
when either VCC is switched off (VCCA/B = 0 V).
Architecture
The PI4ULS5V102 architecture(see Figure1) does not require
a direction-control signal to control the direction of data flow
from A to B or from B to A. In a dc state, the output drivers of
the PI4ULS5V102 can maintain a high or low, but are
designed to be weak, so that they can be overdriven by an
external driver when data on the bus starts flowing the
opposite direction.
Enable and Disable
The PI4ULS5V102 has an OE input that is used to disable the
device by setting OE = low, which places all I/Os in the high-
impedance (Hi-Z) state. The disable time (tdis) indicates the
delay between when OE goes low and when the outputs
acutally get disabled (Hi-Z). The enable time (ten) indicates
the amount of time the user must allow for the one-shot
circuitry to become operational after OE is taken high.
The output one shots detect rising or falling edges on the A or
B ports. During a rising edge, the one shot turns on the PMOS
transistors (T1, T3) for a short duration, which speeds up the
low-to-high transition. Similarly, during a falling edge, the
one shot turns on the NMOS transistors (T2, T4) for a short
duration, which speeds up the high-to-low transition. The
typical output impedance during output transition is 70 Ω at
VCCO=1.2 V to 1.8 V, 50 Ω at VCCO=1.8 V to 3.3 V, and 40 Ω
at VCCO=3.3 V to 5 V.
Pull-up or Pull-down Resistors on I/O Lines
The PI4ULS5V102 is designed to drive capacitive loads of up
to 70 pF. The output drivers of the PI4ULS5V102 have low dc
drive strength. If pullup or pulldown resistors are connected
externally to the data I/Os, their values must be kept higher
than 50 kΩ to ensure that they do not contend with the output
drivers of the PI4ULS5V102.
Input Driver Requirements
For the same reason, the PI4ULS5V102 should not be used in
applications such as I2C or 1-Wire where an open-drain driver
is connected on the bidirectional data I/O.
Typical IIN vs VIN characteristics of the PI4ULS5V102 are
shown in Figure 2. For proper operation, the device driving
the data I/Os of the PI4ULS5V102 must have drive strength of
at least ±2mA.
2015-09-0011
PT0334-4
10/20/15
8
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure1. Architecture of PI4ULS5V102 I/O Cell
Figure2. Typical IIN vs VIN Curve
Note:
A. VT is the input threshold voltage of the PI4ULS5V102 (typically VCCI/2).
B. VD is the supply voltage of the external driver.
2015-09-0011
PT0334-4
10/20/15
9
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mechanical Information
CSP-8
2015-09-0011
PT0334-4
10/20/15
10
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
MSOP-8
8
7
6
5
1
2
3
4
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
Note:
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MO-187E/AA
2015-09-0011
PT0334-4
10/20/15
11
PI4ULS5V102
2-Bit Universal Bi-directional Level
Shifter with Automatic Direction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Ordering Information
Part Number
PI4ULS5V102GAE
PI4ULS5V102UE
Package Code
Package
GA
U
Lead free and Green 8-pin CSP
Lead free and Green 8-pin MSOP
Notes:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
2015-09-0011
PT0334-4
10/20/15
12
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