PI6C100VX [PERICOM]
Processor Specific Clock Generator, 100MHz, CMOS, PDSO48, 0.300 INCH, 0.635 MM PITCH, SSOP-48;
| 型号： | PI6C100VX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Processor Specific Clock Generator, 100MHz, CMOS, PDSO48, 0.300 INCH, 0.635 MM PITCH, SSOP-48 电脑 PC 时钟 |
| 文件： | 总13页 (文件大小：585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C100
Precision Clock Synthesizer
for Desktop PCs
Features
Description
Four copies of CPU clock with V of 2.5V + 5%
ThePI6C100isahigh-speedlow-noiseclockgeneratordesignedto
workwiththePI6C180clockbuffertomeetallclockneedsforIntel
Architecture platforms. CPU and chipset clock frequencies of 66.6
MHz and 100 MHz are supported.
DD
100 MHz or 66 MHz operation
Eight copies of PCI clock, (synchronous with CPU clock) 3.3V
TwocopiesofIOAPICclock@14.31818MHz
Two copies of 48 MHz clock
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard
8-X.Powersequencingofthe3.3Vand2.5Vsuppliesisnotrequired.
ThreecopiesofRef.clock@14.31818MHz(3.3VTTL)
Low cost 14.31818 MHz crystal oscillator input
Spread spectrum modulation of CPU and PCI clocks for
reduced EMI
AnasynchronousPWRDWN#signalmaybeusedtoorderlypower
down (or up) the system.
Powermanagementcontrol
Isolated core V , V pins for noise reduction
DD SS
48-pinSSOPpackage(V48)
PinConfiguration
Block Diagram
48-Pin
V48
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Precision Clock Synthesizer
for Desktop PCs
PinDescription
Pin
Signal Name
Type
O
Qty.
3
Description
14.318 MHz clock output.
1,2,47
REF[0:2]
3
V
ground
power
I
1
Ground for REF[0:2] outputs
Power for REF[0:2] outputs
14.318 MHz crystal input.
14.318 MHz crystal output.
Ground for PCI clock outputs
Free running PCI clock output
Power for PCI clock outputs
SSREF
48
V
DDREF
1
4
5
XTAL_IN
1
XTAL_OUT
O
1
6,12,18
7
V
SSPCI
[0:2]
ground
O
3
PCICLK_F
[0:1]
1
9,15
V
DDPCI
power
2
8,10,11,13,
14,16,17
PCI clock outputs, TTL
compatible 3.3V
PCICLK[1:7]
O
7
19,33
20,32
21
V
[0:1]
[0:1]
power
ground
power
ground
O
2
2
1
1
2
2
Isolated power for core
DDCORE
V
Isolated ground for core
SSCORE
V
DD
48MHz
Isolated power for 48 MHz outputs
Isolated ground for 48 MHz outputs
48 MHz outputs
24
V 48MHz
SS
22,23
26,27
48MHz
SEL[0:1]
1
Logic select pins. LVTTL levels
Select pin for enabling 100 MHz or 66 MHz
H = 100 MHz. L = 66 MHz
25
SEL100/66#
I
1
1
29
30
PWRDWN#
CPUSTOP#
PCI_STOP#
I
Powers down device when held LOW
Stops CPU clocks LOW if held LOW
Stops PCI clocks LOW if held LOW
Power for CPU outputs
I
I
31
1
2
2
4
1
1
2
1
1
37,41
34,38
V [0:1]
DDCPU
power
ground
O
V [0:]
SSPCU
Ground for CPU outputs
35,36,39,40 CPUCLK[0:3]
CPU and Host clock outputs 2.5V
Ground for APIC outputs
43
46
V
SSAPIC
ground
power
O
V
DDAPIC
Power for APIC outputs
44,45
28
APIC[0:1]
SPREAD#
NC
APIC outputs @2.5V. 14.31818 MHz
Enables Spread Spectrum feature when LOW
Reserved for future modification
I
42
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Precision Clock Synthesizer
for Desktop PCs
Select Functions
SEL100/66#
SEL1
SEL0
Function
Hi-Z
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
66 MHz active
Test mode
Reserved
Reserved
100 MHz active
Outputs
PCI, PCI F 48MHz
Function
Description
CPU
REF[0:2]
IOAPIC
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Test Mode
Note:
TCLK/2
TCLK/6
TCLK/2
TCLK
TCLK
TCLK is a test clock over driven on the XTAL_IN input during test mode.
ClockEnableConfiguration
Other
Clocks
CPU_STOP#
PCI_STOP#
PWR_DWN# CPUCLK PCICLK
Crystal VCO's
X
0
X
0
0
1
1
low
low
low
low
low
Stopped
running
running
off
off
running
running
running
running
0
1
33 MHz
100/66
MHz
1
1
0
1
1
1
low
running
running
running
running
running
running
100/66
MHz
33 MHz
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Precision Clock Synthesizer
for Desktop PCs
CPU_STOP# is an input signal used to turn off the CPU clocks All other clocks continue to run while the CPU clocks are disabled.
for low power operation. CPU_STOP# is asserted asynchronously The CPU clocks are always stopped in a low state and started
by the external clock control logic with the rising edge of free guaranteeing that the high pulse width is a full pulse. CPU clock
running PCI clock and is internally synchronized to the external on latency is 2 or 3 CPU clocks and CPU clock off latency is 2 or
PCICLK_F output.
3 CPU clocks.
PowerManagementTiming
Latency
Signal
Signal State
No. of rising edges of free running PCICLK
CPU_STOP#
0 (disabled)
1 (enabled)
1
1
PCI_STOP#
PWR_DWN#
0 (disabled)
1
1 (enabled)
1
1 (normal operation)
0 (power down
3ms
2 max.
Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs between
when the clock disable goes low/high to when the first valid clock comes out of the device.
2. Power up latency is from when PWR_DWN# goes inactive (high) to when the first valid clocks
are driven from the device.
CPU_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3 CPU_STOP# is an input signal that is made synchronous to the free running PCICLK_F.
4. ON/OFF latency shown is 2 CPU clocks.
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Precision Clock Synthesizer
for Desktop PCs
PCI_STOP# is an input signal used to turn off the PCI clocks for low power operation. PCI clocks are stopped in the low state and started
with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic.
PCI_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
ThePWR_DWN#isusedtoplacethedeviceinaverylowpowerstate. PWR_DWN#isanasynchronousactivelowinput. Internalclocks
are stopped after the device is put in power down mode. The power on latency is less than 3ms. PCI_STOP# and CPU_STOP# are dont
cares during the power down operations. The REF0 clock is stopped in the LOW state as soon as possible.
PWR_DWN# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
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Precision Clock Synthesizer
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
StorageTemperature ...................................................................65°Cto+150°C
Ambient Temperature with Power Applied .................................... 0°Cto+70°C
3.3V Supply Voltage to Ground Potential .......................................0.5Vto+4.6V
2.5V Supply Voltage to Ground Potential .......................................0.5Vto+3.6V
DC Input Voltage ............................................................................0.5Vto+4.6V
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
abovethoseindicatedintheoperationalsectionsofthis
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC Electrical Characteristics (V
3 = +3.3V ± 5%, V
2 = +2.5V ± 5%, T = 0°C to +70°C)
DDQ A
DDQ
Parameters
Description
Test Conditions
Min.
Typ.
Max.
+5
Units
I
IL
Input Leakage Current 0V < V < V
IN
-5
µA
DD
V
IL
Input Low Voltage
V
SS
-0.3
0.8
V
Input High Voltage
Output Low Voltage
Output High Voltage
@V
+2.0
2
V
+0.3
IH
DD
DD
V
V
OL
I
OL
= 1mA, V = Min.
0.4
DD
V
OH
I
= -1mA, V = Min.
OL DD
V
= 2.625V, PWRDWN#=0
= Max.
DDQ2
I
100
72
µA
mA
µA
mA
DDQ2
C
LOAD
V
DDQ2
=2.625V @ 66.66 MHz
= Max.
I
2.5V Supply Current
3.3V Supply Current
DDQ2
C
LOAD
V
DDQ2
=2.625V @ 100 MHz
= Max.
I
100
500
170
170
DDQ2
C
LOAD
V
DDQ3
=3.465V, PWRDWN#=0
= Max.
I
DDQ3
C
LOAD
V
DDQ3
=3.465V, 66.66 MHz
= Max.
I
DDQ3
C
LOAD
V
DDQ3
=3.465V, 100 MHz
= Max.
I
DDQ3
C
LOAD
C
Input Capacitance
Output Capacitance
Pin Conductance
5
6
IN
pF
C
OUT
L
PIN
7
nH
°C
T
Ambient Temperature No Airflow
0
70
A
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Precision Clock Synthesizer
for Desktop PCs
DC Operating Specifications
Symbol
Parameters
[0-1] = 3.3V ± 5%
Conditions
Min.
Max.
Units
Input Voltage, V
DDCORE
V
Input high voltage
Input low voltage
Input leakage current
V
2.0
V
+0.3
IH3
DDCORE
DDCORE
V
V
V
-0.3
0.8
IL3
SS
I
0 < V < V
DDCORE
-5
+5
µA
IL
IN
[0-1]
DDAPIC DDCPU
Output Voltage = 2.5V ± 5% V
, V
V
Output high voltage
Output low voltage
I
= -1mA
= 1mA
2.0
2.4
2.4
OH2
OH
V
V
V
V
I
OL
0.4
OL2
Output Voltage = 3.3V ± 5% V
DDREF
V
OH3
Output high voltage
Output low voltage
I
OH
= -1mA
= 1mA
OL
V
I
0.4
OL3
Output Voltage = 3.3V ± 5% V
[0-1]
DDCPI
V
POH
PCI Bus output high voltage
I
OH
= -1mA
= 1mA
OL
V
PCI Bus output low voltage
I
0.55
POL
C
Input pin capacitance
5
22.5
6
IN
pF
C
X
TAL
pins capacitance
13.5
18.0
0
XTAL
C
Output pin capacitance
Pin Inductance
OUT
L
PIN
7
nH
°C
T
Ambient Temperature
No airflow
70
A
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Precision Clock Synthesizer
for Desktop PCs
Buffer Specifications
Buffer Name
CPU
V
Range(V)
Impedance (Ω)
13.5 - 45
9 - 30
Buffer Type
Type 1
DD
2.375 -2.625
2.375 -2.625
3.135 - 3.465
3.135 - 3.465
APIC
Type 2
48MHz, REF
PCI
20 - 60
Type 3
12 - 55
Type 4
Type 1: CPU Clock Buffers (2.5V)
Symbol
Parameters
Pull-up current
Pull-up current
Pull-down current
Pull-down current
Conditions
= 1.0V
Min.
Typ.
Max. Units
I
V
-27
OHMIN
OUT
I
V
= 2.375V
-27
mA
OHMAX
OUT
I
V
= 1.2V
= 0.3V
27
OLMIN
OUT
I
V
OUT
30
OLMAX
t
2.5V Type 1 output rise edge rate 2.5V + /-5% @ 0.4V-2.0V
2.5V Type 1 output fall edge rate 2.5V + /-5% @ 2.0V-0.4V
1
1
4
RH
V/ns
4
t
FH
Type 2: APIC Buffers (2.5V)
Symbol
Parameters
Pull-up current
Pull-up current
Pull-down current
Pull-down current
Conditions
Min.
Typ.
Max.
Units
I
V
= 1.4V
= 2.5V
= 1.0V
= 0.2V
-36
OHMIN
OUT
I
V
OUT
-21
OHMAX
mA
I
V
OUT
36
OLMIN
I
V
OUT
31
4
OLMAX
t
RH
2.5V Type 2 output rise edge rate
2.5V Type 2 output fall edge rate
2.5V ±5% @0.4V-2.0V
2.5V ±5% @2.0V-0.4V
1
1
V/ns
t
FH
4
Type 3: 48MHz, REF Buffers (3.3V)
Symbol
Parameters
Pull-up current
Pull-up current
Pull-down current
Pull-down current
Conditions
Min.
Typ.
Max.
Units
I
V
OUT
= 1.0V
-29
OHMIN
I
V
= 3.135V
= 1.95V
OUT
-23
OHMAX
OUT
mA
I
V
29
OLMIN
I
V
OUT
= 0.4V
27
2
OLMAX
t
RH
3.3V Type 3 output rise edge rate 3.3V ±5% @0.4V-2.4V
3.3V Type 3 output fall edge rate 3.3V ±5% @2.4V-0.4V
0.5
0.5
V/ns
t
FH
2
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PI6C100
Precision Clock Synthesizer
for Desktop PCs
Type 4: PCI Clock Buffers (3.3V)
Symbol
Parameters
Pull-up current
Pull-up current
Pull-down current
Pull-down current
Conditions
= 1.0V
Min.
Typ. Max. Units
I
V
-33
OHMIN
OUT
I
V
= 3.135V
= 1.95V
OUT
-33
mA
OHMAX
OUT
I
V
30
OLMIN
I
V
OUT
= 0.4V
38
OLMAX
t
3.3V Type 4 output rise edge rate 3.3V ±5% @ 0.4V-2.4V
3.3V Type 4 output fall edge rate 3.3V ±5% @ 2.4V-0.4V
1
1
4
RH
V/ns
4
t
FH
AC Timing
66 MHz
100 MHz
Units
Figure 1. Host Clock to
PCI CLK Offset
Parameters
Host CLK period
Min.
15.0
5.2
Max. Min.
Max.
t
(2.5V)
(2.5V)
(2.5V)
(2.5V)
15.5
10.0
3.0
2.8
0.4
0.4
10.5
HKP
t
Host CLK high time
HKH
ns
t
Host CLK low time
5.0
HKL
t
Host CLK rise time
0.4
1.6
1.6
250
55
1.6
1.6
250
55
HRISE
t
(2.5V)
(2.5V)
Host CLK fall time
0.4
HFALL
t
Host CLK Jitter
ps
%
JITTER
Duty Cycle (2.5V)
(2.5V)
Measured at 1.25V
45
45
t
Host Bus CLK Skew
IO APIC Bus CLK Skew
Output enable delay
175
250
8.0
8.0
3
175
250
8.0
8.0
3
HSKW
ps
ns
t
IOSKW
t
, t
1.0
1.0
1.0
1.0
PZL PZH
t
, t
Output disable delay
PLZ PHZ
t
Host CLK Stabilization from power-up
PCI CLK period
ms
ns
HSTB
t
30.0
30.0
PKP
t
PCI CLK period stability
PCI CLK high time
500
500
ps
PKPS
t
12.0
12.0
12.0
12.0
PKH
ns
t
PCI CLK low time
PKL
t
PCI Bus CLK Skew
Host to PCI Clock Offset
PCI CLK Stabilization from power-up
500
4.0
3
500
4.0
3
ps
ns
PSKW
t
1.5
1.5
HPOFFSET
t
ms
PSTB
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PI6C100
Precision Clock Synthesizer
for Desktop PCs
Figure 1. Host Clock to PCI CLK Offset
Figure 2. Clock Output Waveforms
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PI6C100
Precision Clock Synthesizer
for Desktop PCs
Minimum and Maximum Expected Capacitive Loads
Clock
CPU Clocks (HCLK)
PCI Clocks (PCLK)
48 MHz Clock
REF
Min. Load Max. Load
Units
Notes
10
30
10
10
10
20
30
20
20
20
1 device load, possible 2 loads
Meets PCI 2.1 requirements
pF 1 device load
1 device load
2 device loads
APIC
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.
2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.
3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an
additional 500Wresistor inparallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for
CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still
within the specified values.
2. Minimize the number of vias of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
Ω
Ω
Ω
Ω
Ω
Ω
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PI6C100
Precision Clock Synthesizer
for Desktop PCs
PCB Layout Suggestion
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C2-C11 should be placed as close as possible
Recommended capacitor values:
C2-C11 .............. 0.1µF,ceramic
C1,C12 ........... 22µF
to their respective V
.
DD
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Precision Clock Synthesizer
for Desktop PCs
48-Pin SSOP Package Data
48
Gauge Plane
0.25
.291
.299
7.39 10.03
7.59 10.67
.395
.420
.02
.04
0.51
1.01
.010
.015 0.381
.025 0.635
x 45˚
1
.620
Nom.
0-8˚
.0080.20
.630
15.75
16.00
.110 2.79 Max
.008 0.20
.016 0.40
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.008
.0135
0.20
.025 BSC
0.635
0.34
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
Table of Dimensions
Body
E (Width) D (Length) A (Height) e (Pin-to-Pin pitch)
48 pins
Min.
0.291
0.299
0.620
0.630
0.095
0.110
0.025
-
(300 mil)
Max.
Ordering Information
P/N
Description
48-pin SSOP Package
PI6C100V
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8142A 10/13/98
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