PI6C102 [PERICOM]
Precision Clock Synthesizer for Mobile PCs; 精密时钟合成器适用于移动PC
| 型号： | PI6C102 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Precision Clock Synthesizer for Mobile PCs |
| 文件： | 总11页 (文件大小：585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C102
Precision Clock Synthesizer
for Mobile PCs
Features
Description
Two copies of CPU clock with V of 2.5V ±5%
The PI6C102 is a high-speed low-noise clock generator designed
to work with the Pericom's PI6C18x clock buffer to meet all clock
needs for Mobile Intel Architecture platforms. CPU and chipset
clock frequencies of 66.6 MHz and 100 MHz are supported.
DD
100MHzor66.6MHzoperation
Six copies of PCI clock, (synchronous with CPU clock) 3.3V
OnecopyofRef.Clock@14.31818MHz(3.3V
)
TTL
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powersaportionoftheI/Oandthecore. The2.5Vis usedto power
theremainingoutputs.2.5VsignalingfollowsJEDECstandard8-X.
Power sequencing of the 3.3V and 2.5V supplies is not required.
Low cost 14.31818 MHz crystal oscillator input
Powermanagementcontrol
Isolated core V , V pins for noise reduction
DD SS
28-pinSSOPpackage(H)
AnasynchronousPWRDWN#signalmaybeusedtoorderlypower
down (or up) the system.
BlockDiagram
PinConfiguration
28-Pin
H
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PI6C102
Precision Clock Synthesizer for Mobile PCs
PinDescription
Pin
Signal Name
Type
Qty.
1
Description
1
XTAL_IN
I
14.318 MHz crystal input
14.318 MHz crystal output
Ground for PCI clock outputs
2
XTAL_OUT
O
1
3,12
4
V [0:1]
SSPCI
ground
2
PCICLK_F
O
1
Free running PCI clock output
PCI clock outputs, TTL comatible 3.3V
Power for PCI clock outputs
5,7,8,10,11 PCICLK[1:5]
O
5
6,9
21
V
DDPCI
[0:1]
power
2
V
power
1
Isolated power for core
DDCORE 1
20
V
ground
1
Isolated ground for core
SSCORE 1
15
SEL100/66#
SEL
I
1
Select pin for enabling 100 MHz or 66 MHz H = 100 MHz. L = 66 MHz
Test or Active Mode Select
16
I
1
17
PWRDWN#
CPUSTOP#
PCISTOP#
I
I
1
Powers down device when held LOW
Stops CPU clocks LOW if held LOW
Stops PCI clocks LOW if held LOW
Ground for CPU outputs
18
1
19
I
1
22
V
SSCPU
ground
O
1
23,24
25
CPUCLK[0:1]
2
CPU and Host clock outputs 2.5V
Power for CPU outputs
V
DDCPU
power
O
1
26
REF
1
14.318 MHz clock output
27
V
power
ground
1
Power for REF outputs
DDREF
28
V
1
Ground for REF outputs
SSREF
SelectFunctions
SEL100/66#
SEL
Function
Hi-Z
Function
Description
Outputs
0
0
1
1
0
1
0
1
CPU [0:1] PCI[0:5], PCIF
REF
Hi-Z
66 MHz active
Test Mode
100 MHz active
Hi-Z
Hi-Z
Hi-Z
Test Mode
TCLK/2
TCLK/6
TCLK
Notes:
TCLK is a test clock over driven on he XTAL_IN inpu during test mode.
ClockEnableConfiguration
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK [0:1] PCICLK[1:5] PCICLK_F Other Clocks Crystal VCO's
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
low
low
low
low
low
stopped
running
running
running
running
off
off
33 MHz
33 MHz
33 MHz
33 MHz
running
running
running
running
running
running
running
running
low
33 MHz
low
100/66 MHz
100/66 MHz
33 MHz
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PI6C102
Precision Clock Synthesizer for Mobile PCs
PowerManagementTiming
Latency
Signal
Signal State
No. of rising edges of free running PCICLK
CPU_STOP#
0 (disabled)
1 (enabled)
1
1
PCI_STOP#
PWR_DWN#
0 (disabled)
1
1 (enabled)
1
1 (normal operation)
0 (power down)
3ms
2 max.
Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs
between when the clock disable goes low/high to when the first valid clock comes out of
the device.
2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid
clocks are driven from the device.
CPU_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F.
4. ON/OFF latency shown in the diagram is 2 CPU clocks.
5. All other clocks continue to run undisturbed.
6. PWR_DWN# and PCI_STOP# are shown in a HIGH state.
7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
CPU_STOP# is an input signal used to turn off the CPU clocks for
low power operation. CPU_STOP# is asserted asynchronously by
the external clock control logic with the rising edge of free running
PCIclockandisinternallysynchronizedtotheexternalPCICLK_F
output. All other clocks continue to run while the CPU clocks are
disabled. The CPU clocks are always stopped in a LOW state and
started guaranteeing that the high pulse width is a full pulse. CPU
clock on latency is 2 or 3 CPU clocks and CPU clock off latency
is 2 or 3 CPU clocks.
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PI6C102
Precision Clock Synthesizer for Mobile PCs
PCI_STOP# is an input signal used to turn off PCI clocks for low startedwithaguaranteedfullhighpulsewidth. ThereisONLYone
power operation. PCI clocks are stopped in the LOW state and rising edge of external PCICLK after the clock control logic.
PCI_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output.
3 Internal means inside the chip.
4. All other clocks continue to run undisturbed.
5. PWR_DWN# and CPU_STOP# are shown in a high state.
6. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
The PWR_DWN# is used to place the device in a very low power
state. PWR_DWN# is an asynchronous active low input. Internal
clocks are stopped after the device is put in power-down mode.
Thepower-onlatencyislessthan3ms.PCI_STOP#andCPU_STOP#
aredontcaresduringthepower-downoperations.TheREFclock
is stopped in the LOW state as soon as possible.
PWR_DWN# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown wth respect to 66 MHz. Similar operation as CPU = 100 MHz.
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................... 65°Cto+150°C
Ambient Temperature with Power Applied ................................ 0°Cto+70°C
3.3V Supply Voltage to Ground Potential................................... 0.5Vto+4.6V
2.5V Supply Voltage to Ground Potential................................... 0.5Vto+3.6V
DC Input Voltage ....................................................................... 0.5Vto+4.6V
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximumratingconditionsforextendedperiodsmayaffectreliability.
DCElectricalCharacteristics(V
=+3.3V±5%,V =+2.5V±5%,T =0°Cto+70°C)
DDQ2 A
DDQ3
Max. 2.5V Supply Consumption
Max. discrete cap loads,
Max. 3.3V Supply Consumption
Max. discrete cap loads,
PI6C102
Condition
VDDQ2 = 2.625V
VDDQ3 = 3.465V
All static inputs = VDDQ3 or VSS
All static inputs = VDDQ3 or VSS
Powerdown Mode
(PWRDWN# =0)
100µA
500µA
Active 66 MHz
SEL 100/66# = 0
72mA
170mA
170mA
Active 100 MHz
SEL 100/66# = 1
100mA
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PI6C102
Precision Clock Synthesizer for Mobile PCs
DC Operating Specifications
Symbol
Parameters
Conditions
Min.
Max.
Units
V
DD
= 3.3V ± 5%
V
Input high voltage
Input low voltage
V
DD
2.0
V
+0.3
IH3
DD
V
V
V
-0.3
0.8
IL3
SS
I
Input leakage current
0 < V < V
DD
-5
+5
0.4
0.4
µA
IL
IN
V
V
= 2.5V ± 5%
DD
V
OH2
Output high voltage
Output low voltage
I
OH
= -1mA
2.0
2.4
V
V
V
OL2
I
OL
= 1mA
= 3.3V ± 5%
DD
V
OH3
Output high voltage
Output low voltage
I
= -1mA
= 1mA
OH
V
OL3
I
OL
V
DD
= 3.3V ± 5%
V
PCI Bus output high voltage
PCI Bus output low voltage
I
= -1mA
= 1mA
OL
2.4
POH
OH
V
V
I
0.55
POL
C
Input pin capacitance
Xtal pins capacitance
Output pin capacitance
Pin Inductance
5
22.5
6
IN
pF
C
13.5
18.0
0
XTAL
C
OUT
L
PIN
7
nH
°C
T
Ambient Temperature
No airflow
70
A
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Buffer Specifications
Buffer Name
CPU
V
Range(V)
Impedance (Ω)
13.5 - 45
20 - 60
Buffer Type
Type 1
DD
2.375 -2.625
3.135 - 3.465
3.135 - 3.465
REF
Type 3
PCI
12 - 55
Type 5
Type 1: CPU Clock Buffers (2.5V)
Symbol
Parameters
Pull-up current
Conditions
= 1.0V
OUT
Min.
Typ.
Max.
Units
I
V
-27
OHMIN
I
Pull-up current
V
= 2.375V
= 1.2V
OUT
-27
OHMAX
OUT
mA
I
Pull-down current
Pull-down current
V
27
OLMIN
I
V
OUT
= 0.3V
30
4
OLMAX
t
2.5V Type 1 output rise edge rate 2.5V ± 5% @ 0.4V-2.0V
2.5V Type 1 output fall edge rate 2.5V ± 5% @ 2.0V-0.4V
1
1
RH
V/ns
t
FH
4
Type 3: REF (3.3V)
Symbol
Parameters
Pull-up current
Conditions
= 1.0V
OUT
Min.
Typ.
Max.
Units
I
V
-29
OHMIN
I
Pull-up current
V
= 2.375V
= 1.2V
OUT
-23
OHMAX
OUT
mA
I
Pull-down current
Pull-down current
V
29
OLMIN
I
V
OUT
= 0.3V
27
2
OLMAX
t
3.3V Type 3 output rise edge rate 3.3V ± 5% @ 0.4V-2.4V
3.3V Type 3 output fall edge rate 3.3V ± 5% @ 2.4V-0.4V
0.5
0.5
RH
V/ns
t
FH
2
Type 5: PCI Clock Buffers (3.3V)
Symbol
Parameters
Pull-up current
Conditions
= 1.0V
OUT
Min.
Typ.
Max.
Units
I
V
-33
OHMIN
I
Pull-up current
V
= 3.135V
= 1.95V
= 0.4V
-33
OHMAX
OUT
mA
I
Pull-down current
Pull-down current
V
OUT
30
OLMIN
I
V
OUT
38
4
OLMAX
t
3.3V Type 5 output rise edge rate 3.3V ± 5% @ 0.4V-2.4V
3.3V Type 5 output fall edge rate 3.3V ± 5% @ 2.4V-0.4V
1
1
RH
V/ns
t
FH
4
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PI6C102
Precision Clock Synthesizer for Mobile PCs
AC Timing
66 MHz
100 MHz
Figure 1. Host Clock
to PCI CLK Offset
Parameters
Host CLK period
Units
Min.
15.0
5.2
Max.
Min.
Max.
tHKP (2.5V)
tHKH (2.5V)
tHKL (2.5V)
tHRISE (2.5V)
tHFALL (2.5V)
tJITTER (2.5V)
Duty Cycle (2.5V)
tHSKW (2.5V)
tPZL, tPZH
15.5
10.0
3.0
2.8
0.4
0.4
10.5
Host CLK high time
ns
Host CLK low time
5.0
Host CLK rise time
0.4
1.6
1.6
250
55
1.6
1.6
250
55
Host CLK fall time
0.4
Host CLK Jitter
ps
%
ps
Measured at 1.25V
45
45
Host Bus CLK Skew
Output enable delay
175
8.0
8.0
3
175
8.0
8.0
3
1.0
1.0
1.0
1.0
ns
tPLZ, tPHZ
Output disable delay
Host CLK Stabilization from power-up
PCI CLK period
tHSTB
ms
ns
tPKP
30.0
30.0
tPKPS
PCI CLK period stability
PCI CLK high time
500
500
ps
12.0
12.0
12.0
12.0
tPKH
ns
tPKL
PCI CLK low time
tPSKW
tHPOFFSET
tPSTB
PCI Bus CLK Skew
Host to PCI Clock Offset
PCI CLK Stabilization from power-up
500
4.0
3
500
4.0
3
ps
ns
1.5
1.5
ms
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Figure1.HostClockandPCICLKTiming
Figure2.ClockOutputWaveforms
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PI6C102
Precision Clock Synthesizer for Mobile PCs
PCB Layout Suggestion
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C2-C7 should be placed as close as possible to
Recommended capacitor values:
C2-C7 ............... 0.1µF,ceramic
C1,C8 ............. 22µF
their respective V
.
DD
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PI6C102
Precision Clock Synthesizer for Mobile PCs
Minimum and Maximum Expected Capacitive Loads
Clock
Min. Load Max. Load
Units
Notes
CPU Clocks (HCLK)
PCI Clocks (PCLK)
10
30
10
20
30
20
1 device load, possible 2 loads
pF
Meets PCI 2.1 requirements
1 device load
REF
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.
2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.
3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an
additional 500Ω resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of vias of the clock traces.
3. Routeclocktracesoveracontinuousgroundplaneoroveracontinuouspowerplane. Avoidroutingclock
traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
Ω
Ω
Ω
Ω
Ordering Information
P/N
Description
28-pin SSOP Package
PI6C102H
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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