PI6C182BHEX [PERICOM]
Precision 1-10 Clock Buffer; 1-10精密时钟缓冲器
| 型号： | PI6C182BHEX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Precision 1-10 Clock Buffer |
| 文件： | 总7页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C182B
Precision 1-10 Clock Buffer
Features
Description
ThePI6C182Bisahigh-speedlow-noise1-10non-invertingbuffer
designedforSDRAMclockbufferapplicationsandsupportshigher
frequencies up to 140 MHz.
• Low noise non-inverting 1-10 buffer
• Supports frequency up to 140 MHz
• Supports up to four SDRAM DIMMs
2
At power up all SDRAM output are enabled and active. The I C
Serial control may be used to individually activate/deactivate any
of the 10 output drivers.
• Low skew (<200ps) between any two output clocks
2
• I C Serial Configuration interface
The output enable (OE) pin may be pulled low to Hi-Z state on
all outputs.
• Multiple V , V pins for noise reduction
DD
SS
Note:
• 3.3V power supply voltage
2
Purchase of I C components from Pericom conveys a license to
use them in an I C system as defined by Philips.
• Separate Hi-Z state pin for testing
• Industrial Temperature Range (-40°C to +85°C)
2
• Packaging: (Pb-free & Green available)
—28-pin SSOP (H)
Diagram
Pin Configuration
SDRAM0
SDRAM1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
1
V
DD5
DD0
SDRAM0
SDRAM1
SDRAM7
SDRAM6
2
3
BUF_IN
V
V
4
V
V
SS0
SS5
SDRAM2
SDRAM3
5
DD4
DD1
SDRAM2
6
SDRAM5
SDRAM4
SDRAM3
7
V
8
V
SS1
SS4
BUF_IN
9
OE
SDRAM1
V
10
11
12
13
14
V
DD3
DD2
SDRAM8
SDRAM9
OE
V
V
SS2
SS3
V
V
SSIIC
SDATA
DDIIC
2
I C
SDATA
SCLOCK
I/O
SCLOCK
PS8465C
09/07/05
1
PI6C182B
Precision 1-10 Clock Buffer
Pin Description
Pin
2, 3, 6, 7
22, 23, 26, 27
11, 18
Symbol
SDRAM[0-3]
SDRAM[4-7]
SDRAM[8-9]
BUF_IN
Type
Qty
4
Description
O
O
O
I
SDRAM Byte 0 clock output
SDRAM Byte 1 clock output
SDRAM Byte 2 clock output
Input for 1-20 buffer
4
2
9
1
Hi-Z states all outputs when held LOW. Has a >100kΩ internal pull-up
resistor.
20
OE
I
1
2
14
15
SDATA
I/O
I/O
1
1
Data pin for I C curcuitry. Has a >100kΩ internal pull-up resistor.
2
SCLOCK
Clock pin I C circuitry. Has a >100kΩ internal pull-up resistor.
1, 5, 10, 19, 24,
28
VDD[0-5]
VSS[0-5]
Power
6
6
3.3V power supply for SDRAM buffer
Ground for SDRAM buffers
4, 8, 12, 17, 21,
25
Ground
2
13
16
VDDIIC
VSSIIC
Power
1
1
3.3V power supply for I C circuitry
2
Ground
Ground for I C circuitry
Serial Configuration Map
OE Functionality
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
OE
SDRAM[0-9]
Hi-Z
Notes
0
1
2
Bit
7
Pin
Description
NC (Initialize to 0)
1
BUF_IN
Notes:
6
NC (Initialize to 0)
1. Used for test purposes only
2. Buffers are non-inverting
5
NC (Initialize to 0)
4
NC (Initialize to 0)
3
7
6
3
2
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
2
I C Address Assignment
2
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
1
0
1
0
0
1
0
0
Note:
1. Inactive means outputs are held LOW and are disabled from
switching
PS8465C
09/07/05
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PI6C182B
Precision 1-10 Clock Buffer
2-Wire I2C Control
2
The I C interface permits individual enable/disable of each clock
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addresseddevice,LOW=writetoaddresseddevice).Ifthedevice’s
own address is detected, PI6C182B generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts
the following data bytes until another start or stop condition is
detected.
output and test mode enable.
The PI6C182B is a slave receiver device. It can not be read back.
Sub addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
Every byte put on the SDATA line must be 8-bits long (MSB
first), followed by an acknowledge bit generated by the receiving
device.
DuringnormaldatatransfersSDATAchangesonlywhenSCLOCK
is LOW. Exceptions: AHIGH to LOW transition on SDATAwhile
SCLOCK is HIGH indicates a “start” condition. ALOW to HIGH
transitiononSDATAwhileSCLOCKisHIGHisa“stop”condition
and indicates the end of a data transfer cycle.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Each data transfer is initiated with a start condition and ended with
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
Bit
7
Pin
27
26
23
22
Description
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
NC (Initialize to 0)
Bit
7
Pin
18
Description
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
(Reserved)
6
11
6
5
5
4
(Reserved)
4
3
(Reserved)
3
2
NC (Initialize to 0)
2
(Reserved)
1
(Reserved)
1
NC (Initialize to 0)
0
NC (Initialize to 0)
0
(Reserved)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Storage Temperature............................................................–65°C to +150°C
Ambient Temperature with Power Applied...........................–40°C to +85°C
3.3V Supply Voltage to Ground Potential ..............................–0.5V to +4.6V
DC Input Voltage....................................................................–0.5V to +4.6V
Supply Current (V = +3.465V, C
= Max.)
LOAD
DD
Symbol
Parameter
Test Condidtion
BUF_IN = 0 MHz
Min.
Typ.
Max.
2
Units
I
I
I
I
DD
DD
DD
DD
BUF_IN = 66.66 MHz
BUF_IN = 100.00 MHz
BUF_IN = 133.00 MHz
180
240
360
Supply Current
mA
PS8465C
09/07/05
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PI6C182B
Precision 1-10 Clock Buffer
DC Operating Specifications (V = +3.3V ±5%, T = - 40°C to + 85°C)
DD
A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Input Voltage
V
V
Input High voltage
V
2.0
V +0.3
DD
V
IH
IL
DD
Input Low voltage
V
-0.3
0.8
SS
I
Input leakage current
0 < V < V
-5
5
mA
IL
IN
DD
V
[0-9] = 3.3V ±5%
DD
V
V
Output High voltage
Output Low voltage
I
I
= -1mA
= 1mA
2.4
V
OH
OL
OH
OL
0.4
C
C
Output pin capacitance
Input pin capacitance
Pin Inductance
6
5
7
pF
OUT
IN
L
nH
°C
PIN
T
A
Ambient Temperature
No Airflow
0
70
SDRAM Clock Buffer Operating Specification
Symbol
Parameter
Test Conditions
= 2.0V
Min.
Typ.
Max.
Units
I
I
I
I
Pull-up current
V
V
V
V
-54
OHMIN
OUT
OUT
OUT
OUT
Pull-up current
= 3.135V
= 1.0V
-46
53
OHMAX
OLMIN
OLMAX
mA
Pull-down current
Pull-down current
54
= 0.4V
AC Timing
66 MHz
100 MHz
Min. Max.
133MHz
Min.
Symbol
Parameter
Units
Min.
Max.
4.0
4.0
5.0
5.0
8.0
8.0
55
Max.
4.0
4.0
5.0
5.0
8.0
8.0
55
t
t
t
t
t
t
SDRAM CLK rise time
1.5
1.5
1.0
1.0
1.0
1.0
45
1.5
1.5
1.0
1.0
1.0
1.0
45
4.0
4.0
5.0
5.0
8.0
8.0
55
1.5
1.5
1.0
1.0
1.0
1.0
45
SDRISE
SDFALL
PLH
V/ns
SDRAM CLK fall time
SDRAM Buffer LH prop delay
SDRAM Buffer HL prop delay
PHL
ns
(1)
, t
SDRAM Buffer Enable delay
SDRAM Buffer DIsable delay
Measured at 1.5V
PZL PZH
(1)
, t
PLZ PHZ
Duty Cycle
%
ps
t
SDRAM Output-to-Output skew
250
250
200
SDSKW
Note:
1. This Parameter specified at 5 MHz input frequency.
PS8465C
09/07/05
4
PI6C182B
Precision 1-10 Clock Buffer
Test
Point
Output
Buffer
Test Load
tSDKP
tSDKH
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
tSDKL
t
t
SDFALL
SDRISE
Input
Waveform
1.5V
1.5V
t
t
phl
plh
Output
Waveform
1.5V
1.5V
Figure 1. Clock Waveforms
Design Guidelines to Reduce EMI
Minimum and Maximum Expected
Capacitive Loads
1. Place series resistors and CI capacitors as close as possible to
the respective clock pins. Typical value for CI is 10pF. Series
resistor value can be increased to reduce EMI provided that
the rise and fall time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over
a continuous power plane. Avoid routing clock traces from
plane to plane (refer to rule #2).
Clock
Min.
Max.
Units
Notes
SDRAM DIMM
Specificaion
SDRAM
15
20
pF
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified
load.
2. Minimum rise/fall times are guaranteed at minimum specified
load.
4. Position clock signals away from signals that go to any cables
or any external connectors.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
PS8465C
09/07/05
5
PI6C182B
Precision 1-10 Clock Buffer
PCB Layout Suggestion
C1
C7
28
VDD
VDD
1
Ferrite Bead
VCC
2
27
26
25
24
23
3
C8
VSS
C2
VSS
VDD
4
C6
VDD
5
22uF
6
7
22
21
20
19
18
17
VSS
VSS
VDD
8
9
C3
C5
VDD
10
11
12
13
14
Via to GND Plane
Via to VDD Plane
VSS
C4
VSS
VSS
VDD
16
15
Void in Power Plane
Note:
1. This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout.
2. As a general rule, C1-C7 should be placed as close as possible to their respective VDD.
3. Recommended capacitor values:
C1-C7 = 0.1μF, ceramic
C8 = 22μF
PI6C182B
R
S
100/66 MHz
Clock from
Chipset
SDRAM
DIMM
Spec.
10
SDRAM
CL
Figure 2. Design Guidelines
PS8465C
09/07/05
6
PI6C182B
Precision 1-10 Clock Buffer
Packaging Mechanical: 28-Pin SSOP (H)
Ordering Information
Ordering Code
PI6C182BH
PI6C182BHE
Package Code
Package Type
H
H
28-pin SSOP
Pb-free & Green, 28-pin SSOP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PS8465C
09/07/05
7
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