PI6C20800SAE [PERICOM]
PCI Express 1:8 HCSL Clock Buffer; PCI Express的1:8 HCSL时钟缓冲器
| 型号： | PI6C20800SAE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PCI Express 1:8 HCSL Clock Buffer |
| 文件： | 总10页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
Features
Description
PI6C20800S is a PCI Express, high-speed, low-noise differential
clock buffer designed to be a companion to PI6C410BS PCI
Express clock generator for Intel server chipsets. The device
distributes the differential SRC clock from PI6C410BS to eight
differential pairs of clock outputs either with or without PLL.
The input SRC clock can be divided by 2 when SRC_DIV# is
LOW. The clock outputs are controlled by input selection of
SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When
input of either SRC_STOP# or PWRDWN# is LOW, the output
clocks are Tristated. When PWRDWN# is LOW, the SDA and
SCLK inputs must be Tristated.
• Phase jitter filter for PCIe application
• Eight Pairs of Differential Clocks
• Low skew < 50ps
• Low Cycle-to-cycle jitter < 50ps
• Output Enable for all outputs
• Outputs Tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fanout operation
• 3.3V Operation
• Packaging (Pb-Free & Green):
— 48-Pin SSOP (V)
— 48-Pin TSSOP (A)
Block Diagram
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SRC_DIV#
VDD
VDD_A
VSS_A
IREF
LOCK
OE_7
1
2
VSS
SRC
3
OE_INV
OE [0:7]
SRC_STOP#
PWRDWN#
Output
Control
4
SRC#
OE_0
OE_3
OUT0
OUT0#
VSS
5
OUT0
OUT0#
OE_4
6
OUT7
OUT7#
OE_INV
VDD
OUT6
OUT6#
OE_6
7
OUT1
OUT1#
SCLK
SDA
8
SMBus
Controller
OUT2
OUT2#
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PLL/BYPASS#
SRC_DIV#
OUT3
OUT3#
VDD
OUT1
OUT1#
OE_1
OE_2
OUT2
OUT2#
VSS
OUT4
OUT4#
SRC
SRC#
OE_5
OUT5
OUT5#
OUT5
OUT5#
VSS
OUT6
OUT6#
DIV
VDD
PLL_BW#
PLL
OUT7
OUT7#
VDD
OUT4
OUT4#
PLL_BW#
SRC_STOP#
PWRDWN#
VSS
OUT3
OUT3#
PLL/BYPASS#
SCLK
SDA
LOCK
PS8887B
10/19/07
07-0237
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PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
Pin Descriptions
Pin Name
Type
Input
Input
Input
Pin #
1
Descriptions
3.3V LVTTL input for selecting input frequency divide by 2,
active LOW.
SRC_DIV#
SRC & SRC#
OE [0:7]
4, 5
0.7V Differential SRC input from PI6C410 clock synthesizer
6, 7, 14, 15, 35, 36,
43, 44
3.3V LVTTL input for enabling outputs, active HIGH.
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
When 0 = same stage
OE_INV
Input
40
When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted.
8, 9, 12, 13, 16 17,
OUT[0:7] & OUT[0:7]# Output 20, 21, 29, 30, 33, 34, 0.7V Differential outputs
37, 38, 41, 42
PLL/BYPASS#
SCLK
Input
Input
I/O
22
23
24
46
27
28
26
3.3V LVTTL input for selecting fan-out of PLL operation.
SMBus compatible SCLOCK input
SDA
SMBus compatible SDATA
I
Input
Input
Input
Input
External resistor connection to set the differential output current
3.3V LVTTL input for SRC stop, active LOW
3.3V LVTTL input for selecting the PLL bandwidth
3.3V LVTTL input for Power Down operation, active LOW
REF
SRC_STOP#
PLL_BW#
PWRDWN#
3.3V LVTTL output, transition high when PLL lock is achieved
(Latched output)
LOCK
Output
45
V
V
V
V
Power
Ground
Ground
Power
2, 11, 19, 31, 39
3.3V Power Supply for Outputs
Ground for Outputs
DD
3, 10, 18, 25, 32
SS
47
48
Ground for PLL
SS_A
DD_A
3.3V Power Supply for PLL
Serial Data Interface (SMBus)
PI6C20800S is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
1
1
0
0/1
(1)
Data Protocol
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
8 bits
Data
1
1 bit
Byte
Count
= N
Start
bit
Slave
Addr
Register
offset
Data
Byte 0
Stop
bit
R/W Ack
Ack
Ack
Ack Byte N Ack
- 1
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
PS8887B
10/19/07
07-0237
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PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
Data Byte 0: Control Register
Bit
Descriptions
Type
Power Up Condition
Output(s) Affected
Pin
SRC_DIV#
0
0 = Divide by 2
1 = Normal
RW
1 = x1
OUT[0:7], OUT[0:7]#
OUT[0:7], OUT[0:7]#
OUT[0:7], OUT[0:7]#
NA
PLL/BYPASS#
0 = Fanout
1 = PLL
1
2
RW
RW
1 = PLL
1 = Low
NA
NA
PLL Bandwidth
0 = HIGH Bandwidth,
1 = LOW Bandwidth
3
4
5
RESERVED
RESERVED
RESERVED
SRC_STOP#
6
7
0 = Driven when stopped
1 = Tristate
RW
RW
0 = Driven when stopped
0 = Driven when stopped
OUT[0:7], OUT[0:7]#
OUT[0:7], OUT[0:7]#
PWRDWN#
0 = Driven when stopped
1 = Tristate
NA
Data Byte 1: Control Register
Bit
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
Output(s) Affected
OUT0, OUT0#
OUT1, OUT1#
OUT2, OUT2#
OUT3, OUT3#
OUT4, OUT4#
OUT5, OUT5#
OUT6, OUT6#
OUT7, OUT7#
Pin
NA
NA
NA
NA
NA
NA
NA
NA
0
1
2
OUTPUTS enable
1 = Enabled
3
4
0 = Disabled
5
6
7
PS8887B
10/19/07
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PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
Data Byte 2: Control Register
Bit
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
Output(s) Affected
Pin
NA
NA
NA
NA
NA
NA
NA
NA
0
OUT0, OUT0#
OUT1, OUT1#
OUT2, OUT2#
OUT3, OUT3#
OUT4, OUT4#
OUT5, OUT5#
OUT6, OUT6#
OUT7, OUT7#
1
2
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
3
4
1 = Stopped with SRC_Stop#
5
6
7
Data Byte 3: Control Register
Bit
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
Output(s) Affected
Pin
0
1
2
3
RESERVED
4
5
6
7
Data Byte 4: Pericom ID Register
Bit
Descriptions
Type
R
Power Up Condition
Output(s) Affected
Pin
NA
NA
NA
NA
NA
NA
NA
NA
0
0
0
0
0
0
1
0
0
NA
NA
NA
NA
NA
NA
NA
NA
1
R
2
R
3
R
Pericom ID
4
R
5
R
6
R
7
R
PS8887B
10/19/07
07-0237
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PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
Functionality
PWRDWN#
OUT
OUT#
Normal
LOW
SRC_Stop#
OUT
OUT#
Normal
LOW
1
0
Normal
1
0
Normal
I
× 2 or Float
I
× 6 or Float
REF
REF
Power Down (PWRDWN# assertion)
PWRDWN#
OUT
OUT#
Figure 1. Power down sequence
Power Down (PWRDWN# De-assertion)
Tstable
<1ms
PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
Figure 2. Power down de-assert sequence
PS8887B
10/19/07
07-0237
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PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
Current-mode output buffer characteristics of OUT[0:7], OUT[0:7]#
VDD
(3.3V ± 5%)
Slope ~ 1/Rs
RO
IOUT
ROS
Iout
VOUT = 0.85V max
0V
0.85V
Figure 9. Simplified diagram of current-mode output buffer
Differential Clock Buffer characteristics
Symbol
Minimum
3000Ω
Maximum
N/A
R
O
R
unspecified
N/A
unspecified
850mV
OS
V
OUT
Current Accuracy
Symbol
Conditions
V = 3.30 ±5%
DD
Configuration
Load
Min.
Max.
R
= 475Ω 1%
Nominal test load for given
configuration
-12%
+12%
REF
I
OUT
I
= 2.32mA
I
I
REF
NOMINAL
NOMINAL
Note:
1. INOMINAL refers to the expected current based on the configuration of the device.
Differential Clock Output Current
Board Target Trace/Term Z
Reference R, Iref = V /(3xRr)
Output Current
= 6 x I
V
@ Z
DD
OH
100Ω
R
REF
= 475Ω 1%,
I
0.7V @ 50
OH
REF
(100Ω differential ≈ 15% coupling ratio)
I
= 2.32mA
REF
PS8887B
10/19/07
07-0237
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PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
(1)
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol Parameters
Min.
-0.5
-0.5
Max.
4.6
Units
V
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Storage Temperature
ESD Protection
DD_A
V
4.6
DD
V
V
IH
4.6
V
IL
-0.5
-65
Ts
150
°C
V
V
ESD
2000
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Electrical Characteristics (V = 3.3±5%, V
= 3.3±5%)
DD
DD_A
Symbol
Parameters
Condition
Min.
3.135
3.135
2.0
Max.
Units
V
DD_A
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
3.3V Input HIGH Voltage
3.3V Input LOW Voltage
Input Leakage Current
3.3V Output HIGH Voltage
3.3V Output LOW Voltage
3.465
3.465
V
DD
V
V
IH
V
V
+ 0.3
DD
DD
V
IL
V
– 0.3
SS
0.8
I
IK
0 < V < V
DD
-5
+5
μA
IN
V
OH
I
OH
= -1mA
2.4
12.2
1.5
V
V
OL
I
OL
= 1mA
0.4
I
I
= 6 x I
,
OH
REF
I
Output HIGH Current
mA
OH
= 2.32mA
REF
15.6
5
C
Logic Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
IN
pF
C
6
OUT
L
7
nH
PIN
DD
I
Power Supply Current
Power Down Current
Power Down Current
Ambient Temperature
V
DD
= 3.465V, F
= 100MHz
CPU
250
80
12
70
I
Driven outputs
Tristate outputs
mA
°C
SS
SS
I
T
A
0
PS8887B
10/19/07
07-0237
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PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
(1,2,3)
AC Switching Characteristics
(V = 3.3±5%, V
= 3.3±5%)
DD
DD_A
Symbol
Parameters
Min
Max.
Units Notes
SRC/SRC# Input Frequency PLL Mode
SRC/SRC# Input Frequency Bypass Mode
100
400
700
MHz
MHz
6
6
2
F
in
100
175
T
/ T
Rise and Fall Time (measured between 0.175V to 0.525V)
rise
fall
ps
ΔT
/
rise
ΔT
Rise and Fall Time Variation
125
2
fall
PLL Mode
Bypass Mode
-250
2.5
250
6.5
ps
ns
ps
T
Input to Output Propagation Delay
pd
T
skew
Output-to-Output Skew
Voltage HIGH (Measured at 100MHz @ 3.3V)
Max. Voltage
50
3
2
V
660
850
1150
HIGH
V
OVS
UDS
LOW
V
Min. Voltage
-300
-150
250
mV
V
Voltage LOW
+150
550
140
55
2
2
2
3
V
cross
Absolute crossing poing voltages
Total Variation of V
over all edges
ΔV
cross
cross
T
DC
Duty Cycle (Measured at 100 MHz)
45
%
ps
ps
Jitter, Cycle-to-cycle (PLL Mode, Measurement for differential
waveform)
T
50
1
4
5
jcyc-cyc
Jitter, Cycle-to-cycle (BYPASS mode as additive jitter)
Additive RMS phase jitter for PCIe GenII
J
add
<0
Notes:
1. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF.
2. Measurement taken from Single Ended waveform.
3. Measurement taken from Differential waveform.
4. Measured using M1 timing analyzer from Amherst.
5. Additive jitter is calculated from input and output RMS phase jitter by using PCIe Gen II filter. (Jadd = √ (output jitter)2 – (input jitter)2 )
6. –0.5% downnspread input
Configuration Test Load Board Termination
Rs
33Ω
5%
OUT
TLA
Rs
PI6C20800
OUT#
33Ω
5%
TLB
2pF
5%
2pF
5%
Rp
49.9Ω
1%
Rp
49.9Ω
1%
475Ω
1%
PS8887B
10/19/07
07-0237
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PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
Packaging Mechanical: 48-Pin SSOP (V)
48
.395
.420
10.03
10.67
.291
.299
7.39
7.59
Gauge Plane
.010
0.25
.02
.04
0.51
1.01
1
.620
.630
15.75
16.00
0.381
0.635
.015
.025
x 45˚
.008
0.20
Nom.
.110 2.79 Max
.008 0.20
.0135 0.34
.025 BSC
0.635
.008 0.20
.016 0.40
0-8˚
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
Packaging Mechanical: 48-Pin TSSOP (A)
48
.236
.244
6.0
6.2
1
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
0.09
0.20
.004
.008
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.007
.010
.0197
BSC
.319
BSC
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.50
0.17
0.27
8.1
PS8887B
10/19/07
07-0237
9
PI6C20800S
PCI Express 1:8
HCSL Clock Buffer
(1,2)
Ordering Information
Ordering Code
PI6C20800SVE
PI6C20800SAE
Notes:
Package Code
Package Description
VE
AE
48-pin, 300-mil wide, SSOP, Pb-Free and Green
48-pin, 240-mil wide, TSSOP, Pb-Free and Green
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PS8887B
10/19/07
07-0237
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