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PI6C20800SVEX [DIODES]

PLL Based Clock Driver, 6C Series, 16 True Output(s), 0 Inverted Output(s), PDSO48, 0.300 INCH, GREEN, MO-118AA, SSOP-48;
PI6C20800SVEX
型号： PI6C20800SVEX
厂家： DIODES INCORPORATED    DIODES INCORPORATED
描述：

PLL Based Clock Driver, 6C Series, 16 True Output(s), 0 Inverted Output(s), PDSO48, 0.300 INCH, GREEN, MO-118AA, SSOP-48

驱动 光电二极管 逻辑集成电路
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PI6C20800S  
PCI Express® 1:8  
HCSL Clock Buffer  
Features  
Description  
PI6C20800SꢀisꢀaꢀPCIꢀExpress®,ꢀhigh-speed,ꢀlow-noiseꢀdifferentialꢀ  
clockꢀ bufferꢀ designedꢀ toꢀ beꢀ aꢀ companionꢀ toꢀ PI6C410BSꢀ PCIꢀ  
Expressꢀ clockꢀ generatorꢀ forꢀ Intelꢀ serverꢀ chipsets.ꢀ ꢀ Theꢀ deviceꢀ  
distributesꢀtheꢀdifferentialꢀSRCꢀclockꢀfromꢀPI6C410BSꢀtoꢀeightꢀ  
differentialꢀ pairsꢀ ofꢀ clockꢀ outputsꢀ eitherꢀ withꢀ orꢀ withoutꢀ PLL.ꢀ  
TheꢀinputꢀSRCꢀclockꢀcanꢀbeꢀdividedꢀbyꢀ2ꢀwhenꢀSRC_DIV#ꢀisꢀ  
LOW.ꢀ ꢀ Theꢀ clockꢀ outputsꢀ areꢀ controlledꢀ byꢀ inputꢀ selectionꢀ ofꢀ  
SRC_STOP#,ꢀPWRDWN#ꢀandꢀSMBus,ꢀSCLKꢀandꢀSDA.ꢀWhenꢀ  
inputꢀofꢀeitherꢀSRC_STOP#ꢀorꢀPWRDWN#ꢀisꢀLOW,ꢀtheꢀoutputꢀ  
clocksꢀareꢀTristated.ꢀWhenꢀPWRDWN#ꢀisꢀLOW,ꢀtheꢀSDAꢀandꢀ  
SCLKꢀinputsꢀmustꢀbeꢀTristated.  
•ꢀ PhaseꢀjitterꢀfilterꢀforꢀPCIe®ꢀapplication  
•ꢀ EightꢀPairsꢀofꢀDifferentialꢀClocks  
•ꢀ Lowꢀskewꢀ<ꢀ50psꢀ(PI6C20800S),ꢀ<60psꢀ(PI6C20800SI)  
•ꢀ LowꢀCycle-to-cycleꢀjitterꢀ<ꢀ70ps  
•ꢀ OutputꢀEnableꢀforꢀallꢀoutputs  
•ꢀ OutputsꢀTristateꢀcontrolꢀviaꢀSMBus  
•ꢀ PowerꢀManagementꢀControl  
•ꢀ ProgrammableꢀPLLꢀBandwidth  
•ꢀ PLLꢀorꢀFanoutꢀoperation  
•ꢀ 3.3VꢀOperation  
•ꢀ IndustrialꢀTemperatureꢀOptionꢀ-ꢀPI6C20800SI  
•ꢀ Packagingꢀ(Pb-Freeꢀ&ꢀGreen):ꢀ  
—ꢀ48-PinꢀSSOPꢀ(V)ꢀ  
ꢀ —ꢀ48-PinꢀTSSOPꢀ(A)  
Block Diagram  
Pin Configuration  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
SRC_DIV#  
VDD  
VDD_A  
VSS_A  
IREF  
LOCK  
OE_7  
1
2
VSS  
SRC  
3
OE_INV  
OE [0:7]  
SRC_STOP#  
PWRDWN#  
Output  
Control  
4
SRC#  
OE_0  
OE_3  
OUT0  
OUT0#  
VSS  
5
OUT0  
OUT0#  
OE_4  
6
OUT7  
OUT7#  
OE_INV  
VDD  
OUT6  
OUT6#  
OE_6  
7
OUT1  
OUT1#  
SCLK  
SDA  
8
SMBus  
Controller  
OUT2  
9
OUT2#  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
PLL/BYPASS#  
SRC_DIV#  
OUT3  
VDD  
OUT3#  
OUT1  
OUT1#  
OE_1  
OE_2  
OUT2  
OUT2#  
VSS  
OUT4  
SRC  
OUT4#  
OE_5  
SRC#  
OUT5  
OUT5  
OUT5#  
VSS  
OUT5#  
OUT6  
OUT6#  
DIV  
VDD  
PLL_BW#  
PLL  
OUT7  
VDD  
OUT4  
OUT4#  
PLL_BW#  
SRC_STOP#  
PWRDWN#  
VSS  
OUT7#  
OUT3  
OUT3#  
PLL/BYPASS#  
SCLK  
SDA  
LOCK  
14-0190  
1
www.pericom.com  
03/27/13  
PI6C20800S  
PCI Express® 1:8 HCSL Clock Buffer  
Pin Descriptions ꢀ  
ꢀPin Name  
Type  
Input  
Input  
Input  
Pin #  
1
Descriptions  
3.3VꢀLVTTLꢀinputꢀforꢀselectingꢀinputꢀfrequencyꢀdivideꢀbyꢀ2,ꢀ  
activeꢀLOW.  
SRC_DIV#  
SRCꢀ&ꢀSRC#  
OEꢀ[0:7]  
4,ꢀ5  
0.7VꢀDifferentialꢀSRCꢀinputꢀfromꢀPI6C410ꢀclockꢀsynthesizer  
6,ꢀ7,ꢀ14,ꢀ15,ꢀ35,ꢀ36,ꢀ  
43,ꢀ44  
3.3VꢀLVTTLꢀinputꢀforꢀenablingꢀoutputs,ꢀactiveꢀHIGH.  
3.3VꢀLVTTLꢀinputꢀforꢀinvertingꢀtheꢀOE,ꢀSRC_STOP#ꢀandꢀ  
PWRDWN#ꢀpins.ꢀꢀ  
Whenꢀ0ꢀ=ꢀsameꢀstage  
OE_INV  
Input  
40  
Whenꢀ1ꢀ=ꢀOE[0:7],ꢀSRC_STOP#,ꢀPWRDWN#ꢀinverted.  
8,ꢀ9,ꢀ12,ꢀ13,ꢀ16ꢀ17,ꢀ  
OUT[0:7]ꢀ&ꢀOUT[0:7]# Output 20,ꢀ21,ꢀ29,ꢀ30,ꢀ33,ꢀ34,ꢀ 0.7VꢀDifferentialꢀoutputs  
37,ꢀ38,ꢀ41,ꢀ42  
PLL/BYPASS#  
SCLK  
Input  
Input  
I/O  
22  
23  
24  
46  
27  
28  
26  
3.3VꢀLVTTLꢀinputꢀforꢀselectingꢀfan-outꢀofꢀPLLꢀoperation.  
SMBusꢀcompatibleꢀSCLOCKꢀinput  
SDA  
SMBusꢀcompatibleꢀSDATA  
I
Input  
Input  
Input  
Input  
Externalꢀresistorꢀconnectionꢀtoꢀsetꢀtheꢀdifferentialꢀoutputꢀcurrent  
3.3VꢀLVTTLꢀinputꢀforꢀSRCꢀstop,ꢀactiveꢀLOW  
3.3VꢀLVTTLꢀinputꢀforꢀselectingꢀtheꢀPLLꢀbandwidth  
3.3VꢀLVTTLꢀinputꢀforꢀPowerꢀDownꢀoperation,ꢀactiveꢀLOW  
REF  
SRC_STOP#  
PLL_BW#  
PWRDWN#ꢀ  
3.3VꢀLVTTLꢀoutput,ꢀtransitionꢀhighꢀwhenꢀPLLꢀlockꢀisꢀachievedꢀ  
(Latchedꢀoutput)  
LOCK  
Output  
45  
V
V
V
V
Power  
Ground  
Ground  
Power  
2,ꢀ11,ꢀ19,ꢀ31,ꢀ39  
3.3VꢀPowerꢀSupplyꢀforꢀOutputs  
GroundꢀforꢀOutputs  
DDꢀ  
3,ꢀ10,ꢀ18,ꢀ25,ꢀ32  
SS  
47  
48  
GroundꢀforꢀPLL  
SS_A  
DD_A  
3.3VꢀPowerꢀSupplyꢀforꢀPLL  
Serial Data Interface (SMBus)  
ThisꢀpartꢀisꢀaꢀslaveꢀonlyꢀSMBusꢀdeviceꢀthatꢀsupportsꢀindexedꢀblockꢀreadꢀandꢀindexedꢀblockꢀwriteꢀprotocolꢀusingꢀaꢀsingleꢀ7-bitꢀ  
addressꢀandꢀread/writeꢀbitꢀasꢀshownꢀbelow.  
Address assignment  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
W/R  
1
1
0
1
1
1
0
0/1  
(1)  
Data Write Protocol  
1ꢀbit  
7ꢀbits  
1
1
8ꢀbits  
1
8ꢀbits  
1
8ꢀbits  
1
8ꢀbits  
Dataꢀ  
1
1ꢀbit  
Byteꢀ  
Countꢀ  
ꢀ=ꢀN  
Dataꢀ  
Byteꢀ  
Offset  
Startꢀ Slaveꢀ  
bit  
Registerꢀ  
offset  
W
Ack  
Ack  
Ack  
Ack ByteꢀNꢀ Ack Stopꢀbit  
-ꢀ1  
Addr  
Note:  
1.ꢀ Registerꢀoffsetꢀforꢀindicatingꢀtheꢀstartingꢀregisterꢀforꢀindexedꢀblockꢀwriteꢀandꢀindexedꢀblockꢀread.ꢀByteꢀCountꢀinꢀwriteꢀmodeꢀcannotꢀbeꢀ0.  
14-0190  
2
www.pericom.com  
03/27/13  
PI6C20800S  
PCI Express® 1:8 HCSL Clock Buffer  
(2)  
Data Read Protocol  
1ꢀbit 7ꢀbits  
1
1
8ꢀbits  
1
1
7ꢀbits  
1
1
8ꢀbits  
1
8ꢀbits  
Dataꢀ  
Byteꢀ Ack  
Offset  
1
8ꢀbits  
1
1ꢀbit  
Byteꢀ  
Countꢀ  
ꢀ=ꢀN  
Dataꢀ  
Byteꢀ  
Nꢀ-ꢀ1  
Startꢀ Slaveꢀ  
Registerꢀ  
offset  
Repeatꢀ  
Start  
Slaveꢀ  
Addr  
Notꢀ  
Ack  
Stopꢀ  
bit  
W
Ack  
Ack  
R
Ack  
Ack  
bit  
Addr  
Note:  
2.ꢀ Registerꢀoffsetꢀforꢀindicatingꢀtheꢀstartingꢀregisterꢀforꢀindexedꢀblockꢀwriteꢀandꢀindexedꢀblockꢀread.  
Data Byte 0: Control Registerꢀ  
Bit  
Descriptions  
Type  
Power Up Condition  
Output(s) Affected  
Pin  
SRC_DIV#  
0
0ꢀ=ꢀDivideꢀbyꢀ2  
1ꢀ=ꢀNormal  
RW  
1ꢀ=ꢀx1  
OUT[0:7],ꢀOUT[0:7]#  
NA  
NA  
NA  
PLL/BYPASS#  
0ꢀ=ꢀFanout  
1ꢀ=ꢀPLL  
1
RW  
RW  
1ꢀ=ꢀPLL  
1ꢀ=ꢀLow  
OUT[0:7],ꢀOUT[0:7]#  
OUT[0:7],ꢀOUT[0:7]#  
PLLꢀBandwidth  
0ꢀ=ꢀHIGHꢀBandwidth,  
1ꢀ=ꢀLOWꢀBandwidth  
2
3
4
5
RESERVED  
RESERVED  
RESERVED  
SRC_STOP#  
6
7
0ꢀ=ꢀDrivenꢀwhenꢀstopped  
1ꢀ=ꢀTristate  
RW  
RW  
0ꢀ=ꢀDrivenꢀwhenꢀstopped  
0ꢀ=ꢀDrivenꢀwhenꢀstopped  
OUT[0:7],ꢀOUT[0:7]#  
OUT[0:7],ꢀOUT[0:7]#  
PWRDWN#  
0ꢀ=ꢀDrivenꢀwhenꢀstopped  
1ꢀ=ꢀTristate  
NA  
Data Byte 1: Control Registerꢀ  
Bit  
Descriptions  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Power Up Condition  
1ꢀ=ꢀEnabled  
1ꢀ=ꢀEnabled  
1ꢀ=ꢀEnabled  
1ꢀ=ꢀEnabled  
1ꢀ=ꢀEnabled  
1ꢀ=ꢀEnabled  
1ꢀ=ꢀEnabled  
1ꢀ=ꢀEnabled  
Output(s) Affected  
OUT0,ꢀOUT0#  
OUT1,ꢀOUT1#  
OUT2,ꢀOUT2#  
OUT3,ꢀOUT3#  
OUT4,ꢀOUT4#  
OUT5,ꢀOUT5#  
OUT6,ꢀOUT6#  
OUT7,ꢀOUT7#  
Pin  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
0
1
2
OUTPUTSꢀenable  
1ꢀ=ꢀEnabledꢀꢀ  
3
4
0ꢀ=ꢀDisabled  
5
6
7
14-0190  
3
www.pericom.com  
03/27/13  
PI6C20800S  
PCI Express® 1:8 HCSL Clock Buffer  
Data Byte 2: Control Registerꢀ  
Bit  
Descriptions  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Power Up Condition  
0ꢀ=ꢀFreeꢀrunning  
0ꢀ=ꢀFreeꢀrunning  
0ꢀ=ꢀFreeꢀrunning  
0ꢀ=ꢀFreeꢀrunning  
0ꢀ=ꢀFreeꢀrunning  
0ꢀ=ꢀFreeꢀrunning  
0ꢀ=ꢀFreeꢀrunning  
0ꢀ=ꢀFreeꢀrunning  
Output(s) Affected  
OUT0,ꢀOUT0#  
OUT1,ꢀOUT1#  
OUT2,ꢀOUT2#  
OUT3,ꢀOUT3#  
OUT4,ꢀOUT4#  
OUT5,ꢀOUT5#  
OUT6,ꢀOUT6#  
OUT7,ꢀOUT7#  
Pin  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
0
1
2
AllowꢀcontrolꢀofꢀOUTPUTSꢀwithꢀ  
assertionꢀofꢀSRC_STOP#  
0ꢀ=ꢀFreeꢀrunning  
3
4
1ꢀ=ꢀStoppedꢀwithꢀSRC_Stop#  
5
6
7
Data Byte 3: Control Register  
Bit  
Descriptions  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Power Up Condition  
Output(s) Affected  
Pin  
0
1
2
3
RESERVED  
4
5
6
7
Data Byte 4: Pericom ID Register  
Bit  
Descriptions  
Type  
R
Power Up Condition  
Output(s) Affected  
Pin  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
0
0
0
0
0
0
1
0
0
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
1
R
2
R
3
R
PericomꢀID  
4
R
5
R
6
R
7
R
14-0190  
4
www.pericom.com  
03/27/13  
PI6C20800S  
PCI Express® 1:8 HCSL Clock Buffer  
Functionality  
PWRDWN#  
OUT  
OUT#  
Normal  
LOW  
SRC_Stop#  
OUT  
OUT#  
Normal  
LOW  
1
Normal  
1
Normal  
0
I
ꢀ×ꢀ2ꢀorꢀFloat  
0
I
ꢀ×ꢀ6ꢀorꢀFloat  
REF  
REF  
Power Down (PWRDWN# assertion)  
PWRDWN#  
OUT  
OUT#  
Figure 1. Power down sequence  
Power Down (PWRDWN# De-assertion)  
Tstable  
<1ms  
PWRDWN#  
OUT  
OUT#  
Tdrive_PwrDwn#  
<300us, >200mV  
Figure 2. Power down de-assert sequence  
14-0190  
5
www.pericom.com  
03/27/13  
PI6C20800S  
PCI Express® 1:8 HCSL Clock Buffer  
Current-mode output buffer characteristics of OUT[0:7], OUT[0:7]#  
VDD  
(3.3V 5ꢀ%  
Slope ~ 1/Rs  
RO  
IOUT  
ROS  
Iout  
0V  
0.85V  
VOUT = 0.85V max  
Figure 9. Simplified diagram of current-mode output buffer  
Differential Clock Buffer characteristics  
Symbol  
Minimum  
3000Ω  
Maximum  
N/A  
R
O
R
unspecified  
N/A  
unspecified  
850mV  
OS  
V
OUT  
Current Accuracy  
Symbol  
Conditions  
V ꢀ=ꢀ3.30ꢀ±5%  
DD  
Configuration  
=ꢀ475Ωꢀ1%  
Load  
Min.  
Max.  
R
Nominalꢀtestꢀloadꢀforꢀgivenꢀ  
configuration  
-12%ꢀ  
+12%ꢀ  
REFꢀ  
I
OUT  
I =ꢀ2.32mA  
REFꢀ  
I
I
NOMINAL  
NOMINAL  
Note:ꢀ  
1.ꢀ INOMINALꢀrefersꢀtoꢀtheꢀexpectedꢀcurrentꢀbasedꢀonꢀtheꢀconfigurationꢀofꢀtheꢀdevice.  
Differential Clock Output Current  
Board Target Trace/Term Z  
Reference R, Iref = V /(3xRr)  
Output Current  
ꢀ=ꢀ6ꢀxꢀI  
V
@ Z  
DD  
OH  
100Ωꢀ  
R ꢀ=ꢀ475Ωꢀ1%,ꢀ  
REF  
ꢀ=ꢀ2.32mA  
I
0.7Vꢀ@ꢀ50  
OH  
REF  
(100Ωꢀdifferentialꢀ≈ꢀ15%ꢀcouplingꢀratio)  
I
REF  
14-0190  
6
www.pericom.com  
03/27/13  
PI6C20800S  
PCI Express® 1:8 HCSL Clock Buffer  
(1)  
Absolute Maximum Ratings (Overꢀoperatingꢀfree-airꢀtemperatureꢀrange)  
Symbol Parameters  
Min.  
-0.5  
-0.5  
Max.  
4.6  
Units  
V
DD_A  
3.3VꢀCoreꢀSupplyꢀVoltage  
3.3VꢀI/OꢀSupplyꢀVoltage  
InputꢀHIGHꢀVoltage  
InputꢀLOWꢀVoltage  
StorageꢀTemperature  
ESDꢀProtection  
V
4.6  
DD  
V
V
4.6  
IH  
V
-0.5  
-65  
IL  
ꢀTs  
150  
°C  
V
ESD  
2000  
V
Note:  
1. Stressꢀbeyondꢀthoseꢀlistedꢀunderꢀ“AbsoluteꢀMaximumꢀRatings”ꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.  
DC Electrical Characteristics (V =ꢀ3.3±5%,ꢀV  
=ꢀ3.3±5%)  
DDꢀ  
DD_Aꢀ  
Symbol  
Parameters  
Condition  
Min.  
3.135  
3.135  
2.0  
Max.  
Units  
V
DD_A  
3.3VꢀCoreꢀSupplyꢀVoltage  
3.3VꢀI/OꢀSupplyꢀVoltage  
3.3VꢀInputꢀHIGHꢀVoltage  
3.3VꢀInputꢀLOWꢀVoltage  
InputꢀLeakageꢀCurrent  
3.3VꢀOutputꢀHIGHꢀVoltage  
3.3VꢀOutputꢀLOWꢀVoltage  
3.465  
3.465  
V
DD  
V
V
IH  
V
ꢀ+ꢀ0.3  
DD  
V
IL  
V
ꢀ–ꢀ0.3  
0.8  
SS  
I
IK  
0ꢀ<ꢀV ꢀ<ꢀV  
DD  
-5  
+5  
µA  
IN  
V
OH  
I
ꢀ=ꢀ-1mA  
OH  
2.4  
12.2  
1.5  
V
V
OL  
I ꢀ=ꢀ1mA  
OL  
0.4  
I
I
ꢀ=ꢀ6ꢀxꢀI ,ꢀ  
REF  
OH  
I
OH  
OutputꢀHIGHꢀCurrent  
mA  
ꢀ=ꢀ2.32mA  
REF  
15.6  
5
C
LogicꢀInputꢀPinꢀCapacitance  
OutputꢀPinꢀCapacitance  
PinꢀInductance  
IN  
pF  
C
6
OUT  
L
7
nH  
PIN  
DD  
I
PowerꢀSupplyꢀCurrent  
PowerꢀDownꢀCurrent  
PowerꢀDownꢀCurrent  
V
DD  
ꢀ=ꢀ3.465V,ꢀꢀF  
ꢀ=ꢀ100MHz  
CPU  
250  
80  
12  
70  
85  
I
SS  
Drivenꢀoutputs  
Tristateꢀoutputs  
mA  
°C  
I
SS  
Commercialꢀ(PI6C20800S)  
Industrialꢀ(PI6C20800SI)  
0
T
A
AmbientꢀTemperature  
-40  
14-0190  
7
www.pericom.com  
03/27/13  
PI6C20800S  
PCI Express® 1:8 HCSL Clock Buffer  
(1,2,3)  
AC Switching Characteristics  
(V =ꢀ3.3±5%,ꢀV  
=ꢀ3.3±5%)  
DDꢀ  
DD_Aꢀ  
Symbol  
Parameters  
Min  
95  
Max.  
105  
Units  
MHz  
MHz  
Notes  
SRC/SRC#ꢀInputꢀFrequencyꢀPLLꢀMode  
SRC/SRC#ꢀInputꢀFrequencyꢀBypassꢀMode  
6
6
2
F
in  
95  
400  
T
/ꢀT  
RiseꢀandꢀFallꢀTimeꢀꢀ(measuredꢀbetweenꢀ0.175Vꢀtoꢀ0.525V)  
175  
700  
riseꢀ fall  
ps  
ΔT /ꢀ  
riseꢀ  
RiseꢀandꢀFallꢀTimeꢀVariation  
125  
2
ΔT  
fall  
PI6C20800S  
-250  
-450  
-6  
250  
450  
6
PLLꢀMode  
ps  
ns  
ps  
PI6C20800SI  
PI6C20800S  
PI6C20800SI  
InputꢀtoꢀOutputꢀPropagationꢀ  
Delay  
T
pd  
BypassꢀMode  
-8  
8
Output-to-OutputꢀSkewꢀ(PI6C20800S)  
Output-to-OutputꢀSkewꢀ(PI6C20800SI)  
VoltageꢀHIGHꢀ(Measuredꢀatꢀ100MHzꢀ@ꢀ3.3V)  
Max.ꢀVoltage  
50  
3
3
2
T
skew  
65  
V
600  
900  
1150  
HIGH  
V
OVS  
UDS  
LOW  
V
Min.ꢀVoltage  
-300  
-150  
250  
mV  
V
VoltageꢀLOWꢀ  
+150  
550  
140  
57  
2
2
2
3
V
cross  
Absoluteꢀcrossingꢀpoingꢀvoltages  
ΔV  
TotalꢀVariationꢀofꢀV  
overꢀallꢀedges  
crossꢀ  
cross  
DC  
T
DutyꢀCycleꢀ(Measuredꢀꢀatꢀ100ꢀMHz)  
45  
%
ps  
ps  
Jitter,ꢀCycle-to-cycleꢀ(PLLꢀMode,ꢀMeasurementꢀforꢀdifferentialꢀ  
waveform)  
T
70  
4
5
jcyc-cyc  
Jitter,ꢀCycle-to-cycleꢀ(BYPASSꢀmodeꢀasꢀadditiveꢀjitter)  
AdditiveꢀRMSꢀphaseꢀjitterꢀforꢀPCIeꢀ2.0  
J
add  
<0  
1
Notes:  
1.ꢀ TestꢀconfigurationꢀisꢀRSꢀ=ꢀ33.2Ω,ꢀRpꢀ=ꢀ49.9Ω,ꢀandꢀ2pF.  
2.ꢀ MeasurementꢀtakenꢀfromꢀSingleꢀEndedꢀwaveform.ꢀꢀ  
3.ꢀꢀ MeasurementꢀtakenꢀfromꢀDifferentialꢀwaveform.  
4.ꢀ MeasuredꢀusingꢀM1ꢀtimingꢀanalyzerꢀfromꢀAmherst.  
5.ꢀꢀꢀꢀꢀAdditiveꢀjitterꢀisꢀcalculatedꢀfromꢀinputꢀandꢀoutputꢀRMSꢀphaseꢀjitterꢀbyꢀusingꢀPCIeꢀ2.0ꢀfilter.ꢀ(Jaddꢀ=ꢀ√ꢀ(outputꢀjitter)2ꢀ–ꢀ(inputꢀjitter)2ꢀꢀ)  
6.ꢀꢀ –0.5%ꢀdownnspreadꢀinput  
Configuration Test Load Board Termination  
Rs  
33Ω  
5%  
OUT  
TLA  
PI6C20800S  
or  
Rs  
33Ω  
5%  
PI6C20800SI  
OUT#  
TLB  
2pF  
5%  
2pF  
5%  
Rp  
49.9Ω  
1%  
Rp  
49.9Ω  
1%  
475Ω  
1%  
14-0190  
8
www.pericom.com  
03/27/13  
PI6C20800S  
PCI Express® 1:8 HCSL Clock Buffer  
Packaging Mechanical: 48-Pin SSOP (V)  
DATE: 09/27/11  
Notes:  
DESCRIPTION: 48-Pin, 300-Mil Wide, SSOP  
1. All dimensions are in inches  
2. JEDEC outline : MO-118 AA.  
3. Dimensions E and D do not include mold protrusion.  
PACKAGE CODE: V (V48)  
DOCUMENT CONTROL #: PD-1401  
REVISION:F  
14-0190  
9
www.pericom.com  
03/27/13  
PI6C20800S  
PCI Express® 1:8 HCSL Clock Buffer  
Packaging Mechanical: 48-Pin TSSOP (A)  
DOCUMENT CONTROL NO.  
PD - 1501  
48  
REVISION: G  
DATE: 03/09/05  
.236  
.244  
6.0  
6.2  
See Note 4  
1
.488 12.4  
See Note 3  
.496 12.6  
.047  
1.20 Max  
SEATING PLANE  
0.09  
0.20  
.004  
.008  
0.45 .018  
0.75 .030  
.002  
.007  
.010  
.0197  
BSC  
.006  
0.05  
0.15  
.319  
BSC  
X.XX  
X.XX  
DENOTES DIMENSIONS  
IN MILLIMETERS  
0.50  
0.17  
0.27  
8.1  
Note:  
1. Controlling dimensions in millimeters.  
2. Ref: JEDEC MO-153F/ED  
3. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protru-  
sions and gate burrs shall not exceed 0.15mm per side.  
Pericom Semiconductor Corporation  
3545 N. 1st Street, San Jose, CA 95134  
1-800-435-2335 • www.pericom.com  
4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion  
shall not exceed 0.25mm per side.  
DESCRIPTION: 48-Pin 240-Mil Wide TSSOP  
PACKAGE CODE: A  
(1,2)  
Ordering Information  
Ordering Code  
Package Code  
Package Description  
48-pin,ꢀ300-milꢀwide,ꢀSSOP,ꢀPb-FreeꢀandꢀGreen  
48-pin,ꢀ240-milꢀwide,ꢀTSSOP,ꢀPb-FreeꢀandꢀGreen  
PI6C20800SVE  
VE  
AE  
VE  
AE  
PI6C20800SAE  
PI6C20800SIVE  
PI6C20800SIAE  
48-pin,ꢀ300-milꢀwide,ꢀSSOP,ꢀPb-FreeꢀandꢀGreenꢀ(Industrial)  
48-pin,ꢀ240-milꢀwide,ꢀTSSOP,ꢀPb-FreeꢀandꢀGreenꢀ(Industrial)  
Notes:  
1.ꢀꢀ Thermalꢀcharacteristicsꢀcanꢀbeꢀfoundꢀonꢀtheꢀcompanyꢀwebꢀsiteꢀatꢀwww.pericom.com/packaging/  
2.ꢀ Eꢀ=ꢀPb-freeꢀandꢀGreen  
3.ꢀ AddingꢀanꢀXꢀsuffixꢀ=ꢀTape/Reel  
PericomꢀSemiconductorꢀCorporationꢀꢀ•ꢀ1-800-435-2336ꢀ •ꢀ www.pericom.comꢀ  
14-0190  
10  
www.pericom.com  
03/27/13  
®
®
®
PCIe , and the PCI EXPRESS design mark are trademarks of PCI-SIG (www.pcisig.com)  

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