PI6C21900SZDEX [PERICOM]
PLL Based Clock Driver, 6C Series, 19 True Output(s), 0 Inverted Output(s), GREEN, MO-220I/VNND, TQFN-72;
| 型号： | PI6C21900SZDEX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PLL Based Clock Driver, 6C Series, 19 True Output(s), 0 Inverted Output(s), GREEN, MO-220I/VNND, TQFN-72 驱动 逻辑集成电路 |
| 文件： | 总19页 (文件大小：523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C21900S
PCI Express GenII 1:19 Geared Differential
Buffer -18 and 1 Outputs
Description
Features
PI6C21900S is a PCI Express Gen-II complient, high-speed, low-
noisePCI-ExpressandFBDIMMdifferentialclockbufferdesigned
tobeacompaniontotheworkstation/serverclocksynthesizersuchas
PI6C410B. Thedevicedistributesnineteencopiesofthedifferential
SRC clock, such as the one sourced from PI6C410B. To adapt to
different systems and to offer various performance platforms, the
PI6C21900S outputs can be programmed to different frequency.
Theoutputfrequency ratio can bemodifiedtooffervariousderiva-
tive frequency from the input frequency. Most of the output pair is
controlled by individual OE pin. Some OE# pins service multiple
differentialoutputpairs.Theclockoutputsarecontrolledbytheinput
selectionbits:SA_0,SA_1,SA_2throughexternalselectpinsorvia
• Phase jitter filter for PCIe GenII application
• Nineteen Pairs of differential HCSL buffers
-18 and 1 outputs
• Low skew < 100ps within Dif (16:0) group
• Low phase jitter < 108ps (PLL mode)
• Output Enable (OE) pins for all outputs
• Outputs tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or PLL Bypass (Fanout) mode
• Gear Ratios for different input to output frequencies
- Input: 100, 133, 166, 200, 266, 333, or 400 MHz
- Output: 100, 133, 166 or 200 MHz
• 3.3V Operation
SMBus, using SCL (SMBus Clock) and SDA (SMBus Data) pins.
• Packaging (Pb-Free and Green):
—72-pin TQFN (ZD)
Block Diagram
Pinout Configuration
OE18#
18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
DIF (18)
Gear
Shift
Logic
Spread
Compatible
PLL
1
72 SA_2/PLL/BYPASS#
71 CLK_IN#
70 CLK_IN
69 OE_18#
68 DIF_18#
67 DIF_18
SCL 19
SDA 20
Stop
Logic
OE_5# 21
DIF_5 22
DIF_5# 23
OE_6# 24
DIF_6 25
DIF_6# 26
VDD 27
OE16_17#
13
OE(15:5)#,
OE_01234#
DIF (17:0)
66 DIF_17#
65 DIF_17
Spread
Compatible
PLL
Gear
Shift
Logic
CLK_IN
18
Stop
Logic
CLK_IN#
64 VSS
63 VDD
62 DIF_16#
61 DIF_16
60 OE_16_17#
59 DIF_15#
58 DIF_15
57 OE_15#
56 DIF_14#
55 DIF_14
VSS 28
HIGH_RW#
FS_A_410
OE_7# 29
DIF_7 30
DIF_7# 31
OE_8# 32
DIF_8 33
DIF_8# 34
SA_0 35
Control
Logic
SMB_A0
SMB_A1
SMB_A2 PLLBYP#
SMBDAT
SMBCLK
IREF
SA_1
36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
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PI6C21900S
1:19 Geared Differential Buffer for PCI-Express
Pin Description
Pin Name
Type
Pin #
70,71
Description
CLK_IN, CLK_IN#
I, DIF
0.7V Differential input (eg. from PI6C410B clock synthesizer)
22,23,25,26,30,31,33,34,
DIF & DIF# [16:5]
DIF & DIF# [18:17]
O, DIF 38,39,41,42,44,45,49,50, 0.7V Differential clock outputs, geared to the a ratio of the input clock.
52,53,55,56,58,59,61,62
0.7V Differential clock outputs, which can be configured to be 1:1
65,66,67,68
O, DIF
O, DIF
instead of geared. Default is geared same as 0-16 outputs.
6,7,8,9,12,13,
14,15,16,17
0.7V Differential clock outputs, geared to the a ratio of the input clock.
DIF & DIF# [4:0]
OE#_[15:5]
3.3 V LVTTL active low input for enabling differential
outputs(default). Controls each output pair. OE can be disabled by
SMBus registers.
21,24,29,32,37,40,43,48,
51,54,57
I, SE
I, SE
I, SE
I, SE
3.3V LVTTL active low input for enabling differential outputs. The
pin controls both DIF_16 and DIF_17 pairs. Individual disables are
available via SMBus.
OE_16_17#
OE_18#
60
69
18
3.3 V LVTTL active low input for enabling differential
outputs(default). Controls each output pair. OE can be disabled by
SMBus registers.
3.3V LVTTL active low input for enabling differential outputs. The
pin controls both DIF_0 through DIF_4 pairs. Individual disables are
available via SMBus.
OE_0_1_2_3_4#
HIGH_BW#
SCL
I, SE
I, SE
I/O, OC
4
3.3V LVTTL input for selecting the PLL bandwidth (high = low BW)
SMBus slave clock input
Open collector SMBus data
19
20
SDA
A precision resistor is attached to this pin to set the differential output
IREF
SA_[0:1]
I
I
I
1
current. Default is 475Ω
35,36
72
3.3V LVTTL input selecting the address for SMBus address
SA_2/PLL_BYPASS#
3.3V LVTTL input for PLLbypass and SMBus address
GTL level input to establish a high(>=200 MHz) or low frequency
(<200 MHz) range. This is a low-voltage threshold input. Please see
the VIL_FS and VIH_FS specifications.
FS_A
I
5
3
3.3V Power Supply for PLL / Input to power down the device. When
this input is low, outputs are hi-Z and PLL off.
VDD_A / PWRDN#
3.3V
VSS_A
VSS
VDD
GND
I
3.3V
2
Ground for PLL
Ground for outputs
3.3 V power supply for outputs
10,28,46,64
11,27,47,63
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1:19 Geared Differential Buffer for PCI-Express
Signals and Features Description
Gear Ratio
Gear ratio defines the relationship between input to output frequency. The input frequencies are normally
100.00, 133.33, 166.67, 200.00, 266.67, 333.33 and 400.00 MHz. The outputs are also range between 100 to
400 MHz. Gear ratio gives the flexibility to select the desired output frequency based on the input frequency.
Gear Ratio is programmable througn the SMBus interface and FS_A pin. FS_A pin informs the PI6C21900
about the input frequency range. FS_A = 1 indicates input frequency between 100.0 MHz and 166.67 MHz.
FS_A = 0 indicates input frequency range of 200.00 MHz to 400 MHz.
Table 1. DB 1900 G Programmable Gear Ratio Table
Input/Output Frequencies (MHs)
Gear Ratio
(N/M)
200.0
266.7
320.0
333.3
400.0
133.3
160.0
167.7
200.0
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
3
5
1
2
5
1
3
5
2
3
5
1
0.333
0.400
0.417
0.500
0.600
0.625
0.667
0.750
0.833
1.000
133.3
3
12
2
100.0
133.3
133.3
166.7
200.0
166.7
200.0
4
5
5
6
8
266.7
7
3
8
4
1.677
200.0
333.3
400.0
9
6
266.7
333.3
320.0
333.3
10
1
11
12
13
14
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
0
0
1
4
3
3
1
5
4
5
2
1.250
1.333
1.667
2.000
266.7
333.3
400.0
Input/Output Frequencies (MHs)
100.0
133.3
160.0
166.7
133.3
166.7
200.0
15
16
17
1
1
1
0
1
1
1
0
0
1
0
1
1
1
0
5
1
5
4
1
6
0.800
1.000
1.200
100.0
133.3
160.0
166.7
200.0
266.7
18
19
20
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
4
2
1
5
3
2
1.250
1.500
2.000
320.0
Note: Shaded lines are Power-up defaults for FS_A=0 and 1 repectively. Output frequency numbers in BOLD
are valid operating frequencies.
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1:19 Geared Differential Buffer for PCI-Express
Default conditions
Default conditions are defined in conjunction with the power up sequence to ensure system operation
sufficient to configure the timing parameters of the system. Default conditions have also been defined
to account for the typical use of component to support platform debug or analysis.
Outputs are enabled as a default. To prevent over drive of high speed input clock configurations,
explicit system control of pin level output enables are recommended. General purpose I/O gates or
controls can be used to gate the output via pin level OE numbers. One can then use system controls to
program the desired gear ratio before enabling the outputs.
OE# and Output enables
Output enables are asynchronous asserted - low signals. Outputs are enabled by default. Two mecha-
nisms exist to disable the outputs, either by pin or by programming the control registers via the
SMBus.
OE Functionality Table
OE (Pin)
OE (SMBus bit)
DIFF
Diff #
Normal
Tristate
Tristate
Tristate
Note
0
1
1
0
1
0
1
0
Normal
Tristate
Tristate
Tristate
FS_A
The FS_A pin is a low-threshold latched input to the buffer to designate whether the input frequency
is greater than/equal to or less than 200 MHz. The signal is consistant with the FS_A input to the
main clock synthesizer.
Functionality at Power Up (PLL Mode) Table
FS_A
CLK_IN (CPU FSB) MHz
100 ≤ CLK_IN < 200
200 ≤ CLK_IN ≤ 400
DIFF[16:0]
CLK_IN
CLK_IN
1
0
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1:19 Geared Differential Buffer for PCI-Express
VDD_A/PWRD WN#
3.3V power for the PLL core also functions as a Power Down. Collapsing this power supply places the
device in Power Down mode. Pulling the VDD_A/PWRDN# (Power Down) pin low can be used to shut off
all clocks cleanly and instruct the device to evoke power savings mode.
VDD_A/PWRDWN# Functionality Table
INPUTS
CLK_IN/CLK_IN#
OUTPUTS
PLL STATE
VDD_A
3.3V(NCM)
GND
DIF
DIF#
Running
X
Running
Hi-Z
ON
OFF
Power Down Timing Sequence (PWRDWN# - Assertion)
PWRDWN#
+
DIF
DIF#
HIGH_BW#
The HIGH_BW# input is used to set the PLL bandwidth. This mode is intended to minimize PLL peaking
when two or more buffers are cascaded by staggering device bandwidths. The default condition is in a low
bandwidth mode.The PLL high bandwidth mode may be selected in two ways, via writing a '0' to SMBus reg-
ister bit or by asserting the HIGH_BW# pin low. In both methods, if the SMBus register bit has been written
low or the HIGH_BW# pin low or both, the device will be configured for high bandwidth operation.
HIGH_BW# Fynctionality Table
HIGH_BW#
(Pin)
HIGH_BW#
(SMBus bit)
PLL Operating Band-
width
Note
0
1
1
0
1
1
0
0
High
Low
High
High
SMBus bit defaults to '1'
SMBus bit defaults to '1'
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1:19 Geared Differential Buffer for PCI-Express
PLL_BYPASS#
The PLL/BYPASS# input is used to select between bpass mode (no PLL) and PLL mode. In bypass mode, the
input clock is passed directly to the output. In the case of PLL mode, the input clock is passed through a PLL ot
reduce high frequency jitter.The PLL_Bypass# mode may be selected in two ways, via writing a '0' to SMBus
register bit or by asserting the SA_2/PLL/BYPASS# pin low or both, the device will be configurized for BY-
PASS operation.
SA_[0:1], SA_2 / PLL_Bypass#
The SA pins define the SM_Bus address to which the device is to respond. Multiple addresses are required to
support multiple clock devices especially for large system configurations. The SA_2 pin shares functionality
with PLL_bypass# mode setting.
The SA pins select up to 8 unique logical clocking device addresses within an SMBus chain. Accounting for the
fixed addresses already used by the synthesizer and PI6C401B, this leaves 6 address available for PI6C21900
devices on the same SMBus chain.
PI6C21900 SMBus Address Selection Table
SA_[2:0]
000
Address
D0
PLL Operating Mode
BYPASS (non-PLL)
BYPASS (non-PLL)
BYPASS (non-PLL)
BYPASS (non-PLL)
PLL
Note
001
D2
Address of Main Clock Synthesizer
010
D4
011
D6
100
D8
101
DA
DC
DE
PLL
110
PLL
Address of PI6C410B
111
PLL
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1:19 Geared Differential Buffer for PCI-Express
Power Up State Diagram
State#
S0
State Name
Off State
Description
3.3V power to PI6C21900S is OFF
Notes
S1
Power Up Delay
After 3.3V supply voltage is higher than 1.8V, then the device en-
ters state-1, and starts 0.2 ~ 0.3 ms delay
S2
S3
Pending Valid Clock
Normal Operation
Device is waiting for valid clock input
2
1
Notes:
1. Power up latency is 1.8ms from valid input clock detected to outputs active
2. Prior to enabling output clocks, ensure all the conditions are met: (i) power is valid and stable, (ii) PWRDWN is deasserted, (iii)
valid input clock detected, and (iv) PLL is locked and stable. Otherwise, the outputs must remain disabled.
No input clock
S1
Delay >
0.25ms
S2
Wait for input
clock and
PWRDWN
deasserted
PWRDWN asserted
S0
S3
Normal
Operation
Power Off
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PI6C21900S
1:19 Geared Differential Buffer for PCI-Express
SA_[0:1] and SA_2/PLL_BYPASS# pins
SA_[0:2] are used for setting the SMBus address. In some systems there maybe a few similar SMBus devices, to avoid
contention each device needs a unique address. These pins are static, dynamic address reallocation is not allowed. SA
pins are sampled and latched once the 3.3V rail exceeds 1.8V.
SMBus Address Mapping
Devices
Description
A[7:4]
A[3]
A[2] A[1] A[0]
Default Ad-
dress
Notes
PI6C410B
Server/Workstation
Clock Generator
DxH
0
0
1
0
D2H
Fixed address
PI6C20400
PI6C20800
1:4 Differential Buffer
1:8 Differentiall Buffer
DxH
DxH
1
1
1
1
0
0
0
0
DCH
DCH
Fixed address
Fixed address
PI6C21900S
PI6C21900S
1:19 Differential Buffer
1:19 Differential Buffer
DxH
DxH
SA_2 SA_1 SA_0
0
0
D2H ~ DEH
D2H ~ D6H
Address Range
0
x
x
Bypass Mode, default
D6H
PI6C21900S
1:19 Differential Buffer
DxH
1
x
x
0
D8H ~ DEH
PLL mode, default
addr DEH
Serial Data Interface (SMBus)
PI6C21900S is a slave only SMBus device that supports random byte read and write indexed block read and write protocol using a
single 7-bit address and read/write bit as shown below.
Indexed Block Read and Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address - 7 bits
Write = 0
2:8
9
Slave address - 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
Command Code - 8 Bits
'00000000' Stand for block operation
Command Code - 8 Bits
'00000000' Stand for block operation
11:18
11:18
19
20:27
28
Acknowledge from slave
19
20
Acknowledge from slave
Repeat start
Byte Count from master - 8 bits
Acknowledge from slave
21:27
28
Slave address - 7 bits
Read = 1
29:36
37
Datat byte 0 from master - 8 bits
Acknowledge from slave
29
Acknowledge from slave
Byte count from slave - 8 bits
38:45
Datat byte 1 from master - 8 bits
30:37
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1:19 Geared Differential Buffer for PCI-Express
Indexed Block Read and Write Protocol (contnued)
Block Write Protocol
Block Read Protocol
Bit
46
....
....
....
....
Description
Acknowledge from slave
Bit
38
Description
Acknowledge from host
Data bytes from master/Acknowledge
Data byte N - 8 bits
Acknowledge from slave
Stop
39:46
47
Data byte 0 from slave - 8 bits
Acknowledge from host
Data byte 1 from slave - 8 bits
Acknowledge from host
Data bytes from slave/Acknowledge
Data byte N from slave - 8 bits
Acknowledge from host
Stop
48:55
56
....
....
....
....
Random Byte Read and Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address - 7 bits
Write = 0
2:8
9
Slave address - 7 bits
Write - 0
10
Acknowledge from slave
10
Acknowledge from slave
Command Code - 8 bits
Command Code - 8 bits
'100xxxxx' stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed.
'100xxxxx' stands for byte operation, bits[6:0]
of the command code represents the offset of the
byte to be accessed.
11:18
11:18
19
20:27
28
Acknowledge from slave
Data byte from master - 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address - 7 bits
Read = 1
29
29
Acknowledge from slave
Data byte from slave - 8 bits
Acknowledge from master - #38 bit
Stop
30:37
38
39
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1:19 Geared Differential Buffer for PCI-Express
Data Byte 0: Control Register
Bit
Description / Function Center
Type
Power up Condition
Output(s) Affected
Source Pin
0
FSB Gear Ratio SMBus
FSB Gear Ratio SMBus
RW
1
N/A
1
RW
0
N/A
2
3
FSB Gear Ratio SMBus
FSB Gear Ratio SMBus
RW
RW
0
1
N/A
N/A
(1)
4
FS_A CK410B Latched Input
RW
Depends on FS_A pin
N/A
5
6
RW
RW
1
1
Reserved
N/A
N/A
Group of 1 gear ratio select
0 = Gear Ratio, 1 = 1:1
DIF (18)
DIF# (18#)
Group of 18 gear ratio select
0 = Gear Ratio, 1 = 1:1
DIF(17:0)
DIF#(17:0)
7
RW
1
N/A
Note:
1. When FS_A = 1, Bit 1 = 0 and Bit 3 = 1; When FS_A = 0, Bit 1 = 1 and Bit 3 = 0
Data Byte 1: Control Register
Bit
Description / Function Center
Type
Power up Condition
Output(s) Affected
Source Pin
Output Control
0 = Hi-Z, 1 = Enable
DIF_0
DIF#_0
0
RW
1 = Enable
6,7
Output Control
0 = Hi-Z ,1 = Enable
DIF_1
DIF#_1
1
2
3
4
5
6
RW
RW
RW
RW
RW
RW
1 = Enable
1 = Enable
1 = Enable
1 = Enable
1 = Enable
1 = Enable
8,9
Output Control
0 = Hi-Z, 1 = Enable
DIF_2
DIF#_2
12,13
14,15
16,17
22,23
25,26
Output Control
0 = Hi-Z, 1 = Enable
DIF_3
DIF#_3
Output Control
0 = Hi-Z, 1 = Enable
DIF_4
DIF#_4
Output Control
0 = Hi-Z, 1 = Enable
DIF_5
DIF#_5
Output Control
0 = Hi-Z, 1 = Enable
DIF_6
DIF#_6
Output Control
0 = Hi-Z, 1 = Enable
DIF_7
DIF#_7
7
RW
1 = Enable
30,31
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1:19 Geared Differential Buffer for PCI-Express
Data Byte 2: Control Register
Bit
Description / Function Center
Type
Power up Condition
Output(s) Affected
Source Pin
Output Control
0 = Hi-Z, 1 = Enable
DIF_8
DIF#_8
0
RW
1 = Enable
33,34
Output Control
0 = Hi-Z, 1 = Enable
DIF_9
DIF#_9
1
2
3
4
5
RW
RW
RW
RW
RW
1 = Enable
1 = Enable
1 = Enable
1 = Enable
1 = Enable
38,39
41,42
44,45
49,50
52,53
Output Control
0 = Hi-Z, 1 = Enable
DIF_10
DIF#_10
Output Control
0 = Hi-Z, 1 = Enable
DIF_11
DIF#_11
Output Control
0 = Hi-Z, 1 = Enable
DIF_12
DIF#_12
Output Control
0 = Hi-Z, 1 = Enable
DIF_13
DIF#_13
Bypass and PLL selection
0 = BYPASS, 1 = PLL
BYPASS# TEST_
MODE / PLL
6
7
RW
RW
1 = PLL
30
1
PLL Bandwidth Adjust
1 = Low BW
0 = High Bandwidth, 1=Low Bandwidth
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Data Byte 3: Control Register
Bit
Description / Function Center
Type
Power up Condition
Output(s) Affected
Source Pin
Latched input at power
up
0
SA_2/PLL/BYPASS#
HIGH_BW#
R
All
72
Latched input at power
up
Depends on state of pin
at power-up
1
2
R
R
All
4
OE_01234# Input
DIF_01234 Output enable
0 = Enable, 1 = Disable (tristate)
DIF_01234
DIF_01234#
18
OE_5# Input
DIF_5 Output enable
0 = Enable, 1 = Disable (tristate)
OE_6# Input
DIF_6 Output enable
0 = Enable, 1 = Disable (tristate)
DIF_5
DIF_5#
Depends on state of pin
at power-up
3
4
R
R
21
24
DIF_6
DIF_6#
Depends on state of pin
at power-up
OE_7# Input
DIF_7 Output enable
0 = Enable, 1 = Disable (tristate)
Depends on state of pin
at power-up
DIF_7
DIF_7#
5
R
29
Depends on state of pin
at power-up
OE_8# Input
DIF_8 Output enable
0 = Enable, 1 = Disable (tristate)
DIF_8
DIF_8#
6
7
R
R
32
37
OE_9# Input
DIF_9 Output enable
0 = Enable, 1 = Disable (tristate)
DIF_9
DIF_9#
Depends on state of pin
at power-up
Data Byte 4: Control Register
Bit
Description / Function Center
Type
Power up Condition
Output(s) Affected
Source Pin
OE_10# Input
DIF_10
DIF_10#
Depends on state of pin
at power-up
0
DIF_10 Output enable
R
40
0 = Enable, 1 = Disable (Hi-Z)
OE_11# Input
DIF_11 Output enable
0 = Enable, 1 = Disable (Hi-Z)
OE_12# Input
DIF_12 Output enable
0 = Enable, 1 = Disable (Hi-Z)
OE_13# Input
DIF_13 Output enable
0 = Enable, 1 = Disable (Hi-Z)
OE_14# Input
DIF_14 Output enable
0 = Enable, 1 = Disable (Hi-Z)
OE_15# Input
DIF_15 Output enable
0 = Enable, 1 = Disable (Hi-Z)
OE_16_17# Input
DIF_16_17 Output enable
0 = Enable, 1 = Disable (Hi-Z)
OE_17_18# Input
DIF_17_18 Output enable
0 = Enable, 1 = Disable (Hi-Z)
DIF_11
Depends on state of pin
at power-up
1
2
3
4
5
6
7
R
R
R
R
R
R
R
43
48
51
54
57
60
69
DIF_11#
DIF_12
DIF_12#
Depends on state of pin
at power-up
DIF_13
DIF_13#
Depends on state of pin
at power-up
DIF_14
DIF_14#
Depends on state of pin
at power-up
DIF_15
DIF_15#
Depends on state of pin
at power-up
DIF_16, DIF_17
DIF_16#, DIF_17#
Depends on state of pin
at power-up
DIF_18
DIF_18#
Depends on state of pin
at power-up
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PI6C21900S
1:19 Geared Differential Buffer for PCI-Express
Data Byte 5: Pericom ID Register
Bit
Description / Function Center
Type
R
Power up Condition
Output(s) Affected
Source Pin
N/A
0
Vendor ID – VID0
0
0
0
0
0
1
0
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
Vendor ID – VID1
R
N/A
2
Vendor ID – VID2
R
N/A
3
Vendor ID – VID3
R
N/A
4
Revision ID – RID0
Revision ID – RID1
Revision ID – RID2
Revision ID – RID3
R
N/A
5
R
N/A
6
R
N/A
7
R
N/A
Data Byte 6: Pericom Device ID Register
Bit
0
Description / Function Center
Device ID 0
Type
R
Power up Condition
Output(s) Affected
Source Pin
N/A
0
0
1
1
0
0
0
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
Device ID 1
R
N/A
2
Device ID 2
R
N/A
3
Device ID 3
R
N/A
4
Device ID 4
R
N/A
5
Device ID 5
R
N/A
6
Device ID 6
R
N/A
7
Device ID 7 (MSB)
R
N/A
Data Byte 7: Byte Counter Register
Bit
0
Description / Function Center
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power up Condition
Output(s) Affected
Source Pin
N/A
BC0 - Writing to this register configures
1
0
0
1
0
0
0
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
how many bytes will be read back
BC1 - Writing to this register configures
1
N/A
how many bytes will be read back
BC2 - Writing to this register configures
2
N/A
how many bytes will be read back
BC3 - Writing to this register configures
3
N/A
how many bytes will be read back
BC4 - Writing to this register configures
4
N/A
how many bytes will be read back
BC5 - Writing to this register configures
5
N/A
how many bytes will be read back
BC6 - Writing to this register configures
6
N/A
how many bytes will be read back
BC7 - Writing to this register configures
7
N/A
how many bytes will be read back
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PI6C21900S
1:19 Geared Differential Buffer for PCI-Express
Data Byte 8: Control Register
Bit
0
Description / Function Center
Type
RW
RW
RW
RW
RW
Power up Condition
1 = Enable
Output(s) Affected
Source Pin
55, 56
DIF_14
DIF#_14
DIF_15
DIF#_15
1
1 = Enable
58, 59
Output Control
0 = Hi-Z
1 = Enable
DIF_16
DIF#_16
2
1 = Enable
61, 62
DIF_17
DIF#_17
3
1 = Enable
65, 66
DIF_18
DIF#_18
4
1 = Enable
67, 68
5
6
7
Reserved
Reserved
All
Latched Value at
power up
FS_A
R
5
Current-mode output buffer characteristics of OUT[0:18], OUT[0:18]#
V
DD
(3.3V ±5%)
Slope ~ 1/R
O
R
O
I
OUT
R
V
OS
I
OUT
1.2V
V
= 1.2V max
0V
OUT
OUT
Figure 3. Simplified diagram of current-mode output buffer
PS8898A
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PI6C21900S
1:19 Geared Differential Buffer for PCI-Express
Differential Clock Buffer Characteristics
Symbol
Minimum
Maximum
N/A
R
3000Ω
unspecified
N/A
O
R
unspecified
850mV
OS
V
OUT
Current Accuracy
Symbol
Conditions
V = 3.30 ±5%
DD
Configuration
Load
Min.
-12% I
Max.
+12% I
NOMINAL
R
= 475Ω 1%
Nominal test load for given
REF
I
OUT
NOMINAL
I
= 2.32mA
configuration
REF
Note: INOMINAL refers to the expected current based on the configuration of the device.
Differential Clock Output Current
Board Target Trace/Term Z
Reference R, Iref = V /(3xRr)
Output Current
V
OH
@ Z
DD
100Ω differential
R = 475Ω 1%, I
REF
= 2.32mA
I = 6 x Iref
OH
0.7V @ 50-Ohm
REF
Absolute Maximum Ratings (Over free-air operating temperature range)
Symbol
Parameters
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
Input High Voltage
Input Low Voltage
Min.
-0.5
-0.5
Max.
4.6
Units
V
DD_A
V
4.6
DD
V
V
IH
4.6
V
IL
-0.5
-65
Ts
Storage Temperature
ESD Protection
150
°C
V
V
ESD
2000
Note: Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Electrical Characteristics (V = 3.3±5%, V
= 3.3 ±5%)
DD
DD_A
Symbol
Parameters
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
3.3V Input High Voltage
3.3V Input Low Voltage
Condition
Min.
3.135
3.135
2.0
Max.
3.465
3.465
Units
V
DD_A
V
DD
V
V
IH
V
V
+ 0.3
DD
V
IL
V
– 0.3
SS
0.8
+5
+ 0.3
(1)
I
Input Leakage Current
0 < V < V
DD
-5
0.7
– 0.3
μA
IL
IH_FS
IN
(2)
V
FS_A Input High Voltage
FS_A Input High Voltage
DD
V
(2)
V
IL_FS
V
0.35
SS
PS8898A
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PI6C21900S
1:19 Geared Differential Buffer for PCI-Express
DC Electrical Characteristics (V = 3.3±5%, V
= 3.3 ±5%, continued)
DD
DD_A
Symbol
Parameters
3.3V Output High Voltage
3.3V Output Low Voltage
Condition
= -1mA
Min.
Max.
Units
V
OH
I
OH
2.4
V
V
OL
I
OL
= 1mA
0.4
4.5
4.5
7
(3)
C
IN
Input Pin Capacitance
2.5
2.5
pF
(3)
C
OUT
Output Pin Capacitance
L
Pin Inductance
nH
°C
PIN
T
A
Ambient Temperature
Power Supply Current
Power Down Current
No air flow
= 3.465V, F = 400MHz
0
70
I
DD
V
DD
600
36
CPU
mA
I
SS
Tristate outputs
Notes:
1. Input Leakage Current does not include inputs with pullups or pulldowns.
2. Internal voltage reference is used to guarantee these thresholds
3. Internal silicon capacitance, does not include pin capacitance
Skew and Jitter Characteristics
Input to output relationships are applicable only in 1:1 mode. Output to output relationships are applicable when all
outputs are the same frequency.
In PLL mode, DIF_18 can be configured as 1:1, different from the others. The default is same gear ratio. This group of
two and group of five may incur additional skew from the others.
Skew and Jitter Timing Parameters (Ta = 0 ~ 70C, Vdd = 3.3V, 5%)
Symbol
Tpd_PLL_nom
Tpd_Bypass_nom
Tskew1
Description
Conditions
Min
Max Unit
Notes
1,2,4,5
CLK to DIF_xx Skew in 1:1 PLL mode
CLK to DIF_xx Skew in 1:1 Bypass mode
DIF_[0:17] output to output Skew
DIF_[0:18] output to output Skew
Nominal Voltage and
Temperature
1.0
5.5
ns
ns
ps
ps
2.5
2,3,5
1,2
100
250
Tskew_all
Same gear ratio or
Bypass mode
1,2,3
Notes:
1. Measured across 2pF.
2. Measured between differential crosspoints
3. Applicable to same edges; i.e. rising to rising, or falling to falling
4. Deterministic values
5. Measured mean values with scope averaging on
PS8898A
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PI6C21900S
1:19 Geared Differential Buffer for PCI-Express
PLL Bandwidth and Peaking
Parameter
Target Min
< 1.0
Max Unit
Notes
PLL Peaking (HIGH_BW# = 0)
PLL Peaking (HIGH_BW# = 1)
PLL Bandwidth (HIGH_BW# = 0)
PLL Bandwidth (HIGH_BW# = 1)
< 2.5
< 2.0
4
dB
dB
2
2
1
1
< 1.0
3
1
2
MHz
MHz
0.7
1.4
Notes:
1. Measured @ 3dB down or Half Power point
2. Measured as max pass band gain
3. Post processed evaluation through Intel FB-DIMM Draft Spec Rev. 0.5.
4. These jitter are needed to achieve BER of 1E-12. Measured values with smaller sample size have to ve extrapolated to acheive 1E-12 BER.
Differential AC Characteristics (V = 3.3±5%, V
= 3.3 ±5%, SSC=-0.5%)
DD
DD_A
Symbol
Parameters
Min.
Max.
1.8
Unit
Notes
T
stab
Clock Stabilization Time
ms
9
Average Period (variation from ideal period), non-SSC
Average Period (variation from ideal period), SSC mode
Absolute Minimum Period, non-SSC (from ideal period)
Absolute Minimum Period, SSC mode
Rise and Fall Time (between 0.175V to 0.525V)
Rise and Fall Time Variation
-0.3
-0.3
-2.5
+0.3
+0.53
T
period
%
4,5,8
T
abs_min
T
- 0.125
ns
ps
period
T
/ T
175
700
75
2,4,7,21
4,7,18
rise
fall
ΔT / ΔT
rise
fall
Edge_rate
Edge rate
0.5
660
-150
200
Calc
2.0
850
V/ns
V
high
Voltage High (typ. = 0.7V)
4,7,10,11
V
low
Voltage Low (typ. = 0.0V)
V
Absolute Crossing Point Voltages
Relative Crossing Point Voltages
Total Variation of (Vx) Vcross over all edges
Cycle to Cycle Jitter
550
Calc
140
mV
1,3,4,7,14
4,6,7,14
4,7,15
x_abs
V
x_rel
Total ΔV
x
T
ccjitter
50
ps
%
4,8,20,22
4,8,21
T
Duty Cycle
45
55
dc
V
Overshoot Voltage
Voh + 0.3
-0.3
4,7,12
ovs
V
uds
Undershoot Voltage
4,7,13
V
Ringback Voltage, Non SSC
0.2
V
4,7
23
rb
Ringback Voltage, SSC mode
Additive RMS phase jitter
Vx-0.2
Vx+0.2
0.7
T
jadd
ps
PS8898A
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07-0151
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PI6C21900S
1:19 Geared Differential Buffer for PCI-Express
Differential AC Characteristics (V = 3.3±5%, V
= 3.3 ±5%, SSC=-0.5%, continued)
DD
DD_A
Notes:
1. Instantenous voltage crossing point where "rising edge CLK" = "falling edge CLK#"
2. Measured from Vol = 0.175 V to Voh = 0.525 V. Only valid for Rising clock and Falling clock#. Signal must be monotonic through the Vol to
Voh region for Trise and Tfall.
3. Total variation from the lowest to the highest crossing point, on both differential rising and falling edges
4. Test configuration is Rs = 33.2 Ohm, Rp = 49.9 Ohm, and 2pF.
5. The average period over any 1 ꢀs period of time must be greater than the minimum and less than the maximum specified period
6. Vx_rel_min = 0.25 + 0.5 * (Vh_avg - 0.70); Vx_rel_max = 0.55 - 0.5*(Vh_avg - 0.70)
7. Single ended waveform measurement
8. Differential waveform measurement
9. Measured from: (i) power supply ramp up, or (ii) valid CLK clock input; to stable output clock (PLL is locked)
10. Vhigh = Statistical Average High value from the oscilloscope Vhigh Math function
11. Vlow = Statistical Average Low value from the oscilloscope Vlow Math function
12. Overshoot = Absolute Maximum Voltage
13. Undershoot = Absolute Minimum Voltage
14. Crossing Point must simultaneously meet absolute and relative crossing point specifications
15. ∆Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK#. This is the maximum allowed vari-
ance in Vcross for any particular system
16. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 100,000,000 Hz, 133,333,333 Hz,
166,666,666 Hz and 200,000,000 Hz
17. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz,
166,250,000 Hz and 199,500,000 Hz
18. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
19. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the falling edge rate (average)
of clock#
20. Measured in PLL mode; in Bypass mode, jitter is additive
21. Measured at < 270 mHz
22. Measure with M1•
23. Additive jitter is calculated from input and output RMS phase jitter by using PCIe GenII filter. (Tjadd = √(output jitter)2-(input jitter)2
Configuration Test Load Board Termination
Clock
TLA
PI6C21200
Clock#
TLB
2pF
5%
2pF
5%
Figure 4. Configuration test load board termination
Note: TLA and TLB are 3” transmission lines.
PS8898A
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PI6C21900S
1:19 Geared Differential Buffer for PCI-Express
Packaging Mechanical: 72-lead, TQFN (ZD)
ꢄꢂꢋꢅ 2%&ꢂ
0IN ꢌꢀ
#ORNER
0IN ꢌꢀ
#ORNER
!
ꢀꢅꢂꢅꢅ Òꢅꢂꢀꢅ
ꢅꢂꢋꢅ "3#ꢂ
ꢅꢂꢉꢅ Òꢅꢂꢅꢋ
#
ꢅꢂꢀꢋ
#
ꢅꢍꢅꢂꢅꢋ
ꢅꢂꢉꢅ 2%&ꢂ
ꢅꢂꢄꢅ Òꢅꢂꢅꢎ
%
"
ꢅꢂꢋꢅ "3#ꢂ
ꢅꢂꢉꢋ ꢇꢈꢉ8ꢊ
TYPE I
TYPE II
6.00 ± 0.05
6.00 ± 0.05
6.05
D
E
6.30 ± 0.05
6.30 ± 0.05
6.35
D1
E1
6.35
6.05
.OTESꢀ
%ꢀ
ꢀꢊ !LL DIMENSIONS ARE IN MILLIMETERSꢂ !NGLES IN $EGREESꢂ
ꢉꢊ 2EF *%$%#ꢏ -/ꢍꢉꢉꢅ)ꢐ6..$
ꢆꢊ 4HERMAL 6IA $IAMETERꢂ 2ECOMMENDED ꢅꢂꢉ^ꢅꢂꢆꢆMM
ꢎꢊ 4HERMAL 6IA 0ITCHꢂ 2ECOMMENDED ꢀꢂꢉꢈMM
ꢋꢊ "ILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS
THE TERMINALS
DATE: 03/27/06
ꢅꢂꢃꢆ ꢇꢈꢉ8ꢊ
www.pericom.com
ꢁꢂꢃꢄ
DESCRIPTION: 72-Contact Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZD (ZD72)
2ECOMMENDED ,AND 0ATTERN
REVISION: C
DOCUMENT CONTROL #: PD-2037
Ordering Information:
Ordering Code
Packaging Code
ZD
Package Type
72-Lead TQFN, Pb-Free and Green
PI6C21900SZDE
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PS8898A
06/22/07
07-0151
19
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