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PI6C2408-4WE [PERICOM]

Zero-Delay Clock Buffer; 零延迟时钟缓冲器
PI6C2408-4WE
型号： PI6C2408-4WE
厂家： PERICOM SEMICONDUCTOR CORPORATION    PERICOM SEMICONDUCTOR CORPORATION
描述：

Zero-Delay Clock Buffer
零延迟时钟缓冲器

时钟
文件： 总10页 (文件大小：200K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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PI6C2408  
Zero-Delay Clock Buffer  
Features  
• Maximumratedfrequency:140MHz  
• Lowcycle-to-cyclejitter  
• Input to output delay, less than 150ps  
• External feedback pin allows outputs to be synchronized  
to the clock input  
• 5V tolerant input*  
• Operatesat3.3VVDD  
• Test mode allows bypass of the PLL for system testing  
purposes (e.g., IBIS measurements)  
Description  
The PI6C2408 is a PLL-based, zero-delay buffer, with the ability  
to distribute eight outputs of up to 140 MHz at 3.3 V. Two banks of  
four outputs exist, and, depending on product option ordered, can  
supply either reference frequency, prescaled half frequency, or  
multiplied2xor4xinputclockfrequencies. ThePI6C2408familyhas  
a power-sparing feature: when input SEL2 is 0, the component will  
3-state one or both banks of outputs depending on the state of input  
SEL1. A PLL bypass test mode also exists. This product line is  
available in high-drive and industrial environment versions.  
An external feedback pin is used to synchronize the outputs to the  
input; the relationship between loading of this signal and the other  
outputs determines the input-output delay.  
The PI6C2408 is characterized for both commercial and industrial  
operation.  
• Clock frequency multipliers ½x to 4x dependent on option  
• Packaging(Pb-freeandGreenavailable):  
-16-pin,150-milSOIC (W)  
-16-pin173-milTSSOP (L)  
* FB_IN and CLKIN must reference the same voltage thresh-  
olds for the PLL to deliver zero delay skewing  
BlockDiagram  
PinConfiguration  
FB_IN  
CLKIN  
÷2  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
OUTA1  
OUTA2  
16  
15 OUTA4  
1
2
3
4
5
6
7
8
FB_IN  
Option (-3, -4)  
14  
13  
12  
11  
10  
9
OUTA3  
SEL1  
SEL2  
Decode  
Logic  
16-Pin  
W,L  
V
V
GND  
DD  
DD  
GND  
OUTB1  
OUTB2  
SEL2  
÷2  
OUTB4  
OUTB3  
SEL1  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
Option (-2, -3)  
PI6C2408 (-1, -1H, -2, -3, -4)  
FB_IN  
PLL  
OUTA1  
OUTA2  
OUTA3  
OUTA4  
MUX  
CLKIN  
SEL2  
SEL1  
Decode  
Logic  
÷2  
MUX  
PI6C2408-6  
OUTB1  
OUTB2  
OUTB3  
OUTB4  
PS8589E  
09/15/04  
1
PI6C2408  
Zero Delay Clock Buffer  
Input Select Decoding for PI6C2408 (-1, -1H,-4)  
SEL2  
SEL1  
OUTA [1-4]  
3-State  
PLL  
OUTB [1-4]  
3-State  
3-State  
CLKIN  
PLL  
Output Source  
PLL  
OFF  
ON  
0
0
1
1
0
1
0
1
PLL  
PLL  
CLKIN  
PLL  
CLKIN  
PLL  
OFF  
ON  
Input Select Decoding for PI6C2408 (-2,-3)  
SEL2  
SEL1  
OUTA [1-4]  
3-State  
PLL  
OUTB [1-4]  
3-State  
Output Source  
PLL  
PLL  
OFF  
ON  
0
0
1
1
0
1
0
1
3-State  
PLL  
CLKIN  
PLL  
CLKIN/2  
PLL  
CLKIN  
PLL  
OFF  
ON  
Input Select Decoding for PI6C2408-6  
SEL2  
SEL1  
OUTA [1-4]  
OUTB [1-4]  
3-State  
Output Source  
PLL  
PLL  
OFF  
OFF  
ON  
0
0
1
1
0
1
0
1
3-State  
CLKIN  
PLL  
CLKIN/2  
PLL  
CLKIN  
PLL  
PLL  
PLL/2  
PLL  
ON  
PI6C2408Configurations  
Device  
Feedback From  
OUTA [1-4] Frequency  
CLKIN  
OUTB [1-4] Frequency  
CLKIN  
PI6C2408-1  
OUTA or OUTB  
OUTA or OUTB  
OUTA  
PI6C2408-1H  
PI6C2408-2  
CLKIN  
CLKIN  
CLKIN  
CLKIN/2  
PI6C2408-2  
OUTB  
2X CLKIN  
2X CLKIN  
4X CLKIN  
2X CLKIN  
CLKIN  
CLKIN  
CLKIN or CLKIN(1 )  
PI6C2408-3  
OUTA  
PI6C2408-3  
OUTB  
2X CLKIN  
PI6C2408-4  
OUTA or OUTB  
OUTA  
2XCLKIN  
PI6C2408-6  
CLKIN or CLKIN/2  
CLKIN  
PI6C2408-6  
OUTB  
CLKIN or 2X CLKIN  
Note:  
1. Outputphaseisindeterminant(0°or180°fromCLKIN)  
PS8589E  
09/15/04  
2
PI6C2408  
Zero Delay Clock Buffer  
PinDescription  
Pin  
Signal  
Description  
1
CLKIN  
Input clock reference frequency (weak pull-down)  
Clock output, Bank A (weak pull-down)  
3.3V supply  
2, 3, 14, 15  
OUTA[1-4]  
VDD  
4, 13  
5, 12  
GND  
Ground  
6, 7, 10 ,11  
OUTB[1-4]  
SEL2  
Clock output, Bank B (weak pull-down)  
Select input, bit 2 (weak pull-up)  
Select input, bit 1 (weak pull-up)  
PLL feedback input  
8
9
SEL1  
16  
FB_IN  
ZeroDelayandSkewControl  
CLKINInputtoOutputBankDelayvs.DifferenceinLoadingbetweenFB_INpinandOUTA/OUTBpins  
800  
600  
400  
200  
0
0
5
10  
15  
20  
25  
-25  
-20  
-15  
-10  
-5  
-200  
-400  
PI6C2408-1H  
-600  
-800  
PI6C2408-1,2,3,4,6  
-900  
-1000  
Output Load Difference: FB_IN Load - OUTA/OUTB Load (pF)  
The relationship between loading of the FB_IN signal and other outputs determines the input-output delay. Zero delay is achieved when  
all outputs, including feedback, are loaded equally.  
MaximumRatings  
Supply Voltage to Ground Potential ............................................................................................................................. –0.5Vto+7.0V  
DCInputVoltage(ExceptCLKIN) ........................................................................................................................ –0.5VtoV +0.5V  
DD  
DCInputVoltageCLKIN ......................................................................................................................................................–0.5to7V  
Storage Temperature................................................................................................................................................... –65ºCto+150ºC  
MaximumSolderingTemperature(10seconds)........................................................................................................................... 260ºC  
Junction Temperature .................................................................................................................................................................. 150ºC  
StaticDischargeVoltage(perMIL-STD-883,Method3015) .................................................................................................... >2000V  
PS8589E  
09/15/04  
3
PI6C2408  
Zero Delay Clock Buffer  
OperatingConditions(VCC =3.3V±0.3V)  
Parameter  
Description  
Min.  
3.0  
0
Max.  
3.6  
70  
85  
30  
Units  
V
VDD  
Supply Voltage  
Commerical Operating Temperature  
Industrial Operating Temperature  
Load Capacitance, below 100 MHz  
Load Capacitance, from 100 MHz to 140MHz  
Input Capacitance  
TA  
ºC  
pF  
–40  
CL  
15  
7
CIN  
DCElectricalCharacteristicsforIndustrialTemperatureDevices  
Parameter  
Description  
Input LOW Voltage  
Input HIGH Voltage  
Input LOW Current  
Input HIGH Current  
Output LOW Voltage  
Output HIGH Voltage  
Test Conditions  
Min.  
Max.  
Units  
VIL  
0.8  
V
VIH  
IIL  
2.0  
VIN = 0V  
50.0  
100.0  
0.4  
µA  
IIH  
VIN = VDD  
VOL  
VOH  
IOL = 8mA (–1, –2, –3,–4, –6); IOL = 12mA (–1H)  
IOH = –8mA (–1, –2, –3,–4, –6); IOH = –12mA (–1H)  
V
2.4  
IDD (PD mode) Pwr Dwn Supply Current SEL1 = 0 (–1, –2, –3, –4, –1H); SEL2 = 0 (–6)  
25.0  
54.0  
µA  
IDD  
Supply Current  
Unloaded outputs 100 MHz,  
Select inputs at VDD or GND  
70.0 (–1H)  
39.0  
mA  
Unloaded outputs 66 MHz, CLKIN, except (–1H)  
Unloaded outputs 33MHz, CLKIN, except (–1H)  
20.0  
PS8589E  
09/15/04  
4
PI6C2408  
Zero Delay Clock Buffer  
ACElecricalCharacteristicsforIndustrialTemperatureDevices  
Parameters  
Name  
Test Conditions  
Min. Typ. Max. Units  
30pF load  
15pF load  
100  
140  
FO  
Output Frequency  
10.0  
MHz  
tDC  
Duty Cycle(1)  
(–1, –2, –3, –4, –6)  
Measured at VDD/2, FOUT <66.67MHz 30pF load  
Measured at VDD/2, FOUT <140 MHz 15pF load  
Measured at VDD/2, FOUT <45 MHz 30pF load  
40.0  
45.0  
60.0  
50  
55.0  
%
Duty Cycle(1) (–1H)  
Measured at VDD/2, FOUT <66.67MHz 30pF load 45.0  
Measured at VDD/2, FOUT <140 MHz 15pF load  
Measured at VDD/2, FOUT <45MHz 30pF load  
Measured between 0.8V and 2.0V, 30pF load  
Measured between 0.8V and 2.0V, 15pF load  
Measured between 0.8V and 2.0V, 30pF load  
Measured between 0.8V and 2.0V, 30pF load  
Measured between 0.8V and 2.0V, 15pF load  
Measured between 0.8V and 2.0V, 30pF load  
All outputs equally loaded  
40.0  
45.0  
60.0  
55.0  
2.2  
1.50  
1.50  
2.50  
1.50  
1.25  
Rise Time(1) (–1, –2, –3, –4,)  
tR  
Rise Time(1) (–1H)  
Fall Time(1) (–1, –2, –3, –4,)  
ns  
ps  
tF  
Fall Time(1) (–1H)  
tSK(O)  
Output to Output Skew within  
same Bank (–1,–2,–3,–4,–6)(1)  
200  
OUTA to OUTB Skew(1)  
(–1,–1H,–4)  
OUTA to OUTB Skew(1)  
(–2,–3,–6)  
400  
t0  
Measured at VDD/2  
Delay, CLKIN Rising Edge  
0
0
±150  
500  
to FB_IN Rising Edge(1)  
tSK(D)  
tSLEW  
Device-to-Device Skew(1)  
Output Slew Rate(1)  
Measured at VDD/2 on FB_IN pins of devices  
Measured between 0.8V & 2.0V on –1H device  
using Test Crt #2  
Measured at 66.67 MHz, loaded 30pF load  
Measured at 140 MHz, loaded 15pF load  
1
V/ns  
ps  
tJIT  
Cycle-to-Cycle Jitter(1)  
(–1,–1H,–4)  
Cycle-to-Cycle Jitter(1)  
(–2,–3,–6)  
PLL Lock Time(1)  
200  
100  
Measured at 66.67 MHz, loaded 30pF load  
400  
tLOCK  
Stable power supply, valid clocks  
presented on CLKIN and FB_IN pins  
1.0  
ms  
Notes:  
1. See Switching Waveforms on page 7.  
PS8589E  
09/15/04  
5
PI6C2408  
Zero Delay Clock Buffer  
DCElectricalCharacteristicsforCommercialTemperatureDevices  
Parameter  
Description  
Input LOW Voltage  
Input HIGH Voltage  
Input LOW Current  
Input HIGH Current  
Output LOW Voltage  
Output HIGH Voltage  
Test Conditions  
Min. Max. Units  
VIL  
0.8  
V
VIH  
IIL  
IIH  
VOL  
VOH  
2.0  
VIN = 0V  
VIN = VDD  
50  
µA  
100  
IOL = 8mA (–1, –2, –3,–4, –6); IOL = 12mA (–1H)  
IOH = –8mA (–1, –2, –3,–4, –6); IOH = –12mA (–1H)  
0.4  
V
2.4  
IDD (PD mode) Power Down Supply Current SEL1 = 0 (-1,-2,-3,-4,-1H); SEL2 = 0 (-6)  
12  
39  
54  
µA  
IDD  
IDD  
Supply Current  
Supply Current  
Unloaded outputs, 66.67 MHz, Select inputs at VDD or GND  
Unloaded outputs 100 MHz Select Inputs @ VDD or GND  
mA  
ACElectrialCharacteristicsforCommercialTemperatureDevice  
Parameters  
Name  
Test Conditions  
Min. Typ. Max. Units  
30pF load  
15pF load  
10  
100  
140  
55  
FO  
Output Frequency  
MHz  
%
Duty Cycle(1) (–1H)  
Measured at VDD/2, for high drive output  
Measured at VDD/2, for normal drive output  
45  
40  
50  
50  
tDC  
Duty Cycle (–1, –2, –3, –4, –6)  
Rise Time(1) @30pF  
Rise Time(1) @15pF  
Rise Time(1) @30pF (–1H)  
Fall Time(1) @30pF  
Fall Time(1) @15pF  
Fall Time(1) @30pF (–1H)  
Output to Output Skew(1) within same  
bank (–1,–1H,–2,–3,–4,–6)  
60  
tR  
2.2  
1.5  
1.5  
2.2  
1.5  
1.25  
Measured between 0.8V and 2.0V  
ns  
ps  
tF  
tSK(O)  
All outputs equally loaded, VDD/2  
200  
OUTA to OUTB Skew(1) (–1,–1H,–4) All outputs equally loaded, VDD/2  
200  
400  
OUTA to OUTB Skew(1) (–2,–3,–6)  
All outputs equally loaded, VDD/2  
t0  
Input to Output Delay, CLKIN  
Measured at VDD/2  
0
0
±150  
500  
Rising Edge to FB_IN Rising Edge(1)  
tSK(D)  
tSLEW  
Device to Device Skew(1)  
Output Slew Rate(1)  
Measured at VDD/2 on FB_IN pins of devices  
Measured between 0.8V and 2.0V on –1H  
device using Test Circuit #2  
Measured at 66.67 MHz, loaded 30pF outputs  
Measured at 140 MHz, loaded 15pF outputs  
Measured at 66.7 MHz, loaded 30pF outputs  
1
V/ns  
ps  
tJIT  
Cycle-to-Cycle Jitter (1)(–1,–1H,–4)  
200  
100  
400  
Cycle-to-Cycle Jitter(1) (–2,–3,–6)  
PLL Lock Time(1)  
tLOCK  
Stable power supply, valid clocks  
presented on CLKIN and FB_IN pins  
1.0  
ms  
Notes:  
1. See Switching Waveforms on page 7.  
PS8589E  
09/15/04  
6
PI6C2408  
Zero Delay Clock Buffer  
SwitchingWaveforms  
Duty Cycle Timing  
t
t
LOW  
HIGH  
/2  
t
HIGH  
t
t
DC =  
V
/2  
DD  
V
V
/2  
DD  
t
+
LOW  
DD  
HIGH  
All Outputs Rise/Fall Time  
3.3V  
2.0V  
0.8V  
2.0V  
0.8V  
OUTPUT  
0V  
t
t
R
F
Output-Output Skew  
Device-Device Skew  
V
/2  
DD  
OUTPUT  
OUTPUT  
V
/2  
DD  
t
SK(O)  
V
/2  
DD  
OUTPUT Device 1  
OUTPUT Device 2  
V
/2  
DD  
t
SK(D)  
Input-Output Propagation Delay  
V
/2  
DD  
INPUT  
FB_IN  
V
/2  
DD  
t
0
0.1µF  
0.1µF  
0.1µF  
VDD  
OUTPUTS  
VDD  
OUTPUTS  
1k-ohm  
1k-ohm  
CLK out  
CLK out  
10pF  
C
LOAD  
VDD  
VDD  
GND  
0.1µF  
GND  
GND  
GND  
PS8589E  
09/15/04  
7
PI6C2408  
Zero Delay Clock Buffer  
16-PinSOIC(W)Package  
16  
3.78  
3.99  
.149  
.157  
0.25  
0.50  
.0099  
.0196  
x 45˚  
1
0.19  
0.25  
.0075  
.0098  
0-8˚  
.386  
.393  
9.80  
10.00  
0.41  
1.27  
.016  
.050  
1.35  
1.75  
.053  
.068  
.0155  
.0260  
.2284  
.2440  
5.80  
6.20  
0.393  
0.660  
SEATING PLANE  
REF  
0.10  
0.25  
.0040  
.0098  
.050  
.013  
BSC  
.020  
1.27  
0.330  
0.508  
X.XX  
X.XX  
DENOTES DIMENSIONS  
IN MILLIMETERS  
16-PinTSSOP(L)Package  
16  
.169  
.177  
4.3  
4.5  
1
0.09  
0.20  
.193  
.201  
.004  
.008  
4.9  
5.1  
.047  
0.45 .018  
0.75 .030  
max.  
1.20  
SEATING  
PLANE  
.252  
BSC  
6.4  
.002  
.006  
0.05  
0.15  
.0256  
BSC  
.007  
.012  
X.XX DENOTES CONTROLLING  
X.XX DIMENSIONS IN MILLIMETERS  
0.65  
0.19  
0.30  
Note:Controllingdimensions inmillimeters.Ref:JEDECMS-012AC  
PS8589E  
09/15/04  
8
PI6C2408  
Zero Delay Clock Buffer  
OrderingInformation (CommercialTemperatureDevice)  
OrderingCode  
PI6C2408-1W  
PI6C2408-1WE  
PI6C2408-1HW  
PI6C2408-1HWE  
PI6C2408-2W  
PI6C2408-2WE  
PI6C2408-3W  
PI6C2408-3WE  
PI6C2408-4W  
PI6C2408-4WE  
PI6C2408-6W  
PI6C2408-6WE  
PI6C2408-1WE  
PI6C2408-1HWE  
PI6C2408-1L  
Package  
W
W
W
W
W
W
W
W
W
W
W
W
W
W
L
Description  
OperatingRange  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
Pb-free&Green16-pin150-milSOIC  
Pb-free&Green16-pin150-milSOIC  
16-pin173-milTSSOP  
PI6C2408-1LE  
PI6C2408-1HL  
PI6C2408-1HLE  
PI6C2408-3L  
L
L
L
L
Pb-free&Green,16-pin173-milTSSOP  
16-pin173-milTSSOP  
Pb-free&Green,16-pin173-milTSSOP  
16-pin173-milTSSOP  
PI6C2408-3LE  
PI6C2408-4L  
L
L
Pb-free&Green,16-pin173-milTSSOP  
16-pin173-milTSSOP  
PI6c2408-4LE  
PI6C2408-1LE  
PI6C2408-1HLE  
L
L
L
Pb-free&Green,16-pin173-milTSSOP  
Pb-free&Green16-pin173-milTSSOP  
Pb-free&Green16-pin173-milTSSOP  
PS8589E  
09/15/04  
9
PI6C2408  
Zero Delay Clock Buffer  
OrderingInformation(Industrial TemperatureDevice)  
OrderingCode  
PI6C2408-1WI  
PI6C2408-1WIE  
PI6C2408-1HWI  
PI6C2408-1HWIE  
PI6C2408-2WI  
PI6C2408-2WIE  
PI6C2408-4WI  
PI6C2408-4WIE  
PI6C2408-6WI  
PI6C2408-6WIE  
PI6C2408-1LI  
Package  
Description  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin150-milSOIC  
Pb-free&Green,16-pin150-milSOIC  
16-pin173-milTSSOP  
OperatingRange  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
Industrial  
W
W
W
W
W
W
W
W
W
W
L
PI6C2408-1LIE  
PI6C2408-6LI  
L
L
Pb-free&Green,16-pin173-milTSSOP  
16-pin173-milTSSOP  
PI6C2408-6LIE  
L
Pb-free&Green,16-pin173-milTSSOP  
Notes:  
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/  
PericomSemiconductorCorporation • 1-800-435-2336 • www.pericom.com  
10  
PS8589E  
09/15/04  

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 PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, GREEN, SOIC-16
PERICOM

PI6C2408-4WIEX

 PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-16
PERICOM

PI6C2408-4WX

 PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-16
PERICOM

PI6C2408-6

 Clock IC | 4+4 Output Zero-Delay Clock Driver (Bank A=2Xref or REF. Bank B = Ref). 10 to 134 MHz
ETC

PI6C2408-6I

 Clock IC | 4+4 Output Zero-Delay Clock Driver (Bank A=2Xref or REF. Bank B = Ref). 10 to 134 MHz. Industrial Temp. Operation
ETC

PI6C2408-6LIEX

 PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.173 INCH, TSSOP-16
PERICOM

PI6C2408-6LX

 PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.173 INCH, TSSOP-16
PERICOM

PI6C2408-6W

 Zero-Delay Clock Buffer
PERICOM

PI6C2408-6WE

 Zero-Delay Clock Buffer
PERICOM

PI6C2408-6WEX

 PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-16
PERICOM
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