PI6C2502W [PERICOM]
SINGLE CLOCK DRIVER|CMOS|SOP|8PIN|PLASTIC ; 单时钟驱动器| CMOS |专科| 8PIN |塑料\n
| 型号： | PI6C2502W |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | SINGLE CLOCK DRIVER|CMOS|SOP|8PIN|PLASTIC
|
| 文件： | 总6页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C2502
Phase-Locked Loop Clock Driver
Product Description
ProductFeatures
The PI6C2502 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback FB_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
• High-PerformancePhase-Locked-LoopClockDistribution
forNetworking,
• Synchronous DRAM modules for server/workstation/
PC applications
Application
• Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends the use of a zero-delay buffer
and an eighteen output non-zero-delay buffer. As shown in Figure
1, this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
• Zero Input-to-Output delay
• Lowjitter:Cycle-to-Cyclejitter±100psmax.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operatesat3.3VVCC
• Wide range of Clock Frequencies up to 80 MHz
• Package:Plastic8-pinSOICPackage(W)
LogicBlockDiagram
ProductPinConfiguration
8-Pin
W
Figure1.ThisCombinationProvidesZero-DelayBetweenthe
Reference Clocks Signal and 17 Outputs
PS8382B
03/20/02
1
PI6C2502
Phase-Locked Loop Clock Driver
PinFunctions
Pin Name
Pin Number
Type
Description
CLK_IN
FB_IN
8
5
I
I
Reference Clock input. CLK_IN allows spread spectrum clock input.
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Feedback output FB_OUT is dedicated for external feedback.
FB_OUT has an embedded series-damping resistor of the same value
as the clock outputs CLK_OUT.
FB_OUT
CLK_OUT
AVCC
2
3
7
O
O
Clock outputs. These outputs provide low-skew copies of CLK_IN.
Each output has an embedded series-damping resistor.
Analog power supply. AVCC can be also used to bypass the PLL for
test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK_IN is buffered directly to the device outputs.
Power
AGND
VCC
1
4
6
Ground
Power
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply.
Ground.
GND
DC Specifications (Absolute maximum ratings over operating free-air temperature range)
Symbol
Parameter
Min.
Max.
Units
V
Input voltage range
Output voltage range
DC output current
I
0.5
V
CC
+0.5
V
V
O
I
100
mA
W
O_DC
o
Power
Maximum power dissipation at T = 55 C in still air
1.0
A
o
T
STG
Storage temperature
65
150
C
Note: Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device.
Parameter
Test Conditions
V
CC
Min.
Typ.
Max.
Units
(1)
I
V = V or GND; I = 0
3.6V
3.3V
10
µA
CC
I
CC
O
C
V = V or GND
4
6
I
I
CC
pF
C
V =V or GND
O CC
O
Note: 1. Continuous Output Current
PS8382B
03/20/02
2
PI6C2502
Phase-Locked Loop Clock Driver
Recommended Operating Conditions
Symbol
Parameter
Min.
3.0
Max.
Units
V
VCC
VIH
VIL
VI
Supply voltage
3.6
High level input voltage
Low level input voltage
Input voltage
2.0
0.8
VCC
70
0
0
TA
Operating free-air temperature
ºC
ElectricalCharacteristics
(Over recommended operating free-air temperature range Pull Up/Down Currents, VCC = 3.0V)
Symbol
Parameter
Pull-up current
Condition
VOUT = 2.4V
VOUT = 2.0V
VOUT = 0.8V
VOUT = 0.55V
Min.
Max.
Units
−18
−30
IOH
mA
25
17
IOL
Pull-down current
ACSpecificationsTimingRequirements
(Over recommended ranges of supply voltage and operating free-air temperature)
Symbol
Parameter
Min.
25
Max.
80
Units
F
CLK
CYI
Clock frequency
MHz
%
D
Input clock duty cycle
40
60
Stabilization Time after power up
1
ms
SwitchingCharacteristics
(Over recommended ranges of supply voltage and operating free-air temperature, CL=30pF)
V
CC = 3.3V ±0.3V, 0-70°C
Units
Parameter
From (Input)
To (Output)
Min.
Typ.
Max.
tphase error without jitter
Jitter, cycle-to-cycle
CLK_IN↑ at 100MHz and 66MHz
FB_IN↑
150
100
+150
ps
At 100 MHz and 66 MHz
CLK_OUT
+100
Skew at 100 MHz
and 66 MHz
CLK_OUT
or FB_OUT
CLK_OUT or FB_OUT
200
55
Duty cycle
45
%
ns
CLK_OUT
or FB_OUT
tr, rise-time, 0.4V to 2.0V
tf, fall-time, 2.0V to 0.4V
1.0
1.1
Note: These switching parameters are guaranteed by design.
PS8382B
03/20/02
3
PI6C2502
Phase-Locked Loop Clock Driver
Application Note
Layout and Schematic Guidelines
Introduction
This location minimizes the total loops needed between the outgo-
ing and returning paths. That is why it is important to separate the
signal layers by ground planes if possible. Also avoid totally
cutting part of the ground plane to be used for a signals path. That
is totally unacceptable, because it will increase crosstalk consider-
ably and does not provide a clean return to those signals. Also use
lower trace impedance because it lowers undershoot and over-
shoot. AlwaysuseFR-4materialforboardfabrication. Use4-layer
stack-up arrangement. Make sure you have a signal layer that is
followed by the ground layer, then a power layer, and finally the
second signal layer. Please see Figure 1 below.
Because of todays high-speed design demands, board designers
must have extensive knowledge concerning transmission line
effect, EMI, and crosstalk. They also need to understand board
materials, signal and power stacking, connectors, cables, vias, and
trace dimensions. Pericom Semiconductor Corporation offers an
extensive line of high-speed clock products for desktop, notebook,
set top boxes, information device, servers, and workstations. To
make high-speed chips function properly, a designer needs to rely
on accurate schematics and layout guidelines.
This application note focuses on Pericoms PI6C2502 Zero- Delay
Clock Buffer, presenting schematics and layout guidelines for the
chip. Also listed are some decoupling guidelines that are important
for this chips varied applications.
Primary Signal
Z = 60 Ohms
Layer (½ oz. cu.)
5 mils
47 mils
5 mils
PREPREG
CORE
Ground Plane
(1 oz. cu.)
DecouplingCapacitors
Every printed circuit board needs large bypass capacitors to
balance the inductance of the power-supply wiring. These capaci-
tors have some lead inductance that increase as the frequency goes
higher, which is why it is very important to place the capacitors as
close as possible to the VCC and Ground Pins on the Chip.
Power Plane
(1 oz. cu.)
PREPREG
Secondary Signal
Layer (½ oz. cu.)
Z = 60 Ohms
Total Board Thickness = 62.6
To reduce the series lead inductance effect, avoid the following:
Figure1:Four-LayerBoardStack-up
1.Long traces larger than 00.1 inch between capacitor pad and
2.Use of capacitors other than surface mount
via
Clockroutingandspacing
3.Via holes less than 00.35-inch diameter
To minimize crosstalk on the clock signals, use a minimum of
0.014-inch spacing between clock traces and others. If you have to
use serpentine to match trace lengths on similar chips, make sure
thatyouhaveatleast0.018-inchspacingforserpentines. Pleasesee
Figure2below.
Pericomsclocksusehigh-precision,integratedanalogPLLthatcan
be effected by the power supply and ground pins. Noise on these
two pins can dramatically increase skew and output jitter.
Tominimizetheseproblems,connecta4.7µF,a220nF,anda2.2nF
capacitor to the digital supply pin. Also use one 4.7µF , one 220nF,
andone2.2nFcapacitorontheanalogsupplypin.Connecttheother
side to the analog ground pin.
Place a10µFcapacitorfromthemainpowerislandtothepowerplane
that is supplied to the clock chip.
Use high-quality, low ESR, ceramic surface-mount capacitors.
Clock
0.014"
0.018"
Stacking
At low speeds, currents follow the least resistance path, but at high
speeds current follows the least inductance path. The lowest
inductance return path lies directly under the signal conductor.
Figure 2: Clock Trace Spacing Guidelines
PS8382B
03/20/02
4
PI6C2502
Phase-Locked Loop Clock Driver
SchematicDrawing
INPUT_CLOCK
25-150 MHZ
PI6C2502
AGND
CLK_IN
AVCC
1.5µH
.002µF
.22µF
Board
AVCC
FB_OUT
4.7µF
GND
CLK_OUT
VCC
3.3V
.22µF
Power
FB_IN
1.5µH
4.7µF
Supply
.002µF
5-12pF
Feedback
Capacitor
Decoupling Capacitors
Series Terminating Resistor
ClockChipLayout
PI6C2502
AVCC Island for PI6C2510
CLK_IN
AGND
AGND
C
C
C
L
AVCC
FB_OUT
AGND
AGND
R
CLK_OUT
GND
C
C
C
GND
FB_IN
L
CFB
VCC
GND
Use Wider Traces for Ground and Power
(0.034-inch width, 0.1-inch pitch)
Legend:
GND = Via to Digital Ground
AGND = Via to Analog Ground
VCC = Via to 3.3V Digital Power
AVCC = Via to 3.3V Analog Power
R = Termination Resistor 12-32Ω
C = Decoupling Capacitor
L = Inductor
CFB = Feedback Capacitor
PS8382B
03/20/02
5
PI6C2502
Phase-Locked Loop Clock Driver
Package Mechanical Information
Plastic 8-pin SOIC Package
8
3.78
3.99
.149
.157
1
4.80
5.00
.189
.196
0.25
0.50
.0099
.0196
x 45˚
1.35
1.75
.053
.068
.016
.026
REF
0.406
0.660
SEATING PLANE
0-8˚
0.19
0.25
.0075
.0098
0.40 .016
0.10
0.25
.0040
.0098
1.27
.050
.050
BSC
.2284
.2440
5.80
.013
.020
0.330
0.508
1.27
6.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
OrderingInformation
Ordering Code
Package Name
Package Type
Operating Range
PI6C2502W
W8
8-pin 150-mil SOIC
Commercial
Pericom Semiconductor Corporation
2380BeringDrive SanJose,CA951311-800-435-2336 Fax(408)435-1100 http://www.pericom.com
PS8382B
03/20/02
6
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