PI6C410VE [PERICOM]
Clock Generator for Intel PCI-Express Desktop Chipset; 时钟发生器为Intel PCI -Express的台式机芯片组
| 型号： | PI6C410VE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Clock Generator for Intel PCI-Express Desktop Chipset |
| 文件： | 总16页 (文件大小：712K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C410
Clock Generator for Intel PCI-Express Desktop Chipset
Product Features
Product Description
• 14.318 MHz Crystal Input
PI6C410 is a high-speed, low-noise clock generator designed to
work with Intel Desktop PCI-Express Chipset.
Spread Spectrum PLL based clock generator reduce EMI emis-
sion and support a wide range of frequencies.
• Selectable of 100, 133, 166, 200, 266, 333, and 400MHz CPU
Output Frequencies
• SMBus: Power Management Control
• Spread Spectrum support (-0.5% down spread)
Jitter Performance
• < 85ps Cycle to Cycle CPU clock jitter
• < 350ps Cycle to Cycle 48MHz clock jitter
• < 500ps Cycle to Cycle PCI clock jitter
• < 125ps Cycle to Cycle SRC clock jitter
• < 1000ps Cycle to Cycle REF clock jitter
• Packaging (Pb-free & Green available):
-56-Pin SSOP (V)
-56-Pin TSSOP (A)
Output Features
Skew Performance
• Two Pairs of Differential CPU Clocks
• One selectable of CPU/SRC Clock
• Six Pairs of SRC Clocks
• Nine PCI Clocks
• < 100ps Output to output CPU clock skew
• < 500ps Output to output PCI clock skew
• < 250ps Output to output SRC clock skew
• One 48 MHz USB clock
• One REF clock
• One 96 MHz Differential clock
Pin Description
Logic Block Diagram
DOT_96
DOT 96#
XTAL_IN
XTAL
OSC
PLL 2
VDD_PCI
VSS_PCI
PCI_3
PCI_4
PCI_5
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI_2
PCI_1
PCI_0
FS_C / TEST_SEL
REF
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SDA
SCL
VSS_CPU
CPU_0
XTAL_OUT
USB_48
REF
/2
PLL 1
VSS_PCI
VDD_PCI
PCIF_0 / ITP_EN
PCIF_1
PCI [0:5]
PCIF[0:2]
Div
SDA
SCL
SMBus
Logic
9
PCIF_2
VDD_48
USB_48
VSS_48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SRC [1:6]
SRC [1:6]#
Div
Div
FS_A
C
O
N
T
R
O
L
DOT_96
CPU_0#
VDD_CPU
CPU_1
CPU_1#
IREF
DOT_96#
FS_B / TEST_MODE
VTT_PWRGD# / PWRDWN
FS_A
CPU2_ITP / SRC7
CPU2_ITP# / SRC7#
FS_B / TEST_MODE
FS_C / TEST_SEL
CPU[0:1]
CPU[0:1]#
SRC_1
SRC_1#
VDD_SRC
SRC_2
SRC_2#
SRC_3
SRC_3#
SRC_4
SRC_4#
VSS_A
VDD_A
VTT_PWRGD#
/ PWRDWN
CPU2_ITP / SRC7
CPU2_ITP# / SRC7#
VDD_SRC
SRC_6
SRC_6#
SRC_5
PCIF_0 / ITP_EN
SRC_5#
VSS_SRC
VDD_SRC
PS8734A
09/02/04
1
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Pin Description
Pin Name
Type
Output
Pin No
52
Descriptions
REF
3.3V 14.31818MHz output
14.31818MHz crystal input
14.31818MHz crystal output
XTAL_IN
Input
Output
Output
50
49
XTAL_OUT
CPU[0:1] & CPU[0:1]#
40, 41, 43, 44 Differential CPU outputs
19, 20, 22, 23,
SRC[1:6] & SRC[1:6]#
Output
Output
24, 25, 26, 27, Differential Serial Reference Clock outputs
30, 31, 32, 33
Selectable Differential CPU or SRC clock output
CPU2_ITP / SRC_7 &
CPU2_ITP# / SRC_7#
35, 36
ITP_EN = 0 @ Vtt_Pwrgd# assertion = SRC
ITP_EN = 1 @ Vtt_Pwrgd# assertion = CPU
PCIF_0 / ITP_EN
PCIF[1:2]
Input / Output
Output
8
33MHz clock output / CPU2 select when HIGH
33MHz clocks outputs (free running)
9, 10
3, 4, 5, 54, 55,
56
PCI[0:5]
Output
33MHz clocks outputs
USB_48
Output
Output
Input
12
14, 15
18
48MHz clock output
DOT_96 & DOT_96#
FS_A
96MHz differential clock output
3.3V LVTTL inputs for CPU frequency selection
3.3V LVTTL inputs for CPU frequency selection / Test Mode
select: 0 = HiZ, 1 = Ref/N
FS_B / TEST_MODE
Input
16
3.3V LVTTL inputs for CPU frequency selection / Test Mode
select if pulled to 3.3V when Vtt_Pwrgd# is asserted LOW
FS_C / TEST_SEL
IREF
Input
Input
53
39
External resistor connection for internal current reference
3.3V LVTTL Level sensitive strobe used to determine to latch
the FS_A, FS_B/TEST_MODE, FS_C/TEST_SEL and PCIF0/
ITP_EN inputs (active low) / 3.3V LVTTL active high input for
Power Down operation.
VTT_PWRGD# /
PWRDWN
Input
17
SDA
I/O
47
46
SMBus compatible SDATA
SMBus compatible SCLOCK
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
Ground for Outputs
SCL
Input
VDD_PCI
VDD_48
VDD_SRC
VDD_CPU
VDD_REF
VSS_PCI
VSS_48
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Power
Ground
1, 7
11
21, 28, 34
42
48
2, 6
13
Ground for Outputs
VSS_SRC
VSS_CPU
VSS_REF
VDD_A
VSS_A
29
Ground for Outputs
45
Ground for Outputs
51
Ground for Outputs
37
3.3V Power Supply for PLL
Ground for PLL
38
PS8734A
09/02/04
2
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Functionality
Frequency Selection
FS_C
FS_B
FS_A
CPU
SRC
PCIF / PCI
33MHz
33MHz
33MHz
33MHz
33MHz
33MHz
33MHz
33MHz
REF
DOT_96
96MHz
96MHz
96MHz
96MHz
96MHz
96MHz
96MHz
96MHz
USB_48
48MHz
48MHz
48MHz
48MHz
48MHz
48MHz
48MHz
48MHz
Note
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
100MHz
133MHz
166MHz
200MHz
266MHz
333MHz
400MHz
Reserved
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
1
1
1
1
1
1
1
1
Notes:
1. Refer to DC Electrical Characteristics for FS_A, FS_B and FS_C (Vih_FS, Vil_FS) threshold levels
Test Mode Selection
TEST_MODE
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
PCIF / PCI
REF/N
REF
REF
Hi-Z
DOT_96
USB_48
Note
1
0
REF/N
Hi-Z
REF/N
Hi-Z
2
2
Hi-Z
Notes:
2. Test mode will occur where the SMBus Bit 6 of Byte 6 = 1, or FS_C/TEST_SEL is set to logic high level.
PWRDWN Functionality
PCIF /
PWRDWN
CPU
CPU#
Normal
Float
SRC
SRC#
Normal
Float
REF
33MHz 14.318MHz
Low Low
DOT_96 DOT_96# USB_48
PCI
0
1
Normal
Normal
Normal
Normal
Float
48MHz
Low
Iref × 2 or
Iref × 2 or
Iref × 2 or
Float
Float
Float
PS8734A
09/02/04
3
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Serial Data Interface (SMBus)
PI6C410 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
1/0
Data Protocol
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Byte
Count
= N
Data
Byte N
- 1
Start
bit
Register
offset
Data
Byte 0
Stop
bit
Slave Addr
R/W
Ack
Ack
Ack
Ack
…
Ack
Notes:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
Data Byte 0: Control Register
Power Up
Bit
Descriptions
Type
Output(s) Affected
Pin
Source Pin
Condition
0
Reserved
RW
SRC_1 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
1
RW
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
SRC_1
SRC_2
19, 20
22, 23
24, 25
26, 27
30, 31
32, 33
35, 36
NA
NA
NA
NA
NA
NA
NA
SRC_2 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
2
3
4
5
6
7
RW
RW
RW
RW
RW
RW
SRC_3 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_3
SRC_4 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_4
SRC_5 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_5
SRC_6 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_6
CPU_2 / SRC_7 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
CPU_2 / SRC_7
PS8734A
09/02/04
4
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Data Byte 1: Control Register
Power Up
Condition
Bit
Descriptions
Type
RW
Output(s) Affected
Pin
Source Pin
3, 4, 5, 8, 9, 10,
19, 20, 22, 23,
24, 25, 26, 27,
30, 31, 32, 33,
35, 36, 40, 41,
43, 44, 54, 55,
56
Spread Spectrum
1 = On, 0 = Off
CPU[0:2], SRC[1:7],
PCI[0:5], PCIF[0:2]
0
0 = Spread off
NA
CPU_0 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
1
RW
1 = Enabled
1 = Enabled
CPU_0, CPU_0#
CPU_1, CPU_1#
43, 44
40, 41
NA
NA
CPU_1 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
2
3
4
RW
RW
RW
Reserved
REF Output Enable
1 = Enabled, 0 = Disabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
REF
USB_48
52
12
NA
NA
NA
NA
USB_48 Output Enable
1 = Enabled, 0 = Disabled
5
6
7
RW
RW
RW
DOT_96 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
DOT_96 & DOT96#
PCIF_0
14, 15
8
PCIF_0 Output Enable
1 = Enabled, 0 = Disabled
Data Byte 2: Control Register
Power Up
Condition
Bit
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Output(s) Affected
PCIF_1
PCIF_2
PCI_0
Pin
9
Source Pin
NA
PCIF_1 Output Enable
1 = Enabled, 0 = Disabled
0
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
PCIF_2 Output Enable
1 = Enabled, 0 = Disabled
1
10
54
55
56
3
NA
PCI_0 Output Enable
1 = Enabled, 0 = Disabled
2
NA
PCI_1 Output Enable
1 = Enabled, 0 = Disabled
3
PCI_1
NA
PCI _2 Output Enable
1 = Enabled, 0 = Disabled
4
PCI_2
NA
PCI _3 Output Enable
1 = Enabled, 0 = Disabled
5
PCI_3
NA
PCI _4 Output Enable
1 = Enabled, 0 = Disabled
6
PCI_4
4
NA
PCI _5 Output Enable
1 = Enabled, 0 = Disabled
7
PCI_5
5
NA
PS8734A
09/02/04
5
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Data Byte 3: Control Register
Power Up
Condition
Bit
0
Descriptions
Type
RW
Output(s) Affected
Pin
Source Pin
Reserved
SRC_1 Output Control
0 = Free Running
1
RW
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
SRC_1
SRC_2
SRC_3
SRC_4
SRC_5
SRC_6
SRC_7
19, 20
22, 23
24, 25
26, 27
30, 31
32, 33
35, 36
NA
NA
NA
NA
NA
NA
NA
SRC_2 Output Control
0 = Free Running
2
3
4
5
6
7
RW
RW
RW
RW
RW
RW
SRC_3 Output Control
0 = Free Running
SRC_4 Output Control
0 = Free Running
SRC_5 Output Control
0 = Free Running
SRC_6 Output Control
0 = Free Running
SRC_7 Output Control
0 = Free Running
Data Byte 4: Control Register
Power Up
Condition
Bit
Descriptions
Type
RW
RW
RW
RW
RW
RW
Output(s) Affected
CPU_0
Pin
43, 44
40, 41
35, 36
8
Source Pin
NA
CPU_0 Output Control
0 = Free Running
0
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
0 = Free running
CPU_1 Output Control
0 = Free Running
1
CPU_1
NA
CPU_2 Output Control
0 = Free Running
2
CPU_2
NA
PCIF_0 Output Control
0 = Free Running
3
PCIF_0
NA
PCIF_1 Output Control
0 = Free Running
4
PCIF_1
9
NA
PCIF_2 Output Control
0 = Free Running
5
PCIF_2
10
NA
DOT_Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
DOT_96 &
DOT_96#
6
7
RW
RW
14, 15
NA
Reserved
PS8734A
09/02/04
6
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Data Byte 5: Control Register
Power Up
Condition
Bit
Descriptions
Type
RW
RW
RW
Output(s) Affected
CPU_0 & CPU_0#
CPU_1 & CPU_1#
CPU_2 & CPU_2#
Pin
Source Pin
NA
CPU_0 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
0
43, 44
40, 41
35, 36
CPU_1 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
1
NA
CPU_2 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
2
NA
19, 20, 22, 23,
24, 25, 26, 27,
30, 31, 32, 33,
35, 36
SRC_Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
SRC[1:7] &
SRC[1:7]#
3
RW
NA
CPU_0 CPU_Stop drive mode
1 = Hi-Z,
0 = Driven in CPU_Stop
0 = Driven in
CPU_Stop
4
5
6
RW
RW
RW
CPU_0 & CPU_0#
CPU_1 & CPU_1#
CPU_2 & CPU_2#
43, 44
40, 41
35, 36
NA
NA
NA
CPU_1 CPU_Stop drive mode
1 = Hi-Z,
0 = Driven in CPU_Stop
0 = Driven in
CPU_Stop
CPU_2 CPU_Stop drive mode
1 = Hi-Z,
0 = Driven in CPU_Stop
0 = Driven in
CPU_Stop
19, 20, 22, 23,
24, 25, 26, 27,
30, 31, 32, 33,
35, 36
SRC_Stop drive mode
1 = Hi-Z,
0 = Driven in PCI_Stop
0 = Driven in
PCI_Stop
SRC[1:7] &
SRC[1:7]#
7
RW
NA
PS8734A
09/02/04
7
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Data Byte 6: Control Register
Power Up Con-
dition
Bit
Descriptions
Type
Output(s) Affected
Pin
Source Pin
FS_A Reflects the value of the
FS_A pin sampled on power up
0 = FS_A was low during
Vtt_Pwrgd# assertion
Externally
Selected
35, 36, 40, 41,
43, 44
0
R
CPU[0:2]
NA
FS_B Reflects the value of the
FS_B pin sampled on power up
0 = FS_B was low during
Vtt_Pwrgd# assertion
Externally
Selected
35, 36, 40, 41,
43, 44
1
2
R
R
CPU[0:2]
CPU[0:2]
NA
NA
FS_C Reflects the value of the
FS_C pin sampled on power up
0 = FS_C was low during
Vtt_Pwrgd# assertion
Externally
Selected
35, 36, 40, 41,
43, 44
3, 4, 5, 8, 9, 10,
19, 20, 22, 23,
24, 25, 26, 27,
30, 31, 32, 33,
35, 36
PCI_Stop Output Control
0 = Enabled, all stoppable PCI
and SRC clocks are stopped
1 = Disabled
All PCI & SRC
clocks except PCIF
and SRC clocks set to
free-running
3
RW
1 = Disabled
NA
NA
REF Output Drive Strength
0 = 1x, 1 =2x
4
5
6
RW
RW
RW
1 = 2X
REF
52
Reserved
Test Clock Mode Entry Control
0 = Disabled, 1 = REF/N or Hi-Z
0 = Disabled
3, 4, 5, 8, 9, 10,
12, 14, 15, 19,
20, 22, 23, 24,
25, 26, 27, 30,
31, 32, 33, 35,
36, 40, 41, 43,
44, 52, 54, 55,
56
CPU[0:2],
SRC[1:7],
PCI[0:5],
Test Clock Mode
0 = Hi-Z, 1 = REF/N
7
RW
0 = Hi-Z
NA
PCIF[0:2], REF,
USB_48, DOT_96
Data Byte 7: Pericom ID Register
Bit
Descriptions
Type
R
Power Up Condition
Output(s) Affected
Pin
0
0
0
0
0
1
0
1
0
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
1
R
Vendor ID
2
R
3
R
4
R
5
R
Revision Code
6
R
7
R
PS8734A
09/02/04
8
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Power Down (PWRDWN assertion)
PWRDWN
CPU, 133 MHz
CPU#, 133 MHz
SRC, 100 MHz
SRC#, 100 MHz
USB, 48 MHz
DOT, 96 MHz
DOT#, 96 MHz
PCI
REF
Figure 1, Power down sequence
Power Down (PWRDWN de-assertion)
Tstable
< 1.8ms
PWRDWN
CPU, 133 MHz
CPU#, 133 MHz
SRC, 100 MHz
SRC#, 100 MHz
USB, 48 MHz
DOT, 96 MHz
DOT#, 96 MHz
PCI
REF
Tdrive_PwrDwr
< 300us, > 200mV
Figure 2, Power down de-assert sequence
PS8734A
09/02/04
9
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Tristate Specifications
Pwrdwn
Stoppable
Outputs
Running
Non-stop
Outputs
Running
Signal
Pwrdwn Tristate Bit
pin
0
X
0
CPU[0:2], SRC[1:7],
DOT96
1
Driven @ Iref x 2
Tristate
Driven @ Iref x 2
Tristate
1
1
Spread Spectrum Specifications
PI6C410 supports Spread Spectrum clocking and can be enabled and disabled via SMBus control. The maximum Spread Spectrum
Modulation is –0.5% down spread with frequency from 30KHz to 33KHz.
Tperiod
Tperiod
Unit
SSC ON
SSC OFF
Min
Max
2.5133
3.016
3.77
Min
Max
CPU @ 399.000MHz
CPU @ 332.500MHz
CPU @ 266.000MHz
CPU @ 199.500MHz
CPU @ 166.250MHz
CPU @ 133.000MHz
CPU @ 99.750MHz
2.4993
2.9991
3.7489
4.9985
5.9982
7.4978
9.997
CPU @ 400.000MHz
CPU @ 333.333MHz
CPU @ 266.666MHz
CPU @ 200.000MHz
CPU @ 166.666MHz
CPU @ 133.333MHz
CPU @ 100.000MHz
2.4993
2.9991
3.7489
4.9985
5.9982
7.4978
9.997
2.5008
3.0009
3.7511
5.0015
6.0018
7.5023
10.003
5.0266
6.032
7.54
ns
10.0533
SRC @ 99.750MHz
9.997
10.0533
30.1598
SRC @ 100.000MHz
9.997
10.003
30.009
PCIF / PCI @ 33.250MHz
29.991
PCIF / PCI @ 33.333MHz
29.991
Crystal Recommendations
Drive
Max.
Shunt Cap Motional Tolerance Stability Aging
Frequency
Cut
Loading Load Cap
Max.
Cap Max.
Max.
Max.
Max.
14.31818MHz
AT
Parallel 20pF
0.1mW
5pF
0.016pF
35ppm
30ppm
5ppm
Notes:
1. External trim capacitors (Ce) are required by using this formula Ce = 2*CL – (Cs + Ci). Typical Ce = 33pF when Crystal Load = 20pF, Trace
capacitance (Cs) = 2.8pF and XTAL pins capacitance = 4.5pF.
PS8734A
09/02/04
10
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Current-mode output buffer characteristics of CPU, SRC, and DOT
Vdd
(3.3V ± 5%)
Slope ~1/R
o
Ro
lout
Ros
lout
0V
0.85V
Vout = 0.85V Max.
Figure 3. Simplified diagram of a current-mode output buffer
Host Clock Buffer Characteristics
Minimum
Maximum
R
3000 Ω
unspecified
N/A
N/A
O
R
unspecified
850mV
OS
V
OUT
Current Accuracy
Conditions
V = 3.30 ±5%
DD
Configuration
Rref = 475Ω 1%
Iref = 2.32mA
Load
Min.
-12% I
Max.
+12% I
NOMINAL
Nominal test load for given
configuration
I
OUT
NOMINAL
Hot Clock Output Current
Board Target
Trace/Term Z
Reference R,
= V /(3xRr)
Output Current
= 6 x Iref
V
@ Z
OH
I
REF
DD
100 Ω
R
= 475Ω 1%,
= 2.32mA
REF
I
REF
I
0.7V @ 50
OH
(100 Ω differential ≈ 8% coupling ratio)
PS8734A
09/02/04
11
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
VDD_A
VDD
Parameters
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
Input High Voltage
Input Low Voltage
Min.
-0.5
-0.5
Max.
4.6
Units
4.6
V
V
4.6
IH
V
-0.5
-65
IL
Ts
Storage Temperature
ESD Protection
150
°C
V
V
2000
ESD
Notes:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Configuration test load board termination
Rs
33-Ohms
5%
Clock
TLA
PI6C410
Rs
33-Ohms
5%
Clock#
TLB
2pF
5%
Rp
49.9-Ohms
1%
2pF
5%
Rp
49.9-Ohms
1%
475-Ohms
1%
Figure 4. Configuration test load board termination
Notes:
1. Maximum 10" trace length for CPU @ 200 MHz, 16" trace for SRC @ 100 MHz.
PS8734A
09/02/04
12
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
DC Electrical Characteristics (V = 3.3±5%, V
= 3.3±5%)
DD
DD_A
Symbol
VDD_A
VDD
Parameters
Condition
Min.
3.135
3.135
2.0
Max.
3.465
3.465
Units
V
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current
3.3V Input High Voltage
3.3V Input Low Voltage
3.3V Output High Voltage
3.3V Output Low Voltage
V
V
V
V
+ 0.3
DD
IH
DD
V
V
V
– 0.3
SS
0.8
+5
+ 0.3
IL
I
0 < V < V
DD
-5
0.7
– 0.3
μA
V
IK
IN
V _FS
IH
DD
V _FS
IL
0.35
SS
V
I
= -1mA
OH
2.4
OH
V
I
= 1mA
OL
0.4
OL
12.2
-29
CPU, SRC, DOT: I = 6 x Iref,
OH
Iref = 2.32mA
15.6
-23
V
= 1.0V
OH
USB
I
Output High Current
OH
V
= 3.135V
OH
V
= 1.0V
-33
OH
mA
REF, PCI
V
= 3.135V
= 1.95V
-33
27
OH
V
29
30
OL
USB
V
= 0.4V
= 1.95V
= 0.4V
OL
OL
I
Output Low Current
OL
V
REF, PCI
V
38
5
OL
Cin
Cxtal
Cout
Lpin
Input Pin Capacitance
Xtal Pin Capacitance
Output Pin Capacitance
Pin Inductance
3
3
pF
nH
mA
°C
5
6
7
I
Power Supply Current
Power Down Current
Power Down Current
Ambient Temperature
V
= 3.465V, F
= 400MHz
500
70
12
70
DD
DD
CPU
I
Driven outputs
Tristate outputs
SS
I
SS
Ta
0
PS8734A
09/02/04
13
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
AC Electrical Characteristics (V = 3.3±5%, V
= 3.3±5%)
DD
Parameters
Rise and Fall Time
DD_A
Symbol
Outputs
Min
175
Max. Units Notes
T
/ T
/ T
/ T
CPU, SRC, DOT
PCI/PCIF, REF
USB
700
2.0
2.0
ps
ns
3, 4
6
rise
fall
fall
fall
(measured between 0.175V to 0.525V)
Rise and Fall Time
(measured between 0.4V to 2.4V)
T
rise
0.5
1.0
Rise and Fall Time
(measured between 0.4V to 2.4V)
T
rise
7
ΔT / ΔT
CPU, SRC, DOT
CPU, SRC, DOT
CPU
Rise and Fall Time Variation
Rise/Fall Matching
CPU – CPU Skew
125
20
ps
%
rise
fall
3, 4
T
skew
100
250
3, 5
6
T
skew
SRC
SRC – SRC Skew
PCI – PCI Skew / REF - REF Skew (measured at
1.5V)
T
skew
PCI/PCIF, REF
500
T
T
T
T
T
T
CPU
Cycle – Cycle Jitter
85
125
250
500
350
1000
1150
jitter
jitter
jitter
jitter
jitter
ps
SRC
Cycle – Cycle Jitter
3, 5
DOT
Cycle – Cycle Jitter
PCI/PCIF
Cycle – Cycle Jitter (measured at 1.5V)
Cycle – Cycle Jitter (measured at 1.5V)
Cycle – Cycle Jitter (measured at 1.5V)
Voltage High including overshoot
Voltage Low including undershoot
Absolute crossing poing voltages
Total Variation of Vcross over all edges
Duty Cycle
6
7
6
USB
REF
jitter
V
V
CPU, SRC, DOT
CPU, SRC, DOT
CPU, SRC, DOT
CPU, SRC, DOT
CPU, SRC, DOT
660
-300
250
HIGH
LOW
mV
3, 4
Vcross
550
140
55
∆Vcross
T
45
45
%
%
3, 5
6, 7
DC
T
REF, USB, PCI/PCIF Duty Cycle (measured at 1.5V)
All clock stabilization from power-up
55
DC
T
stable
<1.8
ms
Fig 2
T
drive
Differential output enable after PwrDwn de-asser-
tion
300
5.0
µs
Pwrdwn
T
rise
/ T
fall
PwrDwn rise and fall time
ns
Pwrdwn
Notes:
3. Test configuration is Rs = 33.2 Ohms, Rp = 49.9 Ohms, and 2pF.
4. Measurement taken from Single Ended waveform.
5. Measurement taken from Differential waveform.
6. PCI, PCIF, and REF outputs minimum loading = 10pF, Maximum loading = 30pF.
7. USB output minimum loading = 10pF, Maximum loading = 20pF.
PS8734A
09/02/04
14
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Packaging Mechcanical: 56-Pin SSOP (V)
56
.291
.299
7.39
7.59
.396
.416
10.06
10.56
Gauge Plane
0.25
.02
.04
.010
0.51
1.01
1
18.29
18.54
.015 0.381
x 45˚
.720
.730
.008
0.20
.025 0.635
Nom.
.110 2.79
Max
.008
.0135
0.20
0.34
.025 BSC
0.635
0.20
0.40
.008
.016
0-8˚
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
Packaging Mechcanical: 56-Pin TSSOP (A)
56
.236
.244
6.0
6.2
1
.547 13.9
.555 14.1
SEATING PLANE
.047
Max.
1.20
0.09
.004
0.20
.008
0.45 .018
0.75 .030
.0197
BSC
0.50
.007
.011
.002
.006
0.05
0.15
.319
BSC
0.17
0.27
8.1
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
PS8734A
09/02/04
15
PI6C410
Clock Generator for Intel
PCI-Express Desktop Chipset
Ordering Information:
Ordering Code
PI6C410A
Packaging Code
Package Type
A
V
V
56-Pin, 240mil wide, 0.5mm pitch TSSOP
PI6C410V
56-Pin, 300mil wide, 0.64mm pitch SSOP
PI6C410VE
Pb-free & Green 56-Pin, 300mil wide, 0.64mm pitch SSOP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PS8734A
09/02/04
16
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