PI6C49006 [PERICOM]
Embedded Clock Generator;
| 型号： | PI6C49006 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Embedded Clock Generator |
| 文件： | 总15页 (文件大小：940K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C49006
Embedded Clock Generator
Description
Features
The new PI6C49006 is a high performance clock generator
intended for all kinds of embedded applications, which include
Wireless AP & Femtocell BTS, Multi Function Printer, and other
PCIe/Networking applications. It is the most cost effective way
to generate a high quality, high frequency clock output from a
crystal and reference clock. The device can generate 100/125MHz
HCSL outputs for PCIe, selectable 33/50/66/100/133 LVMOS
clock for network processor and DSP and 25MHz Ethernet clock
combination.
ꢀÎ3.3V supply voltage
ꢀÎ25MHz XTAL or reference clock input
ꢀÎOutput
à
4 x PCIe 2.0 100MHz/125MHz clock with spread
spectrum support
à
(2+2) x selectable 33/50/66/100/133MHz LVCMOS
clock with 10% frequency margin
1 x 125MHz LVCMOS clock
2 x 25MHz LVCMOS clock
1 x 25MHz Differential clock (HCSL type)
à
à
à
ꢀÎPackaging (Pb free and Green)
à
48-pin TSSOP (A)
Block Diagram
4
PCIE(0~3)
PLL Clock Synthesis
2
OutB_(0~1)
X1/ICL
X2
& Spread Spectrum
Crystal
Oscillator
& Control Circuit
2
OutB_(2~3)
FS0
125MHz_Out 0
25MHz_Out (1~2)
FS1
FS2
FS3
FS4
2
SCLK
25MHz_Out Diff
I2C Control
Circuit
SDATA
RESET#
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PI6C49006
Embedded Clock Generator
Pin Description
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
VDD
IREF
GND
VDDA
PCIE1N
PCIE1
PCIE0N
PCIE0
GND
GND
PCIE2
PCIE2N
VDD
VDD
OutB_0
PCIE3N
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
9
OutB_1
SCLK
PCIE3
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SDATA
GND
NC
GND
OutB_2
FS0
OutB_3
VDD
FS1
FS2
VDD
GND
FS3
FS4
25M_Out1
25M_Out2
GND
125M_Out0
VDD
VDD
25M_Out Diff+
25M_Out Diff-
GND
GND_XTAL
VDD_XTAL
X2
RESET#
X1
Pin List
Pin#
1
Pin Name
VDD
Pin Type
Power
Pin Description
3.3V Supply Pin
Connect to 475 ohm resistor to set HCSL output drive
current
2
IREF
Output
3
PCIE0N
PCIE0
GND
Output
Output
Power
Power
Power
Output
Output
Input
100/125MHz HCSL output
100/125MHz HCSL output
Ground
4
5
6
GND
Ground
7
VDD
3.3V Supply Pin
8
OutB_0
OutB_1
SCLK
33/50/66 MHz selectable LVCMOS output
33/50/66MHz selectable LVCMOS output
I2C compatible clock
9
10
11
12
13
14
15
SDATA
GND
Input
I2C compatible data
Power
Output
Output
Power
Ground
OutB_2
OutB_3
VDD
50/66/100/133 MHz selectable LVCMOS output
50/66/100/133 MHz selectable LVCMOS output
3.3V Supply Pin
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PI6C49006
Embedded Clock Generator
Pin List
Pin#
16
Pin Name
VDD
Pin Type
Power
Pin Description
3.3V Supply Pin
17
GND
Power
Ground
18
25M_Out1
25M_Out2
VDD
Output
Output
Power
25.MHz LVCMOS output
25MHz LVCMOS output
3.3V Supply Pin
19
20
21
25M_Out Diff+
25M_Out Diff-
GND
Output
Output
Power
25MHz HCSL output, follow matching circuit in Figure 4
25MHz HCSL output, follow matching circuit in Figure 4
Ground
22
23
Power down reset - When low all PLLs are powered down
and outputs tristated. SMBus registers are reset to default
values
24
RESET#
Input
25
26
27
28
29
30
31
X1
Input
Crystal input. Integrated 6pF capacitance
Crystal output. Integrated 6pF capacitance
3.3V Supply Pin for XTAL
Ground for XTAL
X2
Output
Power
Power
Power
Output
Power
VDD_XTAL
GND_XTAL
VDD
3.3V Supply Pin
125M_Out0
GND
125MHz LVCMOS output
Ground
Frequency select pin for Bank C 25/125MHz LVCMOS
output
32
33
34
35
36
FS4
FS3
FS2
FS1
FS0
Input
Input
Input
Input
Input
Frequency select pin for Bank B 33/50/66/100/133MHz
LVCMOS output
Frequency select pin for Bank B 33/50/66/100/133MHz
LVCMOS output
Frequency select pin for Bank B 33/50/66/100/133MHz
LVCMOS output
Frequency select pin for Bank A 100/125MHz HCSL
output
37
38
39
40
41
42
43
44
45
46
GND
Power
-
Ground
NC
Do Not Connect
NC
-
Do Not Connect
PCIE3
PCIE3N
VDD
Output
Output
Power
Output
Output
Output
Output
100/125MHz HCSL output
100/125MHz HCSL output
3.3V Supply Pin
PCIE2N
PCIE2
PCIE1
PCIE1N
100/125MHz HCSL output
100/125MHz HCSL output
100/125MHz HCSL output
100/125MHz HCSL output
Analog Power Supply Pin. See Application Circuit in
Figure 5
47
48
VDDA
GND
Power
Power
Ground
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PI6C49006
Embedded Clock Generator
Selection Table 1 – 100MHz/125MHz PCIe clock in Selection Table 2 – Spread Spectrum
bank A
SS1
SS0
SSC
FS0
PCIE(0~3)
100MHz
125MHz
0
0
No spread
Down -0.75%
Down -0.5%
No spread
0
0
1
1
1
0
1
1
Selection Table 3 – 33/50/66/100/133MHz LVCMOS clock in bank B
FS1
FS2
FS3
OutB_0/1
OutB_2/3
0
0
0
1. Output disable in hardware control
mode, internal pull-down
1. Output disable in hardware control
mode, internal pull-down
2. Output = 50MHz in software control 2. Output = 133MHz in software control
mode
33M
50M
66M
33M
33M
66M
66M
mode
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
66M
100M
133M
50M
100M
50M
100M
Selection Table 4 – 25/125MHz LVCMOS/25MHz Diff clock in bank C
FS4
125M_Out0
25M_Out1
25M_Out2
25M_Out Diff
0
Output disable, internal
pull-down
25MHz
25MHz
Output disable, internal
pull-down
1
125MHz
25MHz
25MHz
Output disable, internal
pull-down
NC
Output disable, internal
pull-down
Output disable, internal
pull-down
Output disable, internal
pull-down
25MHz Diff
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PI6C49006
Embedded Clock Generator
OutB_1 Frequency Margining Table
FM3 FM2 FM1 FM0 OutB_(2~3)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
nominal
nominal + 1%
nominal + 2%
nominal + 3%
nominal + 4%
nominal + 5%
nominal + 6%
nominal + 8%
nominal + 10%
nominal - 1%
nominal - 2%
nominal - 3%
nominal - 4%
nominal - 6%
nominal - 8%
nominal - 10%
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PI6C49006
Embedded Clock Generator
Serial Data Interface (SMBus)
PI6C49006 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
0/1
How to Write
1 bit
8 bits
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Start
bit
Register
offset
Byte
Count = N
Data Byte
0
Data Byte
N - 1
D2H
Ack
Ack
Ack
Ack
…
Ack Stop bit
Note:
1.
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit 8 bits
1 bit
8 bits
1 bit
1 bit
8 bits
1 bit
8 bits
1 bit
8 bits
1 bit
…
8 bits
1 bit
1 bit
S:
sends
# of
data
bytes
that
will
be
S:
sends
start-
ing
data
byte
N
S:
sends
data
byte
N+X-
1
M: send
starting
sends databyte
M:
Not
Ac-
knowl-
edge
M:
Start
bit
M:
Send
"D2h"
S:
S:
M:
M:
Send
"D3h"
S:
sends
Ack
M:
sends
Ack
M:
sends
Ack
M:
Stop
bit
sends Start
Ack bit
…
Ack
location:
N
sent:
X
Byte 0: Spread Spectrum Control Register
Power Up
Condition
Output(s)
Affected
Bit
Description
Type
RW
RW
RW
Notes
50/66/100/133 MHz
selectable LVCMOS
output
0 = disabled
1 = enabled
7
OE for OutB_2
1
0
1
Enables hardware or software control of OE bits
(see Byte 0–Bit 6 and Bit 5 Functionality table)
0 = hardware cntl
1 = software ctrl
6
RESET# pin, bit 5
Software RESET# bit. Enables or disables all
outputs
(see Byte 0–Bit 6 and Bit 5 Functionality table)
0 = disabled
1 = enabled
5
All outputs
4
3
2
Frequency margining select bit FM3
Frequency margining select bit FM2
Frequency margining select bit FM1
RW
RW
RW
1
0
1
See OutB_2,3 Fre-
quency Margining
Table on Page 5
OutB_2,3
1
Frequency margining select bit FM0
RW
0
50/66/100/133 MHz
selectable LVCMOS
output
0 = disabled
1 = enabled
0
OE for OutB_3
RW
1
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PI6C49006
Embedded Clock Generator
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6
Bit 5
X
Description
0
1
(RESET# = "H" will enable all outputs; SMBus cannot control each output.)
0
Disables all outputs and tri-states the outputs, RESET# HW pin/signal = DO NOT CARE
Enable outputs according to the SMBus default values; SMBus can control each output.
RESET# HW pin/signal, FS1, FS2, FS3 and FS4 = DON'T CARE
1
1
Byte 1: Control Register
Power Up Condi-
tion
Bit
Description
Type
Output(s) Affected
Notes
0 = disabled
1 = enabled
7
6
5
4
3
OE for 25M_Out Diff
OE for 25M_Out2
OE for 25M_Out1
OE for 125_Out0
OE for OutB_1
RW
RW
RW
RW
RW
1
1
1
1
1
25M_Out Diff
25M_Out2
25M_Out1
125_Out0
OutB_1
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
2
1
OE for OutB_0
RW
RW
1
0
OutB_0
Spread Spectrum Selection for
100MHz HCSL PCI Express clocks
Bit 1: SS1, Bit 0:SS0
See Selection Table
2 - Spread Spec-
trum
All 100MHz HCSL PCI
Express outputs
0
RW
0
Byte 2: Control Register
Power Up Condi-
tion
Bit
Description
Type
Output(s) Affected
Notes
7 to 0
Reserved
R
Undefined
Not Applicable
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PI6C49006
Embedded Clock Generator
Byte 3: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
Notes
7
6
5
Reserved
Reserved
Reserved
RW
RW
RW
Undefined
Not Applicable
Not Applicable
Not Applicable
1
1
0 = disabled
1 = enabled
4
3
2
OE for 100M_Out3 HCSL Output
OE for 100M_Out2 HCSL Output
OE for 100M_Out1 HCSL Output
RW
RW
RW
1
1
1
100M_Out3
100M_Out2
100M_Out1
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
1
0
OE for 100M_Out0 HCSL Output
Reserved
RW
R
1
100M_Out0
Undefined
Not Applicable
Byte 4 & 5: Control Register
Power Up Condi-
tion
Bit
Description
Type
Output(s) Affected
Notes
Notes
7 to 0
Reserved
R
Undefined
Not Applicable
Byte 6: Control Register
Power Up Condi-
tion
Bit
Description
Type
Output(s) Affected
7
6
5
4
3
2
1
0
Revivsion ID bit 3
Revivsion ID bit 2
Revivsion ID bit 1
Revivsion ID bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
1
1
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
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PI6C49006
Embedded Clock Generator
1
Recommended Operation Conditions (Over operating free-air temperature range)
Symbol
VDD
VIH
Parameters
Min.
Max.
4.6
Units
3.3V I/O Supply Voltage
Input High Voltage
Input Low Voltage
Storage Temperature
ESD Protection
-0.5
4.6
V
VIL
-0.5
-65
Ts
150
°C
V
VESD
2000
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Note:
Maximum Supply Voltage, VDD.............................................................. 7V
All Inputs and Outputs ................................................ –0.5V to VDD +0.5V
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Ambient Operating Temperature........................................... 0°C to +70°C
Storage Temperature........................................................ –65°C to +150°C
Junction Temperature ........................................................................125°C
Peak Soldering Temperature..............................................................260°C
DC Electrical Characteristics
Unless otherwise specified, VDD=3.3V±5%, Ambient Temperature 0°C to +70°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Operating Supply Volt-
age
VDD
3.135
3.465
Analog Supply Voltage VDDA
3.135
2
3.465
VDD
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
VIH
VIL
VIH
VIL
V
–0.3
0.7VDD
0.8
SDATA, SCLK, FS4
SDATA, SCLK, FS4
VDD
0.3VDD
Operating Supply Cur-
rent
IDD
197
4.3
230
mA
IDD at Output Disable
Condition
RESET# = 0
RESET#
216
Internal Pull-Up/Pull-
Down Resistor
RPU/RPD
k–Ohm
All single-ended outputs
All input pins
75
6
Input Capacitance
CIN
pF
Pin FS4 External Pull-
Up/Pull-Down Resistor
RFS4Ext
470
Ohm
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PI6C49006
Embedded Clock Generator
Electrical Characteristics - Single-Ended
Unless otherwise specified, VDD=3.3V±5%, Ambient Temperature 0°C to +70°C
Parameter
Symbol
Conditions
Min
Typ
25
Max
Units
MHz
kHz
Input Clock Frequency FIN
SCLK Frequency
100
400
Minimum Pulse Width
of RESET# Input
100
ns
Output Frequency
Error
FM0, FM3 = 0
20% to 80%
0
ppm
ns
Output Rise/Fall Time tr, tf
1
2
Output Clock Duty
Cycle
Measured at VDD/2
45
50
57
%
High-Level Output
VOH
IOH = -4mA
IOH = -8mA
VDD-0.4
2.4
Voltage
High-Level Output
VOH
Voltage
V
Low-Level Output
VOL
IOL = 8mA
0.4
Voltage
140
125
200
175
125MHz clock output
33/50/66/100/133MHz clock
output
Peak-to-Peak Jitter
25MHz clock output
125MHz clock output
115
120
150
175
ps
33/50/66/100/133MHz clock
output
Cycle-to-Cycle Jitter
120
120
160
160
10
25MHz clock output
Clock Stabilization
Time from Power Up
3
ms
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PI6C49006
Embedded Clock Generator
Electrical Characteristics - 100MHz Differential HCSL Outputs
Unless otherwise specified, VDD=3.3V±5%, Ambient Temperature 0°C to +70°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output Frequency
100
150
MHz
Cycle-to-Cycle Jitter
TCC/Jitter
ps
Peak-to-Peak Phase
Jitter
Using PCIe jitter measure-
ment method
86
3.1
0
PCIe 2.0 RMS Phase
Jitter
PCIe 2.0 Test Method @
100MHz Output
JRMS2.0
ps
%
Spread Modulation
Percentage
-0.5
Spread Modulation
Frequency
32
50
kHz
%
Duty Cycle
TDC
45
55
SE Rise/Fall Time
Measured from 0.175V Tor , Tof
to 0.525V
1. RL=50-Ohm with CL =
2pF
2. Single-ended waveform
175
700
ps
VT = 50%(measurement
threshold)
Output Skew
TOSKEW
VOH
200
ps
V
High-Level Output
Voltage
Note 2, (RS=33-Ohm,
RT=50-Ohm)
0.65
0.71
0.95
Low-Level Output
Voltage
VOL
–0.20
–13
0
0.05
–19
IOH @ 6*IREF
IOH
–14.2
mA
V
Absolute Crossing
Point Voltage
VCROSS
Note 2, 5, 6
Note 2, 5, 8
Note 3, 9, 10
Note 3, 7
0.25
0.55
Variation of VCROSS
over all rising clock
edges
VCROSS Delta
TPERIOD AVG
TPERIOD ABS
140
mV
ppm
ns
Average Clock Period
Accuracy
–300
9.847
2800
10.203
Absolute Period
(including jitter and
spread spectrum)
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PI6C49006
Embedded Clock Generator
Notes:
1. Measured at the end of an 8-inch trace with a 5pF load.
2. Measurement taken from a single-ended waveform.
3. Measurement taken from a differential waveform.
4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the measurement region for rise and fall time.
The 300 mV measurement window is centered on the differential zero crossing.
5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the falling edge 100M–.
6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement.
7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance,
and spread spectrum modulation.
8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–.
9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations.
10. 10) PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM
there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or
greater. With spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in
maximum period resulting from the -0.5% down spread.
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PI6C49006
Embedded Clock Generator
Application Notes
Crystal circuit connection
e following diagram shows PI6C49006 crystal circuit connection with a parallel crystal. For the CL=18pF
crystal, it is suggested to use C1= 18pF, C2= 18pF. C1 and C2 can be adjusted to fine tune to the target ppm of
crystal oscillator according to different board layouts.
Crystal Oscillator Circuit
XTAL_IN
C1
18pF
SaRonix-eCera
CG2500003
Crystal�(CL�=�18pF)
XTAL_OUT
C2
18pF
Recommended Crystal Specification
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf
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PI6C49006
Embedded Clock Generator
Configuration test load board termination for HCSL Outputs
Rs
33Ω
5%
Clock
TLA
PI6C49006
Rs
33Ω
5%
Clock#
TLB
2pF
5%
2pF
5%
Rp
49.9Ω
1%
Rp
49.9Ω
475Ω
1%
1%
Figure 4. Configuration Test Load Board Termination
3.3V ± 5%
VDD
0.1μF
10μF
5.1ohm
VDDA
0.1μF
Figure 5. Power Supply Filter
www.pericom.com
P-0.1
07/02/12
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PI6C49006
Embedded Clock Generator
DOCUMENT CONTROL NO.
PD - 1501
48
REVISION: G
DATE: 03/09/05
.236
.244
6.0
6.2
See Note 4
1
.488 12.4
.496 12.6
See Note 3
.047
1.20 Max
SEATING PLANE
0.09
0.20
.004
.008
0.45 .018
0.75 .030
.002
.007
.010
.0197
BSC
.006
0.05
0.15
.319
BSC
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.50
0.17
0.27
8.1
Note:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/ED
3. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protru-
sions and gate burrs shall not exceed 0.15mm per side.
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion
shall not exceed 0.25mm per side.
DESCRIPTION: 48-Pin 240-Mil Wide TSSOP
PACKAGE CODE: A
Note:
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
•
Ordering Information(1-3)
Ordering Code
Package Code
Package Description
48-pin, Pb-free & Green, TSSOP, (A48)
PI6C49006AE
A
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
www.pericom.com
P-0.1
07/02/12
All trademarks are property of their respective owners.
12-0212
15
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