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PI6C671FV [PERICOM]

Clock Generator for Pentium Modules; 时钟发生器奔腾模块
PI6C671FV
型号： PI6C671FV
厂家： PERICOM SEMICONDUCTOR CORPORATION    PERICOM SEMICONDUCTOR CORPORATION
描述：

Clock Generator for Pentium Modules
时钟发生器奔腾模块

时钟发生器
文件： 总7页 (文件大小：200K)
中文：  中文翻译
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PI6C671F  
Clock Generator for Pentium Modules  
Features  
Description  
• Supports Pentium or Pentium II CPU modules  
The PI6C671F is a mixed-voltage clock generator designed to  
providealltimingsignalsforIntelPentium/PentiumIImodule-based  
motherboards. It provides four CPU, seven PCI, and up to eight  
SDRAM clocks. Additionally, three reference clocks (same fre-  
quency as the crystal) and two selectable 24/48 MHz clocks are  
available.  
• Spread Spectrum capability reduces EMI  
• Low power consumption  
• FourCPUClockswithV  
of3.3Vor2.5V  
DDQ2  
• EnhanceddriveonCPUCLK0  
Pericom design improvements resulted in a low-power device  
optimized for 2.5V CPU operation. A special spread-spectrum  
feature may be enabled to minimize EMI.  
• Seven PCI synchronous clocks (3.3V)  
• OneIOAPICClock@14.31818MHz  
(Powerfrompin46),withV  
of3.3Vor2.5V  
DDQ1  
2
The two-wire I C serial interface can be used to reduce circuit  
• Two48/24MHzclocks(3.3V)  
• Six/eightSDRAMclocks(3.3V)  
2
noise and power consumption. I C control lets you enable/disable  
eachclockoutputdriver, changeCPUfrequencies, andselect24or  
48 MHz outputs.  
• ThreeRef.Clocks@14.31818MHz(3.3V)  
• Internal crystal loading capacitor  
A power-down function (pin 44) puts the whole system in a low-  
powermodebystoppingthecrystaloscillatorandboth PLLs. CPU  
andPCIclocksmayalsobestoppedbythe“CPU_STOP#”(pin27),and  
“PCI _STOP#” (pin 26) functions.  
• Ref.14.31818MHzcrystaloscillatorinput  
• Separate 66/60# MHz select pin  
• Separate power management MODE control pin  
2
Note:PurchaseofI CcomponentsfromPericomconveysalicense  
2
2
• I C 2-WireSerialInterface  
to use them in an I C system as defined by Philips.  
• 48-pinSSOPPackage(V)andTSSOP(A)  
Block Diagram  
Pin Configuration  
48-Pin  
A, V  
÷
All trademarks are of their respective companies.  
PS8137A 03/15/99  
392  
PI6C671F  
Clock Generator for Pentium Modules  
Pin Descriptions  
Signal Name  
Xin  
Type  
Qty  
1
Pin  
4
Description  
1
2
I
Crystal oscillator input or input for externally generated reference signal.  
Crystal oscillator output. Connect to external parallel resonant crystal.  
Xout  
O
1
5
Select pin for enabling 66 MHz or 60 MHz.  
H=66 MHz, L=60 MHz. Has an internal pull-up resistor.  
SEL66/60#  
I
1
18  
CPUCLK (0-3)  
SDRAM  
O
O
4
6
1
1
42,41,39,38  
CPU & Host clock outputs. Powered by V  
, can be 2.5V or 3.3V.  
DDQ2  
3
29,30,32,33,35,36 SDRAM clocks 60/66 MHz. Powered by V  
(3.3V).  
DDQ3  
SDRAM6/CPU_STOP# bi-dir  
27  
26  
MODE=1: SDRAM6, MODE=0: CPU_STOP#.  
MODE=1: SDRAM7, MODE=0: PCI_STOP#.  
SDRAM7/PCI_STOP#  
MODE  
bi-dir  
I
Mode Select pin for enabling power management features at pins 26 & 27.  
Has an internal pull-up resistor.  
4
5
1
6
PCICLK(0-5)  
PCICLK_F  
REF0,REF1,REF2  
IOAPIC0  
O
6
1
3
1
1
2
1
1
7
2
5
1
1
9,11,12,13,14,16 Low skew PCI clock outputs. TTL compatible. Powered by V  
(3.3V).  
DDQ3  
O
8
2,1,47  
45  
Free running synchronous PCI clock. Stops when in shut down mode.  
14.318 MHz buffered reference clock outputs.  
O
O
I
IOAPIC0 clock outputs. Powered by V  
PWR_DWN#, active LOW.  
, can be 2.5V or 3.3V  
DDQ1  
6
PWR_DWN#  
48/24MHz  
44  
O
22,23  
19  
Selectable 48/24 MHz clock output. Powered by V  
(3.3V).  
DDQ3  
2
SDATA  
I
Serial data input for I C control.  
2
SDCLK  
I
20  
Clock input for I C control.  
7
V
Ground  
Power  
Power  
Power  
Power  
3,10,17,24,31,37,43 Ground pins for the device.  
SS  
V
25,48  
Power supply for analog circuits and core logic.  
3.3V I/O power supply.  
DD  
8
V
V
7,15,21,28,34  
DDQ3  
DDQ2  
40  
46  
CPUCLK power supply. Can be either 2.5V or 3.3V.  
IOAPIC power supply. Can be either 2.5V or 3.3V.  
9
V
DQ1  
10  
11  
12  
13  
14  
15  
Driver Types  
Pin  
2
Driver Type  
Symbol  
REF0  
Description  
D
C
E
14.318 MHz clock output.  
1,47  
8
REF1, REF2 14.318 MHz clock output.  
PCICLK_F Free running clock during PCICLK stopped.  
9,11,12,  
13.14,16  
E
C
D
A
B
PCICLK  
48/24MHz 48/24 MHz clock output 3.3V selectable.  
PCI clock outputs TTL compatible 3.3V.  
22,23  
26,27,29,30,  
32,33,35,36  
SDRAM  
SDRAM clocks 60/66 MHz.  
38,39,41,42  
45  
CPUCLK  
CPU and host clock outputs: 2.5V or 3.3V  
IOAPIC clock output: 2.5V or 3.3V.  
IOAPIC0,  
IOAPIC1  
PS8137A 03/15/99  
393  
PI6C671F  
Clock Generator for Pentium Modules  
Power Management Functions  
Any or all clocks can be enabled or shut down via the I2C control  
interface. AllclocksstopintheLOWstate. CPU,SDRAM,andPCI  
clocks wait for one rising edge of PCICLK_F followed by a falling  
edge of the clock of interest before settling in the LOW state. To  
reduce power consumption the PI6C671F clocks may be disabled in  
accordance with the following table.  
CPUCLK,  
CPU_STOP# PCI_STOP# PWR_DWN#  
SDRAM  
Other  
Clocks  
Crystal &  
VCOs  
PCICLK  
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
LOW  
LOW  
LOW  
LOW  
LOW  
Off  
Running  
Running  
Running  
Running  
Running  
Running  
Running  
Running  
LOW  
33/30 MHz  
LOW  
66/60 MHz  
66/60 MHz  
33/30 MHz  
2-Wire I2C Control  
2
The I C interface permits individual enable/disable of each  
clock output and test mode enable.  
a stop condition. The first byte after a start condition is always a  
7-bit address byte followed by a read/write bit. (HIGH = read from  
addresseddevice,LOW=writetoaddresseddevice).Ifthedevice’s  
own address is detected, PI6C671F generates an acknowledge by  
pulling SDATA line LOW during ninth clock pulse, then accepts the  
following data bytes until another start or stop condition is detected.  
The PI6C671F is a slave receiver device. It can not be read back.  
Sub addressing is not supported. All preceding bytes must be sent  
in order to change one of the control bytes.  
Every bite put on the SDATA line must be 8-bits long (MSB first),  
followed by an acknowledge bit generated by the receiving  
device.  
During normal data transfers SDATA changes only when SDCLK  
isLOW. Exceptions: AHIGHtoLOWtransitiononSDATAwhile  
Following acknowledgement of the address byte (D2), two more  
bytes must be sent:  
1. “Command Code” byte, and  
2. “Byte Count” byte.  
SDCLK is HIGH indicates a “start” condition. A LOW to HIGH Although the data bits on these two bytes are “don’t care,” they  
transition on SDATA while SDCLK is HIGH is a “stop” condition must be sent and acknowledged.  
and indicates the end of a data transfer cycle.  
2
The I C interface is disabled when the PWR_DWN# pin is LOW.  
Each data transfer is initiated with a start condition and ended with Preset control register contents are retained.  
I2C Serial Configuration  
Byte 0: Functional and Frequency Select  
Clock Register (1 = enable, 0 = disable)  
Bit Pin No. @ Powerup  
Description  
(Reserved)  
7
6
5
4
0
0
0
0
(Reserved, don't change)  
(Reserved, don't change)  
(Reserved, don't change)  
48/24 MHz (Freq Select)  
1 = 48 MHz, 0 =24 MHz  
3
2
23  
22  
1
1
48/24 MHz (Freq Select)  
1 = 48 MHz, 0 = 24 MHz  
1
0
0
0
Bit1 Bit0  
1
1
0
0
1 : Tri-State  
0 : Spread Spectrum  
1 : Test Mode  
0 : Normal Operation  
PS8137A 03/15/99  
394  
PI6C671F  
Clock Generator for Pentium Modules  
Byte 1: CPU 24/48 MHz Active/Inactive Register  
(1 = enable, 0 = disable)  
Byte 4: SDRAMActive/Inactive Register  
(1 = enable, 0 = disable)  
1
2
Bit  
7
Pin No.  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
Description  
SDRAM15 (Active/Inactive)  
SDRAM14 (Active/Inactive)  
SDRAM13 (Active/Inactive)  
SDRAM12 (Active/Inactive)  
SDRAM11 (Active/Inactive)  
SDRAM10 (Active/Inactive)  
SDRAM9 (Active/Inactive)  
SDRAM8 (Active/Inactive)  
Bit Pin No. @ Powerup  
Description  
48/24 MHz (Active/Inactive)  
48/24 MHz (Active/Inactive)  
(Reserved)  
7
6
5
4
3
2
1
23  
22  
1
1
6
X
X
1
5
N/A  
38  
CPUCLK4 (Active/Inactive)  
CPUCLK3 (Active/Inactive)  
CPUCLK2 (Active/Inactive)  
CPUCLK1 (Active/Inactive)  
4
3
3
39  
1
2
41  
1
1
4
5
0
42  
1
CPUCLK0 (Active/Inactive)  
0
Byte 5: Peripheral Active/Inactive Register  
(1 = enable, 0 = disable)  
Byte 2: PCI Active/Inactive Register  
(1 = enable, 0 = disable)  
Bit Pin No. @ Powerup  
Description  
Bit Pin No. @ Powerup  
Description  
(Reserved)  
6
7
6
5
4
3
2
1
0
X
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
X
X
1
(Reserved)  
8
PCICLK_F (Active/Inactive)  
PCICLK5 (Active/Inactive)  
PCICLK4 (Active/Inactive)  
PCICLK3 (Active/Inactive)  
PCICLK2 (Active/Inactive)  
PCICLK1 (Active/Inactive)  
PCICLK0 (Active/Inactive)  
(Reserved)  
16  
14  
13  
12  
11  
9
(Reserved)  
7
45  
1
IOAPIC (Active/Inactive)  
(Reserved)  
X
1
8
47  
1
REF2 (Active/Inactive)  
REF1 (Active/Inactive)  
REF0 (Active/Inactive)  
1
9
2
1
10  
11  
12  
13  
14  
15  
Byte 6: Optional Register  
for Possible Future Requirements  
Byte3: SDRAM Active/Inactive Register  
(1 = enable, 0 = disable)  
Bit Pin No. @ Powerup  
Description  
Bit  
7
Pin Number  
Description  
(Reserved)  
(Reserved)  
(Reserved)  
(Reserved)  
(Reserved)  
(Reserved)  
(Reserved)  
(Reserved)  
7
6
5
4
3
2
1
26  
27  
29  
30  
32  
33  
35  
1
1
1
1
1
1
1
SDRAM7 (Active/Inactive)  
SDRAM6 (Active/Inactive)  
SDRAM5 (Active/Inactive)  
SDRAM4 (Active/Inactive)  
SDRAM3 (Active/Inactive)  
SDRAM2 (Active/Inactive)  
SDRAM1 (Active/Inactive)  
X
X
X
X
X
X
X
X
6
5
4
3
2
1
0
36  
1
SDRAM0 (Active/Inactive)  
0
PS8137A 03/15/99  
395  
PI6C671F  
Clock Generator for Pentium Modules  
Byte 7: Frequency Control  
DC Specifications  
Absolute Maximum DC Power Supply  
Bit  
7
@ Power up  
Description  
(Reserved)  
(Reserved)  
(Reserved)  
(Reserved)  
(Reserved)  
FSEL2  
Symbol  
Supply Voltage  
3.3V Core & I/O  
3.3V Core  
Min. Max. Units  
X
X
X
X
X
1
V
-0.5  
-0.5  
-0.5  
-0.5  
4.6  
4.6  
4.6  
4.6  
DDQ3  
6
V
DD  
5
V
V
DDQ2  
V
DDQ1  
2.5/3.3V I/O  
2.5/3.3V I/O  
4
3
2
DCOperatingRequirements  
(V , V =3.3V ±5%, V  
1
1
FSEL1  
=2.5V ±5%, T =0 to 70°C)  
DDQ2 A  
DD DDQ3  
Symbol Parameter  
Condition  
Min. Typ. Max. Units  
0
1
FSEL0  
2.5V Output  
VOH2  
IOH = -1mA  
2.1  
High Voltage  
FSEL2 FSEL1 FSEL0  
Frequency  
3.3V Output  
VOH3  
IOH = -1mA  
IOL = 1mA  
IOL = 1mA  
2.4  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(Reserved)  
High Voltage  
V
2.5V Output  
VOL2  
(Reserved)  
(Reserved)  
33 MHz  
0.4  
Low Voltage  
3.3V Output  
VOL3  
0.4  
Low Voltage  
Dynamic  
66 MHz  
Unloaded  
Outputs  
50 MHz  
IDD  
Supply  
Current  
55  
14  
70  
20  
mA  
55 MHz  
60 MHz  
Power Down PWR_DWN# = 0  
IPD  
Supply  
Current  
MODE = Float  
(high)  
µA  
From SEL66/60# pin  
Note: Typical values are at room temperature  
PS8137A 03/15/99  
396  
PI6C671F  
Clock Generator for Pentium Modules  
Driver Specifications  
1
2
Symbol  
Parameter  
Condition  
Minimum Typical Maximum Units  
Type A: CPUCLK1-3 2.5V Buffer  
Iohmin Pull-up Current  
Vout = 1.0V  
Vout = 1.2V  
-49  
48  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Iolmin Pull-down Current  
3
Type A: CPUCLK1-3 3.3V Buffer  
Iohmin Pull-up Current  
Vout = 1.0V  
Vout = 1.6V  
-69  
63  
4
5
Iolmin Pull-down Current  
Type B: IOAPIC 2.5V Buffer  
Iohmin Pull-up Current  
Vout = 1.4V  
Vout = 1.0V  
-36  
36  
Iolmin Pull-down Current  
Type B: IOAPIC 3.3V Buffer  
6
Iohmin Pull-up Current  
Vout = 1.0V  
Vout = 1.9V  
-58  
57  
Iolmin Pull-down Current  
7
Type C: REF1, REF2, 48/24 MHz (3.3V) Buffer  
Iohmin Pull-up Current  
Vout = 1.0V  
Vout = 1.95V  
-29  
29  
8
Iolmin Pull-down Current  
Type D: REF0, SDRAM (3.3V) Buffer  
9
Iohmin Pull-up Current  
Vout = 2.0V  
Vout = 1.0V  
-54  
54  
Iolmin Pull-down Current  
10  
11  
12  
13  
14  
15  
Type E: PCI Clock Buffer  
Iohmin Pull-up Current  
Vout = 1.0V  
Vout = 1.95V  
-33  
30  
Iolmin Pull-down Current  
Type F: CPUCLK0 2.5V Buffer  
Vout = 1.0V  
Vout = 2.5V  
Vout = 1.2V  
Vout = 0.3V  
-62  
Iohmin  
Pull-up Current  
Iohmax  
-19  
mA  
60  
Iohmin Pull-down Current  
41  
PS8137A 03/15/99  
397  
PI6C671F  
Clock Generator for Pentium Modules  
AC Timing  
Symbol  
Parameter  
Host CLK rise/fall time, 0.4V - 2.0V  
Host CLK Jitter  
Min.  
Max.  
1.6  
Units  
ns  
tRF  
0.4  
tJITTER  
250  
ps  
Measured the rising edge CLKs at 1.25V for the  
2.5V clocks and at 1.5V for the 3.3V clocks  
Duty Cycle  
45  
55  
%
ps  
tHSKW  
tHSKSD  
tPKPS  
Host Bus CLK skew  
250  
500  
500  
500  
4
Host to SDRAM  
PCI CLK period stability  
PCI Bus CLK skew  
tPSKW  
tHPOFFSET  
tSTB  
Host to PCI Clock Offset  
CLK Stabilization at power-up  
1
ns  
3
ms  
48-Pin SSOP Package Data  
48  
.395  
.420  
10.03  
.291  
.299  
7.39  
7.59  
10.67  
Gauge Plane  
.010  
0.25  
.02 0.51  
.04 1.01  
1
0.381  
0.635  
.015  
.025  
x 45˚  
.008  
0.20  
Nom.  
.620  
.630  
15.75  
16.00  
.110 2.79 Max  
.008 0.20  
.016 0.40  
0-8˚  
.008 0.20  
.0135 0.34  
.025 BSC  
0.635  
X.XX  
X.XX  
DENOTES DIMENSIONS  
IN MILLIMETERS  
48-Pin TSSOP Package Data  
48  
.236  
.244  
6.0  
6.2  
1
.488 12.4  
.496 12.6  
.047  
1.20 Max  
SEATING PLANE  
0.09  
.004  
0.20  
.008  
0.45 .018  
0.75 .030  
.002  
.006  
0.05  
0.15  
.007  
.010  
.0197  
BSC  
.319  
8.1  
BSC  
0.50  
0.17  
0.27  
X.XX  
X.XX  
DENOTES DIMENSIONS  
IN MILLIMETERS  
Ordering Information  
P/N  
Description  
PI6C671FV  
PI6C671FA  
48-pin SSOP Package  
48-pin TSSOP Package  
Pericom Semiconductor Corporation  
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com  
PS8137A 03/15/99  
398  

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