PI6CV855LE [PERICOM]

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型号：	PI6CV855LE
厂家：	PERICOM SEMICONDUCTOR CORPORATION
描述：	暂无描述时钟驱动器动态存储器双倍数据速率
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PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

ProductFeatures

ProductDescription

PLLclockdistributionoptimizedforSSTL_2DDRSDRAM

applications.

PI6CV855PLLclockdeviceisdevelopedforSSTL_DDRSDRAM

applications. This PLL Clock Buffer is designed for 2.5 V and

DDQ

Distributes one differential clock input pair to five differential

clock output pairs.

Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2

Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2

Externalfeedbackpins(FBIN,FBIN)areusedto

synchronize the outputs to the clock input.

2.5V AV operation and differential data input and output levels.

The device is a zero delay buffer that distributes a differential clock

input pair (CLK, CLK) to five differential pairs of clock outputs

(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs

(FBOUT, FBOUT). The clock outputs are controlled by the input

clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the

Analog Power input (AV ). When the AV is strapped low, the

Operates at AV = 2.5V for core circuit and internal PLL,

PLL is turned off and bypassed for test purposes.

and V

= 2.5V for differential output drivers

DDQ

When the input frequency falls below a suggested detection fre-

quency that is below the operating frequency of the PLL, the device

willenteralowpowermode.Inlowpowermode,PLListurnedOFF,

Y[0:4]andY[0:4]outputsare3-stated.

AvailablePackage:

Plastic28-pinTSSOP

ThePI6CV855isabletotrackSpreadSpectrumClockingtoreduce

EMI.

PinConfiguration

BlockDiagram

GND

D D Q

CLK

GND

D D Q

CLK

FBOUT

28-Pin

PLL

FBIN

D D Q

D D

FBIN

GND

AGND

GND

D D Q

Logic

and

Test Ciruit

Y 3

D D Q

GND

PS8545 06/20/01

PI6CV855

PLLClockDriverfor2.5V

SSTL 2 DDR SDRAM Memory

PinoutTable

Name

I/O

Type

Pin No.

Description

CLK

Reference Clock input

Y[0:4]

3,11,13,17,27

2,10,14,16,28

Clock outputs.

Complement Clock outputs.

FBOUT

Feedback output, and Complement Feedback Output

FBIN

Feedback input, and Complement Feedback input

Power Supply for I/O pins.

DDQ

4,12,18,22,26

Power

Analog/core power supply. AV can be used to bypass the PLL for testing purposes. When

AV is strapped to ground, PLL is bypassed & CLK is buffered directly to the device outputs.

AGND

GND

Analog/core ground. Provides the ground reference for the analog/core circuitry

Ground for I/O pins.

Ground

1,9,15,19,25

FunctionTable

Inputs

Outputs

FBOUT

PLL State

CLK

Y[0:4]

FBOUT

GND

Bypassed/Off

GND

Bypassed/Off

2.5V(nom)

off

<20 MHz

Notes: For testing and power saving purposes, PI6CV855 will power down if the frequency of the reference inputs

CLK, CLK is well below the operating frequency range. The maximum power down clock frequency is below 20 MHz.

Forexample,PI6CV855willbepowereddownwhentheCLK,CLKstoprunning.

Z = High impedance

X = Dont care

PS8545 06/20/01

PI6CV855

PLLClockDriverfor2.5V

SSTL 2 DDR SDRAM Memory

Absolute Maximum Ratings (Over operating free-air temperature range)

Symbol

, AV

Parameter

I/O supply voltage range and analog/core supply voltage range

Input voltage range

Min.

0.5

Max.

Units

3.6

DDQ

+0.5

DDQ

Output voltage range

Storage temperature

0.5

Tstg

150

Note: Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

TimingRequirements(Overrecommendedoperatingfree-airtemperature)

AV_DD, V_DDQ= 2.5V ±0.2V

Symbol

Description

Units

Min.

Max.

170

Operating clock frequency^(1,2)

Application clock frequency⁽³⁾

Input clock duty cycle

f_CK

MHz

t_DC

µs

t_STAB

PLL stabilization time after powerup

100

Notes:

1. The PLL is able to handle spread spectrum induced skew.

2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is

not required to meet the other timing parameters. (Used for low-speed debug).

3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.

PS8545 06/20/01

PI6CV855

PLLClockDriverfor2.5V

SSTL 2 DDR SDRAM Memory

DCSpecifications

Recommended Operating Conditions

Symbol

Parameter

Min.

2.3

1.8

Nom.

2.5

Max.

2.7

Units

Analog/core supply voltage

DDQ

Output supply voltage

2.5

2.7

High-level output voltage

DDQ

Low-level output voltage

0.5

Input differential-pair crossing voltage

Output differential-pair crossing voltage at the SDRAM clock input

Input voltage level

/2) 0.2

/2) +0.2

DDQ

/2) 0.2

/2) +0.2

DDQ

0.3

+0.3

+0.6

DDQ

Input differential voltage between CLK and CLK

0.36

0.7

DDQ

Output differential voltage between Y[n] and Y[n] and FBOUT

and FBOUT

+0.6

DDQ

Operating free air temperature

°C

ElectricalCharacteristics

Parameter

Test Conditions

I_I= 18mA

A_VDD, V_DDQ

2.3V

Min.

Typ. Max. Units

V_IK

I_I

All inputs

1.2

±10

300

100

CLK, FBIN

V_I= V_DDQor GND

V_DD= 2.7V ⁽¹⁾

2.7V

µA

Dynamic supply current of V_DDQ

Static supply current

Dynamic supply current of AV_DD

Static supply current

CLK and CLK

I_DDQ

CLK & CLK <20 MHz

V_DD= 2.7V ⁽¹⁾

I_ADD

CLK & CLK <20 MHz

100

C_I

V_I= V_DDor GND

2.5V

2.0

3.0

FBIN and FBIN

Notes:

1. Driving 9 or 18 DDR SDRAM memory chips with 120-ohm termination resistor for each clock output pair at 134 MHz.

2. The maximum power down clock frequency is below 20 MHz.

PS8545 06/20/01

PI6CV855

PLLClockDriverfor2.5V

SSTL 2 DDR SDRAM Memory

ACSpecifications

Switching characteristics over recommended operating free-air temperature range, f_CLK> 100 MHz (unless otherwise noted).

(See Figure 1 and 2)

AV_CC, V_DDQ= 2.5V ±0.2V

Parameter

Description

Static phase offset⁽¹⁾

Diagram

Units

Min.

100

1.0

Nom.

Max

t(θ)

tjit(cc)

tjit(per)

tjit(hper)

tsl(i)

Figure 4

Figure 3

Figure 6

Figure 7

Figure 8

Figure 5

Cycle-to-cycle jitter

Period jitter

Half-period jitter

100

2.0

100

Input clock slew rate⁽²⁾

Output clock slew rate⁽²⁾

Output clock skew

V/ns

tsl(o)

1.0

tsk(o)

The PLL on the PI6CV855 meets all the above parameters while supporting SSC synthesizers with the following parameters⁽³⁾.

SSC modulation frequency

SSC clock input frequency deviation

PLL loop bandwidth

30.0

0.00

50.0

kHz

0.50

MHz

degrees

Phase angle

0.031

Notes:

1. Static Phase offset does not include jitter.

2. The slew rate is determined from the IBIS model with test load shown in Figure 1.

3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.

PS8545 06/20/01

PI6CV855

PLLClockDriverfor2.5V

SSTL 2 DDR SDRAM Memory

Z = 60Ω

DDR

SDRAM

R =120Ω

DDR

SDRAM

Figure1.IBISModelOutputLoad

DDQ

Z = 60Ω

Z = 50Ω

R =10Ω

C=14pF

R = 50Ω

–V

DDQ

Z = 50Ω

Z = 60Ω

C=14pF

DDQ

SCOPE

–V

DDQ

Figure2.OutputLoadTestCircuit

PS8545 06/20/01

PI6CV855

PLLClockDriverfor2.5V

SSTL 2 DDR SDRAM Memory

Yx,FBOUT

t_{cycle n}

t_{cycle n+1}

t_jit(cc)= t_{cycle n}- t_{cycle n+1}

Figure3.Cycle-to-CycleJitter

CLK

FBIN

t₍

)

n+1

n=N

t₍

∑

) n

(N is a large number of samples)

Figure 4. Static Phase Offset

Yx, FBOUT

t_sk(o)

Figure5.OutputSkew

PS8545 06/20/01

PI6CV855

PLLClockDriverfor2.5V

SSTL 2 DDR SDRAM Memory

Yx, FBOUT

t_{cycle n}

Yx, FBOUT

f_O

t _jit(per)

t_{cycle n}

Figure 6. Period Jitter

Yx, FBOUT

t _n+1

t_{half period n}

half period

f_O

2*f_O

t_jit(hper)

t_{half period n}

Figure7.Half-PeriodJitter

V_DDQ

80%

20%

Clock Inputs

and Outputs

t_sl(i),t_sl(o)

Figure8.InputandOutputSlewRates

PS8545 06/20/01

PI6CV855

PLLClockDriverfor2.5V

SSTL 2 DDR SDRAM Memory

PackagingMechanical:28-PinTSSOP(L)

.169

.177

4.3

4.5

0.09

0.20

.004

.008

.378

.386

0.45 .018

0.75 .030

9.6

9.8

.252

BSC

6.4

.047

1.20

Max

SEATING

PLANE

X.XX DENOTES CONTROLLING

X.XX DIMENSIONS IN MILLIMETERS

.002

.006

0.05

0.15

.007

.012

.0256

BSC

0.19

0.30

0.65

OrderingInformation

Ordering Code

Package Name

Package Type

28-pin, 4.4mm wide TSSOP

PI6CV855L

L28

Pericom Semiconductor Corporation

2380BeringDrive • SanJose,CA95131•1-800-435-2336 • Fax(408)435-1100• http://www.pericom.com

PS8545 06/20/01

PI6CV855LE [PERICOM]

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