PI6CV857LKX [PERICOM]

PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.173 INCH, PLASTIC, TVSOP-48;


型号：	PI6CV857LKX
厂家：	PERICOM SEMICONDUCTOR CORPORATION
描述：	PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.173 INCH, PLASTIC, TVSOP-48 驱动光电二极管逻辑集成电路电视
文件：	总9页 (文件大小：87K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PI6CV857L

PLL Clock Driver for

2.5V DDR-SDRAM Memory

ProductFeatures

ProductDescription

• PLL clockdistributionoptimizedforDouble Data Rate

SDRAMapplications.

PI6CV857LPLLclockdeviceisdevelopedforregisteredDDRDIMM

applicationsThisPLLClockBufferisdesignedfor2.5V and2.5V

DDQ

• Distributes one differential clock input pair to ten differential

clock output pairs.

operation and differential data input and output levels.

The device is a zero delay buffer that distributes a differential clock

inputpair(CLK,CLK)totendifferentialpairsofclockoutputs(Y[0:9],

Y[0:9]) and one differential pair feedback clock outputs

(FBOUT,FBOUT) . The clock outputs are controlled by the input

clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V

LVCMOSinput(PWRDWN)andtheAnalogPowerinput(AV ).

When input PWRDWN is low while power is applied, the input

receiversaredisabled,thePLListurnedoffandthedifferentialclock

• Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2

• Input PWRDWN: LVCMOS

• Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2

• Externalfeedbackpins(FBIN,FBIN)areusedto

synchronize the outputs to the clock input.

• Operates at AV = 2.5V for core circuit and internal PLL,

and V

= 2.5V for differential output drivers

DDQ

outputs are 3-stated. When the AV is strapped low, the PLL is

• AvailablePackages:Plastic48-pinTSSOP,TVSOP

turned off and bypassed for test purposes.

When the input frequency falls below a suggested detection fre-

quency that is below the operating frequency of the PLL, the device

willenteralowpowermode.Aninputfrequencydetectioncircuitwill

detectthelowfrequencyconditionandperformthesamelowpower

features as when the PWRDWN input is low.

ThePLLinthePI6CV857Lclockdriverusestheinputclocks(CLK,

CLK)andthefeedbackclocks(FBIN,FBIN)toprovidehigh-perfor-

mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]).

ThePI6CV857LisalsoabletotrackSpreadSpectrumClockingfor

reducedEMI.

BlockDiagram/PinConfiguration

GND

CLK

D D Q

PLL

FBIN

GND

FBIN

GND

48-Pin

D D Q

CLK

D D Q

P W R DW N

FBIN

Powerdown

PWRDWN

D D Q

and Test

FBOUT

D D

Logic

AGND

GND

D D Q

GND

FBOUT

GND

FBOUT

PS8543A

07/29/02

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

PinoutTable

Pin Name

Pin No.

I/O Type

Description

CLK

Reference Clock input

3,5,10,20,22,27,29,39,44,46

2,6,9,19,23,26,30,40,43,47

Clock outputs.

Complement Clock outputs.

FBOUT

Feedback output, and Complement Feedback Output

Feedback Input, and Complement Feedback Input

FBIN

Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0,

the part is powered down and the differential clock outputs are disabled to a

3-state. When PWRDWN = 1, all differential clock outputs are enabled and run

at the same frequency as CLK.

PWRDWN

4,11,12,15,21,28,34,38,45

Power Supply for I/O.

DDQ

Analog /core power supply. AV can be used to bypass the PLL for testing

Power

purposes. When AV is strapped to ground, PLL is bypassed and CLK is

buffered directly to the device outputs.

AGND

GND

Analog/core ground. Provides the ground reference for the analog/core circuitry

Ground

1,7,8,18,24,25,31,41,42,48

FunctionTable

Inputs

Outputs

FBOUT

PLL

AV_DD

GND

PWRDWN

CLK

FBOUT

Bypassed/off

GND

Bypassed/off

off

2.5V(nom)

<20 MHz ⁽¹⁾

Notes: For testing and power saving purposes, PI6CV857L will power down if the frequency of the reference inputs CLK, CLK is well

belowtheoperatingfrequencyrange. Themaximumpowerdownclockfrequencyisbelow20MHz. Forexample, PI6CV857Lwillbe

powered down when the CLK,CLK stop running.

Z = High impedance

X = Don’t care

PS8543A

07/29/02

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

AbsoluteMaximumRatings(Overoperatingfree-airtemperaturerange)

Symbol

Parameter

I/O supply voltage range and analog/core supply voltage range

Input voltage range

Min.

– 0.5

– 50

– 100

– 65

Max.

Units

, AV

3.6

DDQ

+0.5

DDQ

Output voltage range

Input Clamp Current

Output Clamp Current

Continuous output Current

Continuous current through each V , V , or GND

DDQ

100

150

O(PWR)

Tstg

Storage temperature

Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

DCSpecifications

Recommended Operating Conditions

Symbol

Parameter

Min.

2.3

–0.3

1.7

Nom.

2.5

Max.

2.7

Units

Analog/core supply voltage

Output supply voltage

DDQ

2.5

2.7

Low-level input voltage for PWRDWN pin

High-level input voltage for PWRDWN pin

Input Voltage

0.7

+0.3

DDQ

High-level output current

–

Low-level output current

–

–12

/2) +0.2

Input differential-pair crossing voltage

/2) –0.2

DDQ

/2)

+0.15

/2)

DDQ

Output differential-pair crossing voltage at the DRAM clock input

–0.15

–0.3

0.36

0.7

Input voltage level

+0.3

DDQ

Input differential voltage between CLK and CLK

Output differential voltage between Y[n] &Y[n] and FBOUT & FBOUT

Operating free air temperature

+0.6

°C

PS8543A

07/29/02

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

TimingRequirements(Overrecommendedoperatingfree-airtemperature)

AV_DD, V_DDQ= 2.5V ±0.2V

Symbol

Description

Units

Min.

Max.

170

Operating clock frequency^(1,2)

Application clock frequency⁽³⁾

Input clock duty cycle

f_CK

MHz

t_DC

µs

t_STAB

PLL stabilization time after powerup

100

Notes:

1. The PLL is able to handle spread spectrum induced skew.

2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the

other timing parameters. (Used for low-speed debug).

3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.

ElectricalCharacteristics

Parameter

All inputs

Test Conditions

I_I= –18mA

A_VDD, V_DDQ

2.3V

Min.

Typ. Max. Units

V_IK

–1.2

I_OH= –100µA

I_OH= –12mA

2.3 to 2.7V

2.3V

VDDQ– 0.1

1.7

V_OH

High output voltage

Low output voltage

I_OL= 100µA

2.3 to 2.7V

2.3V

0.1

0.6

V_OL

I_I

I_OL= 12mA

CLK, FBIN

PWRDWN

V_I= V_DDQor GND

±10

µA

2.7V

Dynamic supply current of V_DDQV_DD= 2.7V

CLK & CLK <20 MHz or

PWRDWN = Low⁽⁴⁾

Dynamic supply current of AV_DDV_DD= 2.7V

300

100

µA

I_DDQ

Static supply current

µA

I_ADD

CLK & CLK <20 MHz or

Static supply current

100

PWRDWN = Low⁽⁴⁾

CLK and CLK

FBIN and FBIN

CLK and CLK

FBIN and FBIN

C_I

V_I= V_DDQor GND

2.5V

2.0

3.5

C_I(∆)

V_I= V_DDQor GND

2.5V

–0.25

0.25

Part to Part input Capacitance

Variation ⁽⁵⁾

∆C_I

Note:

4. Themaximumpower-downclockfrequencyisbelow20MHz.

5. Guaranteed by design, but not production tested.

PS8543A

07/29/02

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

ACSpecifications

Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )

AV , V

= 2.5V ±0.2V

DDQ

Parameter

Description

Diagram

Units

Min.

Nom.

Max

tjit(cc)

t(θ)

Cycle-to-cycle jitter

see Figure 3

see Figure 4

see Figure 5

see Figure 6

see Figure 7

see Figure 8

–75

–50

(1)

Static phase offset

tsk(o)

tjit(per)

tjit(hper)

tsl(i)

Output clock skew

Period jitter

100

–75

–100

1.0

Half-period jitter

Input clock slew rate

100

4.0

2.0

(2)

V/ns

tsl(o)

Output clock slew rate

1.0

The PLL on the PI6CV857L is capable of meeting all the above parameters while supporting SSC synthesizers with the following

(3)

parameters

SSC modulation frequency

SSC clock input frequency deviation

PLL loop bandwidth

30.00

0.00

50.00

–0.50

kHz

MHz

degrees

Phase angle

–0.031

Notes:

1. Static Phase offset does not include Jitter.

2. The slew rate is determined from the IBIS model with test load shown in Figure1.

3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.

PS8543A

07/29/02

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

V_CLK

R=60Ω

V /2

V_CLK

PI6CV857

Figure1.IBISModelOutputLoad

DDQ

C=14pF

Z=60Ω

R=1M Ω

R=120

Ω

C=1pF

Z=60Ω

GND

C=14pF

R=1M Ω

C=1pF

GND

PI6CV857L

PROBE

–V

DDQ

Figure2.OutputLoadTestCircuit

PS8543A

07/29/02

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

Yx,FBOUT

t_{cycle n}

t_jit(cc)t_{cycle n}

t_{cycle n+1}

Figure3.Cycle-to-CycleJitter

FBIN

t₍

)

n+1

n=N

t₍

∑

) n

(N is a large number of samples)

Figure 4. Static Phase Offset

Yx, FBOUT

t_sk(o)

Figure5.OutputSkew

PS8543A

07/29/02

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

Yx, FBOUT

t_{cycle n}

Yx, FBOUT

f_O

t _jit(per)

t_{cycle n}

Figure 6. Period Jitter

Yx, FBOUT

t _n+1

t_{half period n}

half period

f_O

2*f_O

t_jit(hper)

t_{half period n}

Figure7.Half-PeriodJitter

80%

V_ID

20%

Clock Inputs

and Outputs

t_sl(i),t_sl(o)

Figure8.InputandOutputSlewRates

PS8543A

07/29/02

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

PackagingMechanical:48-PinTSSOP

.236

.244

6.0

6.2

.488 12.4

.496 12.6

.047

1.20 Max

SEATING PLANE

0.09

0.20

.004

.008

0.45 .018

0.75 .030

.002

.006

0.05

0.15

.007

.010

.0197

BSC

.319

BSC

X.XX

DENOTES DIMENSIONS

IN MILLIMETERS

0.50

0.17

0.27

8.1

PackagingMechanical:48-PinTVSOP

.169

.177

4.30

4.50

0.09

0.20

.0035

.008

.031

.041

0.80

1.05

0.45 .018

0.75 .030

.252

BSC

6.4

.378 9.60

.386 9.80

SEATING

PLANE

Max.

.047

.002

.006

0.05

0.15

.016

BSC

.0051

.009

0.13

0.23

1.20

0.40

X.XX DENOTES DIMENSIONS

X.XX IN MILLIMETERS

OrderingInformation

Ordering Code

PI6CV857LA

PI6CV857LK

Package Name

Package Type

A48

K48

48-pin, 240-mil wide TSSOP

48-pin, 173-mil wide TVSOP

Pericom Semiconductor Corporation

2380BeringDrive • SanJose,CA95131•1-800-435-2336 • Fax(408)435-1100• http://www.pericom.com

PS8543A

07/29/02

PI6CV857LKX [PERICOM]

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