PI6LC48S04 [PERICOM]
HiFlex Serial Interface Clock;
| 型号： | PI6LC48S04 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | HiFlex Serial Interface Clock |
| 文件： | 总11页 (文件大小：1225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6LC48S04
HiFlex Serial Interface Clock
Features
Description
ꢀÎSelectable 250MHz, 156.25MHz, 125MHz or 100MHz output
e PI6LC48S04 is a 4-output clock synthesizer designed for se-
rial reference clock applications. e device generates four cop-
ies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz
clock signal with 0.34ps phase jitter performance. e four
outputs are organized in two banks of two LVDS and two low
power HCSL ouputs.e device supports 3.3V and 2.5V voltage
supplies and is packaged in a small 32-lead TQFN package.
clock synthesized from a 25MHz fundamental mode crystal
ꢀÎFour differential clock outputs (two LVDS and two low power
HCSL outputs)
ꢀÎCrystal interface designed for 25MHz, parallel resonant
crystal
ꢀÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.21ps (typical)
ꢀÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
Function Table
(12kHz - 20MHz): 0.32ps (typical)
ꢀÎPower supply noise rejection PSNR: -50dB (typical)
ꢀÎLVCMOS interface levels for the frequency select input
ꢀÎFull 3.3V or 2.5V supply voltage
Inputs
Output Frequency
F_SEL [1]
F_SEL [0]
with fXTAL = 25MHz
0 (default)
0 (default)
156.25MHz
125MHz
100MHz
250MHz
ꢀÎLead-free (RoHS 6) packaging
0
1
1
1
0
1
ꢀÎ-40°C to 85°C ambient operating temperature
Note: F_SEL[1:0] are asynchronous controls.
Pin Configuration
Block Diagram
32 31 30 29 28 27 26 25
XTAL_IN
V
DD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
VSWING_CTRL
1
0
QA0+
QA0-
LVDS
nc
GND
QA0-
OSC
0
1
: N
V
DDA
nc
XTAL_OUT
PFD
&
LPF
QA1+
QA1-
VCO
QA0+
LVDS
HCSL
HSCL
GND
REF_CLK
nOEA
VDDOA
Pulldown
REF_CLK
REF_SEL
QA1-
QB0+
QB0-
Pulldown
QA1+
: 25
Pulldown
Pulldown
Pulldown
Pulldown
VDD
17 GND
BYPASS
F_SEL[0:1]
nOEA
QB1+
QB1-
10 11 12 13 14 15 16
9
2
nOEB
VSWING_CTRL
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PI6LC48S04
HiFlex Serial Interface Clock
Pin Description
Pin #
Pin Name
Type
Description
1, 8, 13, 32
VDD
nc
Power
Unused
Power
Power
Core supply pins.
No connect.
2, 4
3
VDDA
GND
Analog power supply.
Power supply ground.
5, 17, 23, 25, 31
Alternative single-ended reference clock input. LVCMOS/LVTTL inter-
face levels.
6
7
9
REF_CLK
Input
Input
Input
Pulldown
Output enable input. See Table 3D for function. LVCMOS/LVTTL
interface levels.
n
OEA
Pulldown
Pulldown
Output enable input. See Table 3E for function. LVCMOS/LVTTL inter-
face levels.
nOEB
Reference select input. See Table 3B for function.
LVCMOS/LVTTL interface levels.
10
REF_SEL
Input
Input
Input
Input
Pulldown
11,
12
XTAL_IN,
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
XTAL_OUT
Bypass mode select pin. See Table 3C for function.
LVCMOS/LVTTL interface levels.
14
BYPASS
Pulldown
Pulldown
15,
F_SEL0,
F_SEL1
Frequency select pin. See Table 3A for function. LVCMOS/LVTTL
interface levels.
16
18, 19
20
QA1+, QA1- Output
VDDOA Power
Differential clock output. LVDS interface levels.
Output supply pin for QAx outputs.
21, 22
QA0+, QA0- Output
Differential clock output. LVDS interface levels.
Pull up
and Pull-
down
VSWING_
Input
VOH selection pin for low power HCSL outputs. Tri-level selction for
different voltage swings.
24
CTRL
26, 27
28
QB1-, QB1+ Output
Differential clock output. Low power HCSL interface levels.
Output supply pin for QBx outputs.
VDDOB
Power
29, 30
QB0-, QB0+ Output
Differential clock output. Low power HCSL interface levels.
NOTE: Pulldown refers to intetrnal input resistors.
Pin Characteristics
Symbol
Parameter
Test Condition
Minimum Typical
Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
100
kΩ
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PI6LC48S04
HiFlex Serial Interface Clock
Function Table
Output Divider and Output Frequency
Inputs
F_SEL [1]
F_SEL [0]
Operation
fOUT with fREF = 25MHz
0 (default)
0 (default)
fOUT = fREF * 25 ÷ 4
fOUT = fREF * 5
156.25MHz
125MHz
100MHz
250MHz
0
1
1
1
0
1
fOUT = fREF * 4
fOUT = fREF * 10
Note: F_SEL[1:0] are asynchronous controls.
PLL Reference Clock Select Fuction Table
Input
REF_SEL
Operation
0 (default)
1
e crystal interface is selected as reference clock
e REF_CLK input is selected as reference clock
NOTE: REF_SEL is an asynchronous control.
PLL BYPASS Function Table
Input
BYPASS
Operation
PLL is enabled. e reference frequency is multiplied by the PLL feedback divider of 25 and then divided by the
selected output divider N.
0 (default)
PLL is bypassed. e reference frequency is divided by the selected output divider N. AC specifications do not
apply in PLL bypass mode.
1
NOTE: BYPASS is an asynchronous control.
nOEA Output Enable Function Table
Input
nOEA
Operation
0 (default)
1
QA0+, QA0- and QA1+, QA1- outputs are enabled
QA0+, QA0- and QA1+, QA1- outputs are disabled (high-impedance)
NOTE: nOEA is an asynchronous control.
nOEB Output Enable Function Table
Input
nOEB
Operation
0 (default)
1
QB0+, QB0- and QB1+, QB1- outputs are enabled
QB0+, QB0- and QB1+, QB1- outputs are disabled (high-impedance)
NOTE: nOEB is an asynchronous control.
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HiFlex Serial Interface Clock
Table 3: VSWING_CTRL Select Table
VSWING_CTRL
Output Amplitude (V)
0
0.63
0.75
0.87
Open (default)
1
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HiFlex Serial Interface Clock
Maximum Ratings
Note:
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. ese
ratings are stress specifications only. Functional operation of
the product at these conditions or any conditions beyond those
listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Supply Voltage, VDD, VDDA, VDDOx.............................4.6V
Inputs ............................................. -0.5V to VDD + 0.5V
Storage Temperature, TSTG .................... -65oC to 150oC
Inputs (Referenced to GND)..........-0.5 to VDD+0.5V
Clock Output (Referenced to GND) ............-0.5 to 2V
Latch up .............................................................. .200mA
ESD Protection (Input)..................2000 V min (HBM)
DC Electrical Characteristics
Power Supply DC Characteristics (VDD = VDDOA = VDDOB = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C)
Symbol
Parameter
Test Condition
Min.
Typ.
3.3
Max.
3.465
2.625
VDD
Units
3.135
V
V
V
Core Supply Voltage
VDD
2.375
2.5
VDD – 0.30
3.3
Output Supply Voltage
Output Supply Voltage
VDDA
VDD – 0.30
3.135
2.5
3.3
2.5
VDD
3.465
2.625
30
V
V
VDDOA&B
2.375
V
Analog Supply Current
Power Supply Current
Output Supply Current
mA
mA
mA
IDDA
25
IDD
72
IDDOA&B
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PI6LC48S04
HiFlex Serial Interface Clock
LVCMOS/LVTTL Input DC Characteristics (VDD = VDDOA = VDDOB = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C)
Symbol Parameter
Test Condition
Min. Typ. Max.
Units
VDD = 3.3V
VDD = 2.5V
VSWING_CTRL @ VDD= 3.3V and VDD
2.5V
2
VDD + 0.3
V
V
VIH
Input High Voltage
1.7
VDD + 0.3
x
VDD + 0.3
V
0.7
VDD = 3.3V
VDD = 2.5V
-0.3
-0.3
0.8
0.7
V
V
VIL
Input Low Voltage
VSWING_CTRL @ VDD= 3.3V and GND
VDD x 0.3
V
2.5V
- 0.3
nOEA, nOEB, BYPASS, REF_SEL,
REF_CLK, F_SEL[1:0]
150
150
μA
μA
Input High
Current
IIH
VDD = VIN = 2.625V or 3.465V
VSWING_CTRL with VIN = VDD
nOEA, nOEB,
BYPASS, REF_SEL, REF_CLK,
F_SEL[1:0]
-5
μA
μA
Input Low
Current
IIL
VDD = 2.625V or 3.465V, VIN = 0V
VSWING_CTRL with VIN = 0V
-150
LVDS DC Characteristics (VDD = VDDOA = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Units
VOD
∆VOD
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
454
50
mV
mV
V
VOS
1.125
1.375
50
∆VOS
VOS Magnitude Change
mV
Crystal Characteristics
Parameter
Test Condition
Min.
Typ.
Max.
Units
Mode of Oscillation
Frequency
Fundamental
25
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
80
7
pF
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PI6LC48S04
HiFlex Serial Interface Clock
AC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
F_SEL [1:0] = 00
156.25
125
MHz
MHz
MHz
MHz
MHz
F_SEL [1:0] = 01
Output Frequency
Reference Frequency
fOUT
F_SEL [1:0] = 10
100
F_SEL [1:0] = 11
250
25
REF_CLK
fREF
156.25MHz, Integration Range:
1MHz – 20MHz
0.21
0.32
0.21
0.32
ps
ps
ps
ps
156.25MHz, Integration Range:
12kHz – 20MHz
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
125MHz, Integration Range:
1MHz – 20MHz
125MHz,Integration Range:
12kHz – 20MHz
156.25MHz, Offset: 100Hz
156.25MHz, Offset: 1kHz
156.25MHz, Offset: 10kHz
156.25MHz, Offset: 100kHz
From DC to 50MHz
-91.6
-120.8
-132.2
-135.0
-50
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dB
ΦN
Single-Side Band Noise Power
PSNR
tsk(o)
Power Supply Noise Rejection
Output Skew
Between QAx+/QAx- & QBx+/
QBx-
NOTE 2, 3
NOTE 3, 4
1.8
2.7
ns
tsk(b)
tR / tF
tLOCK
Bank Skew
55
ps
Output Rise/Fall Time
PLL Lock Time
QAx+, QAx- 20% to 80%
100
400
20
ps
ms
Ring-back Voltage Margin;
NOTE 5, 6
VRB
QBx+, QBx-
QBx+, QBx-
QBx+, QBx-
QBx+, QBx-
QBx+, QBx-
-100
500
100
mV
ps
Time before VRB is Al-
lowed; NOTE 5, 6
tSTABLE
VMAX
VMIN
VCROSS
Absolute Maximum Output
Voltage; NOTE 7, 8
1150
mV
mV
mV
Absolute Minimum Output
Voltage; NOTE 7, 9
-300
250
Absolute Crossing Voltage;
NOTE 7, 10, 11
550
140
Total Variation of VCROSS
over all edges; NOTE 7, 10, QBx+, QBx-
12
∆
VCROSS
mV
Measured between
-150mV to 150mV
Rise/Fall Edge Rate; NOTE
QBx+, QBx-
0.6
47
5.5
53
V/ns
%
5, 13
odc
Output Duty Cycle
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HiFlex Serial Interface Clock
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when
the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. e device will meet specifications
aꢀer thermal equilibrium has been reached under these conditions.
NOTE: Characterized using a 25MHz crystal.
NOTE 1: Please refer to the phase noise plots.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output
differential cross points.
NOTE 3: is parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 5: Measurement taken from differential waveform.
NOTE 6: TSTABLE is the time the differential clock must maintain a minimum 150mV differential voltage aꢀer rising/falling
edges before it is allowed to drop back into the VRB 100mV differential range.
NOTE 7: Measurement taken from single ended waveform.
NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
See Parameter Measurement Information Section.
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to
all crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of rising Q and falling nQ. is is the maximum allowed variance in
the VCROSS for any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). e signal must be
monotonic through the measurement region for rise and fall time. e 300mV measurement window is centered on the differential
zero crossing.
Configuration test load board termination for low power HCSL Outputs
Clock
5 inches
TLA
PI6LC48S04
Clock#
5 inches
TLB
2pF
5%
2pF
5%
Configuration Test Load Board Termination
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PI6LC48S04
HiFlex Serial Interface Clock
Power Supply Filtering Techniques
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. e PI6LC48S04 provides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and
0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin.
3.3V or 2.5V
V
DD
0.1µF
10Ω *
V
DDA
0.1µF
10µF
* If VDD is 2.5V, the resistor value will be diꢀerent, see app note for details
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PI6LC48S04
HiFlex Serial Interface Clock
Crystal Input Interface
e clock generator has been characterized with 18pF parallel resonant crystals. e capacitor values shown in the figure below
were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
18pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
18pF
LVCMOS to XTAL Interface
e XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram
is shown in the figure below. e XTAL_OUT pin can be leꢀ floating. e input edge rate can be as slow as 10ns. For LVCMOS
signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with
the power rail and to reduce noise. is configuration requires that the output impedance of the driver (Ro) plus the series resis-
tance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in
half. is can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most
50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the
crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal.
VDD
VDD
R1
0.1µF
Rs
Ro
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Thermal Information
Symbol
QJA
Description
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
44.7 OC/W
21.7OC/W
QJC
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PI6LC48S04
HiFlex Serial Interface Clock
Packaging Mechanical:
Notes:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
3. Refer JEDEC MO-220
DATE: 06/30/11
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area (mesh stencile design is recommended)
DESCRIPTION: 32-contact, Thin Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH32
DOCUMENT CONTROL #: PD-2070
REVISION: B
Ordering Information
Ordering Code
Package Code
Package Type
PI6LC48S04ZHIE
PI6LC48S04ZHIEX
ZH
ZH
Pb-free & Green, 32-pin TQFN
Pb-free & Green, 32-pin TQFN, Tape & Reel
Notes:
1. ermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. “E” denotes Pb-free and Green
3. Adding an “X” at the end of the ordering code denotes tape and Reel packaging
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