PI6PCIEB24ZDEX [PERICOM]

PLL Based Clock Driver, PI6 Series, 8 True Output(s), 0 Inverted Output(s), 4 X 4 MM, 0.75 MM HEIGHT, GREEN, MO-220, TQFN-20;
PI6PCIEB24ZDEX
型号: PI6PCIEB24ZDEX
厂家: PERICOM SEMICONDUCTOR CORPORATION    PERICOM SEMICONDUCTOR CORPORATION
描述:

PLL Based Clock Driver, PI6 Series, 8 True Output(s), 0 Inverted Output(s), 4 X 4 MM, 0.75 MM HEIGHT, GREEN, MO-220, TQFN-20

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PI6PCIEB24  
1:4 PCI Express® Clock Driver  
Features  
Description  
Î Phase jitter filter for PCIe® 2.0 application  
Î Four pairs of HCSL PCIe 2.0 Differential Clocks  
Î Prop delay < 2ꢀ0ps (in PLL mode)  
Î Low skew < ꢀ0ps  
Pericom Semiconductor's PI6PCIEB24 is a PCI Express® (PCIe)  
2.0 compliant high-speed, low-noise differential clock buffer. e  
device distributes the input differential PCIe clock to four differ-  
ential pairs of clock outputs with zero delay PLL.  
Î Low jitter < ꢀ0ps cycle-to-cycle  
Î < 1 ps additive RMS phase jitter  
Î 100 MHz PLL Mode operation  
Î 3.3V operation  
Î Packaging (Pb-free and Green):  
à 20-Pin 4.0mm x 4.0mm x0.7ꢀmm TQFN (ZD20)  
Block Diagram  
Pin Configuration  
OE_0  
OUT0  
OUT0#  
OUT1  
OUT1#  
1
2
3
4
5
15  
14  
13  
12  
11  
VDD  
OUT0  
OUT0#  
OE_0  
OUT3  
OUT3#  
OE_3  
OUT2  
OUT2#  
SRC  
SRC#  
OUT2  
OUT2#  
OUT3  
OUT3#  
OUT1  
OE_3  
PWRDWN#  
PLL  
PLL/BYPASS#  
www.pericom.com  
PS9070A  
09/01/10  
10-0210  
1
PI6PCIEB24  
1:4 PCI Express® Clock Driver  
Pin Descriptions  
Pin Name  
Type  
Pin No  
Description  
SRC & SRC#  
Input  
19, 20  
0.7V Differential SRC input from PI6C410 clock synthesizer  
OUT[0:3] & OUT[0:3]# Output  
2, 3, ꢀ, 6, 12, 11, 1ꢀ, 14 0.7V Differential outputs  
IREF  
Input  
Power  
Input  
Power  
Input  
Input  
16  
External resistor connection to set the differential output current  
V
1, 7, 10, 18  
3.3V Power Supply for Outputs  
DD  
PWRDWN#  
VDD_A  
9
3.3V LVTTL active LOW input for power down operation  
3.3V Power Supply for PLL  
17  
8
PLL/BYPASS#  
OE_0, OE_3  
When HIGH, PLL is enabled, When LOW, PLL is bypassed.  
When HIGH, enables corresponding OUT0, OUT3 respectively.  
4, 13  
Ground connection is through the package metal plate underneath.  
www.pericom.com  
PS9070A  
09/01/10  
10-0210  
2
PI6PCIEB24  
1:4 PCI Express® Clock Driver  
Functionality  
PWRDWN#  
OUT  
OUT#  
1
0
Normal  
Normal  
Low  
I
× 2  
REF  
Power Down (PWRDWN# assertion)  
PWRDWN#  
OUT  
OUT#  
Figure 1. Power down sequence  
When PWRDWN# is asserted (Low), 2xI  
current flows through OUT pin.  
REF  
Power Down (PWRDWN# De-assertion)  
Tstable  
<1ms  
PWRDWN#  
OUT  
OUT#  
Tdrive_PwrDwn#  
<300us, >200mV  
Figure 2. Power down de-assert sequence  
www.pericom.com  
PS9070A  
09/01/10  
10-0210  
3
PI6PCIEB24  
1:4 PCI Express® Clock Driver  
Current-mode output buffer characteristics of OUT[0:3], OUT[0:3]#  
VDD  
(3.3V 5ꢀ%  
Slope ~ 1/Rs  
RO  
IOUT  
ROS  
Iout  
0V  
0.85V  
VOUT = 0.85V max  
Figure 2. Simplified diagram of current-mode output buffer  
Differential Clock Buffer characteristics  
Symbol  
Minimum  
Maximum  
R
R
3000Ω  
N/A  
O
unspecified  
N/A  
unspecified  
8ꢀ0mV  
OS  
V
OUT  
Current Accuracy  
Symbol  
Conditions  
Configuration Load  
Min.  
Max.  
R
= 47ꢀΩ 1%  
= 2.32mA  
Nominal test load for given  
configuration  
REF  
REF  
I
V
= 3.30 ꢀ%  
-12% I  
+12% I  
OUT  
DD  
NOMINAL  
NOMINAL  
I
I
refers to the expected current based on the configuration of the device.  
NOMINAL  
Differential Clock Output Current  
Board Target Trace/Term Z  
Reference R, Iref = V /(3xRr) Output Current  
V
OH  
@ Z  
DD  
100Ω  
R
= 47ꢀΩ 1%,  
= 2.32mA  
REF  
REF  
I
= 6 x I  
0.7V @ ꢀ0  
REF  
OH  
(100Ω differential 1ꢀ% coupling ratio)  
I
www.pericom.com  
PS9070A  
09/01/10  
10-0210  
4
PI6PCIEB24  
1:4 PCI Express® Clock Driver  
Absolute Maximum Ratings (Over operating free-air temperature range)  
Symbol  
Parameters  
Min.  
Max.  
Units  
V
V
V
V
3.3V Core Supply Voltage  
3.3V I/O Supply Voltage  
Input High Voltage  
Input Low Voltage  
-0.ꢀ  
-0.ꢀ  
4.6  
4.6  
4.6  
DD_A  
DD  
IH  
V
-0.ꢀ  
-6ꢀ  
IL  
Ts  
Storage Temperature  
ESD Protection  
1ꢀ0  
°C  
V
V
2000  
ESD  
Stress beyond those listed under Absolute Maximum Ratings” may cause permanent damage to the device.  
DC Electrical Characteristics (V = 3.3±5%, V  
= 3.3±5%)  
DD_A  
DD  
Symbol Parameters  
Condition  
Min.  
Max.  
Units  
V
V
V
V
3.3V Core Supply Voltage  
3.3V I/O Supply Voltage  
3.3V Input High Voltage  
3.3V Input Low Voltage  
Input Leakage Current  
3.13ꢀ  
3.13ꢀ  
2.0  
3.46ꢀ  
3.46ꢀ  
DD_A  
DD  
IH  
V
V
V
+ 0.3  
DD  
DD  
V
SS  
– 0.3  
0.8  
+ꢀ  
IL  
I
0 < V < V  
IN  
-ꢀ  
μA  
IK  
DD  
I
I
= 6 x I  
,
12.2  
REF  
OH  
I
Output High Current  
mA  
OH  
= 2.32mA  
1ꢀ.6  
REF  
C
C
Input Pin Capacitance  
Output Pin Capacitance  
Pin Inductance  
3
IN  
OUT  
PIN  
DD  
SS  
pF  
6
L
7
nH  
mA  
°C  
I
I
Power Supply Current  
Power Down Current  
Ambient Temperature  
V
= 3.46ꢀV, F  
= 100MHz  
200  
40  
8ꢀ  
DD  
CPU  
Driven outputs  
T
-4ꢀ  
A
www.pericom.com  
PS9070A  
09/01/10  
10-0210  
PI6PCIEB24  
1:4 PCI Express® Clock Driver  
AC Switching Characteristics (V = 3.3±5%, VDD = 3.3±5%)  
DD  
_A  
Symbol  
Parameters  
Min  
Max.  
Units Notes  
F
9ꢀ  
10ꢀ  
700  
12ꢀ  
20  
MHz  
IN  
T
/ T  
Rise and Fall Time (measured between 0.17ꢀV to 0.ꢀ2ꢀV)  
Rise and Fall Time Variation  
17ꢀ  
ps  
2
2
2
rise fall  
ps  
DT  
/ DT  
fall  
rise  
Rise/Fall Matching  
%
T
PLL Mode (PLL/BYPASS# = 1)  
Cycle – Cycle Jitter  
2ꢀ0  
ꢀ0  
ps  
pd  
T
jitter  
ps  
3, 4  
2
V
V
Voltage High including overshoot  
Voltage Low including undershoot  
Absolute crossing point voltages  
Total Variation of Vcross over all edges  
Duty Cycle  
660  
-300  
2ꢀ0  
11ꢀ0  
mV  
mV  
mV  
mV  
%
HIGH  
LOW  
2
V
cross  
ΔV  
ꢀꢀ0  
140  
ꢀꢀ  
2
2
cross  
T
T
4ꢀ  
3
DC  
Additive RMS phase jitter for PCIe GenII  
Bypass mode (PLL/BYPASS# = 0)  
<0  
2.ꢀ  
1
ps  
jadd  
T
6.ꢀ  
ns  
pd(bypass)  
1. Test configuration is R = 33.2Ω, Rp = 49.9Ω, and 2pF.  
s
2. Measurement taken from Single Ended waveform.  
3. Measurement taken from Differential waveform.  
4. Measurement taken using M1 data capture analysis tool.  
2
2
ꢀ. Additive jitter is calculated from input and output RMS phase jitter using PCIe 2.0 filter by T  
= (output jitter) – (input jitter)  
jadd  
Configuration Test Load Board Termination  
Rs  
33Ω  
5%  
OUT  
TLA  
TLB  
Rs  
33Ω  
5%  
PI6PCIEB24  
OUT#  
2pF  
5%  
2pF  
5%  
Rp  
49.9Ω  
1%  
Rp  
49.9Ω  
1%  
475Ω  
1%  
www.pericom.com  
PS9070A  
09/01/10  
10-0210  
6
PI6PCIEB24  
1:4 PCI Express® Clock Driver  
Packaging Mechanical: 20-Pin TQFN (ZD)  
DATE: 09/11/08  
DESCRIPTION: 20-Lead, Thin Fine Pitch Quad Flat No-Lead (TQFN)  
ZD20  
DOCUMENT CONTROL #: PD-2084  
PACKAGE CODE:  
REVISION: --  
08-0456  
(1-3)  
Ordering Information  
Ordering Code  
Package Code  
Package Description  
PI6PCIEB24ZDE  
ZD  
20-pin, 4.0mm x 4.0mm, TQFN, Pb-Free and Green  
1. ermal characteristics can be found on the company web site at www.pericom.com/packaging/  
2. E = Pb-free and Green  
3. Adding an X suffix = Tape/Reel  
Pericom Semiconductor Corporation • 1-800-435-2336  
www.pericom.com  
PS9070A  
09/01/10  
10-0210  
7
PCI Express and PCIe are registered trademarks of PCI-SIG. Please visit pcisig.org for information.  

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