PI6ULS5V9509WE [PERICOM]
Level Translating SMBus Repeater with Tiny Package;
| 型号： | PI6ULS5V9509WE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Level Translating SMBus Repeater with Tiny Package |
| 文件： | 总10页 (文件大小：628K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6ULS5V9509
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Level Translating I2C-Bus/SMBus Repeater with Tiny Package
Features
Description
Bidirectional buffer isolates capacitance and allows
400 pF on port B of the device
The PI6ULS5V9509 is a level translating I2C-
bus/SMBus repeater. It can provide bidirectional level
translation between low voltage (down to 1.1V) and
higher voltage (2.5V to 5.5V) in mixed-mode
applications. And it enables I2C and similar bus system
to be extended, without degradation of performance
even during level shifting.
Port A operating supply voltage range of 1.1 V to
VCC(B) - 1.0V
Port B operating supply voltage range of 2.5 V to
5.5 V
Voltage level translation from 1.1V to VCC(B)
1.0V and from 2.5 V to 5.5 V
-
The PI6ULS5V9509 enables the system designer to
isolate two halves of a bus for both voltage and
capacitance, accommodating more I2C devices or longer
trace length. It also permits extension of the I2C-bus by
providing bidirectional buffering for both the data (SDA)
and the clock (SCL) lines, thus allowing two buses of
400 pF to be connected in an I2C application.
The bus port B drivers are compliant with SMBus
I/O levels, while port A uses a current sensing
mechanism to detect the input or output LOW signal
which prevents bus lock-up. Port A uses a 1 mA current
source for pull-up and a 200Ω pull-down driver. This
result in a LOW on the port A accommodating smaller
voltage swings. The output pull-down on the port A
internal buffer LOW is set for approximately 0.2V,
while the input threshold of the internal buffer is set
about 50 mV lower than that of the output voltage LOW.
When the port A I/O is driven LOW internally, the LOW
is not recognized as a LOW by the input. This prevents a
lock-up condition from occurring. The output pull-down
on the port B drives a hard LOW and the input level is
set at 0.3 of SMBus or I2C-bus voltage level which
enables port B to connect to any other I2C-bus devices or
buffer.
Requires no external pull-up resistors on lower
voltage port A
Open-drain port B inputs/outputs
Lock-up free operation
Supports arbitration and clock stretching across the
repeater
Accommodates Standard-mode and Fast-mode I2C-
bus devices and multiple masters
Powered-off high-impedance I2C-bus pins
5 V tolerant B SCL, SDA and enable pins
0 Hz to 400 kHz clock frequency (Remark: The
maximum system operating frequency may be less
than 400 kHz because of the delays added by the
repeater.)
ESD protection exceeds 8KV HBM per JESD22-
A114
Package: MSOP-8, SOIC-8 and UQFN1.6x1.6-8L
Pin Configuration
The PI6ULS5V9509 drivers are not enabled unless
VCC(A) is above 0.8 V and VCC(B) is above 2.5 V. The
enable (EN) pin can also be used to turn the drivers on
and off under system control. Caution should be
observed to only change the state of the EN pin when the
bus is idle.
SOIC-8 and MSOP-8
Pin Description
Pin No Pin Name
Description
1
2
3
4
5
6
7
8
VCC(A)
A1
A2
GND
EN
B2
port A supply voltage
port A (lower voltage side)
port A (lower voltage side)
supply ground (0 V)
active HIGH repeater enable input
port B (SMBus/I2C-bus side)
port B (SMBus/I2C-bus side)
port B supply voltage
B1
VCC(B)
UQFN1.6x1.6-8L(Top View)
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PI6ULS5V9509
Level Translating I2C-Bus/SMBus
Repeater with Tiny Package
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Block Diagram
EN
H
Function
A1 = B1;
A2= B2;
L
disabled
Figure 1: Block Diagram
Maximum Ratings
Note:
o
o
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
StorageTemperature...................................................................................-55 Cto+125 C
SupplyVoltageportB......................................................................................-0.5Vto+6.0V
SupplyVoltageportA......................................................................................-0.5Vto+6.0V
DCInputVoltage .............................................................................................-0.5Vto+6.0V
ControlInputVotage(EN)...............................................................................-0.5Vto+6.0V
TotalPowerDissipation...................................................................100mA
Input/OutputCurrent(portA&B).........................................................20mA
InputCurrent (EN,VCC(A),VCC(B),GND)...............................................20mA
ESD:HBMMode...........................................................................................................8000V
Recommended operation conditions
GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified
Symbol
Vcc(B)
Parameter
Test Conditions
Min
2.5
Typ[1]
-
Max
Unit
V
supply voltage port B
supply voltage port A
-
-
5.5
Vcc(A)
1.1
VCC(B) -1.0
V
-
all port A static HIGH
all port A static LOW
all port B static HIGH
0.25
1.25
0.5
0.45
3.0
0.9
0.9
5
ICC(A)
supply current on pin VCC(A)
supply current on pin VCC(B)
mA
mA
ICC(B)
Note:
1.1
[1] Typical values with VCC(A) = 1.1 V, VCC(B) = 5 V.
2015-04-0005
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PI6ULS5V9509
Level Translating I2C-Bus/SMBus
Repeater with Tiny Package
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DC Electrical Characteristics
GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified
Parameter
Description
Test Conditions
Min
Typ[1]
Max
Unit
Input and output of port A (A1&A2)
VIH
HIGH-level input voltage
LOW-level input voltage
-
-
0.7VCC(A)
-0.5
-
-
VCC(A)
+0.3
V
[2]
VIL
contention LOW-level input
voltage
VILc
VIK
-
−0.5
+0.15
-
-
V
V
input clamping voltage
IL= -18 mA
VI = VCC(A)
-1.5
-0.5
ILI
IIL
input leakage current
-
-
±1
μA
LOW-level input current
LOW-level output voltage
SDA, SCL; VI = 0.2 V
VCC(A) = 0.95 V to 1.2V
-1.5
-1.0
0.18
0.2
-0.45
0.25
0.3
mA
-
-
VOL
V
VCC(A) = > 1.2V to
(VCC(B) − 1 V)
difference between LOW-level
output and LOW-level input
voltage contention
VOL-VILc
guaranteed by design
-
50
-
mV
HIGH-level output leakage
current
ILOH
Cio
VO = VCC(A)
-
-
-
-
10
-
μA
input/output capacitance
6
pF
Input and output of port B (B1&B2)
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
0.7VCC(B)
-0.5
-
-
VCC(B)
-
V
+0.3
VCC(B)
-
VIK
ILI
input clamping voltage
input leakage current
LOW-level input current
II = -18 mA
VI = 3.6 V
VI = 0.2 V
-1.5
-1
-
-
-
-0.5
1
V
μA
μA
IIL
-
10
VOL
LOW-level output voltage
IOL = 6 mA
-
0.1
0.2
V
HIGH-level output leakage
current
ILOH
Cio
VO = 3.6 V
-
-
-
-
10
-
μA
input/output capacitance
3
pF
Enable
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
-
-
0.9VCC(A)
-0.5
-
-
VCC(B)
V
V
+0.1
VCC(A)
VI = 0.2 V, EN;
VCC = 3.6 V
IIL
ILI
Ci
LOW-level input current
input leakage current
input capacitance
-1
-1
-
-
-
+1
+1
-
μA
μA
pF
VI = VCC
VI = 3.0 V or 0V
2
Note:
1. Typical values with VCC(A) = 1.1 V, VCC(B) = 5 V.
2. VIL specification is for the falling edge seen by the port A input. VILC is for the static LOW levels seen by the port A input
resulting in port B output staying LOW.
2015-04-0005
PT0460-3
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PI6ULS5V9509
Level Translating I2C-Bus/SMBus
Repeater with Tiny Package
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Dynamic characteristics
VCC(A) = 1.1 V; VCC(B) = 3.3 V [1]
Symbol
tPLH
tPHL
Parameter
Test Conditions
port B to port A
port B to port A
Min
-
-
Typ
65
25
Max
216
140
Unit
ns
ns
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
LOW to HIGH output transition
time
tTLH
port A
14
22
96
ns
HIGH to LOW output transition
time
LOW to HIGH propagation delay
tTHL
tPLH
port A
-
-
20
-
ns
ns
port A to port B
-69
-139
port A to port B; measured from
the 50 % of initial LOW on port A
to 1.5 V rising on port B
t
LOW to HIGH propagation delay
-
100
226
ns
PLH 2
tPHL
HIGH to LOW propagation delay port A to port B
20
-
50
61
183
-
ns
ns
[2]
LOW to HIGH output transition
port B
tTLH
time
HIGH to LOW output transition
time
set-up time
tTHL
port B
EN HIGH before START condition
1
2
40
ns
tsu
th
100
100
-
-
-
-
ns
ns
hold time
EN HIGH after STOP condition
VCC(A) = 1.9 V; VCC(B) = 5.0 V [1]
Symbol
tPLH
tPHL
Parameter
Test Conditions
Min
-
-
Typ
75
20
Max
216
140
Unit
ns
ns
LOW-to-HIGH propagation delay port B to port A
HIGH-to-LOW propagation delay port B to port A
LOW to HIGH output transition
time
HIGH to LOW output transition
time
tTLH
port A
port A
14
27
96
ns
tTHL
tPLH
-
-
20
-
ns
ns
LOW to HIGH propagation delay port A to port B
-69
-139
port A to port B; measured from
tPLH2
tPHL
LOW to HIGH propagation delay the 50 % of initial LOW on port A
to 1.5 V rising on port B
-
91
226
ns
HIGH to LOW propagation delay
port A to port B
20
-
50
65
183
-
ns
ns
[2]
LOW to HIGH output transition
time
port B
tTLH
HIGH to LOW output transition
time
tTHL
port B
1
2
40
ns
tsu
th
set-up time
EN HIGH before START condition
EN HIGH after STOP condition
100
100
-
-
-
-
ns
ns
hold time
Note:
[1] Load capacitance = 50 pF; load resistance on port B = 1.35 k
[2] Value is determined by RC time constant of bus line
Figure 2: Propagation Delay and Transition Times BA
Figure 3: Propagation Delay and Transition Times AB
2015-04-0005
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PI6ULS5V9509
Level Translating I2C-Bus/SMBus
Repeater with Tiny Package
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Figure 4: Propagation delay from the port A’s external driver switching off to port B LOW-to-HIGH transition; (AB)
Figure 5: Test Circuit
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PI6ULS5V9509
Level Translating I2C-Bus/SMBus
Repeater with Tiny Package
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Functional Description
The PI6ULS5V9509 is a level translating I2C-bus/SMBus repeater. It can provide bidirectional level translation
between low voltage (down to 1.1V) and higher voltage (2.5V to 5.5V) in mixed-mode applications. And it enables
I2C and similar bus system to be extended, without degradation of performance even during level shifting.
The PI6ULS5V9509 enables the system designer to isolate two halves of a bus for both voltage and capacitance,
accommodating more I2C devices or longer trace length. It also permits extension of the I2C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus allowing two buses of 400 pF to be
connected in an I2C application.
The bus port B drivers are compliant with SMBus I/O levels, while port A uses a current sensing mechanism to
detect the input or output LOW signal which prevents bus lock-up. Port A uses a 1 mA current source for pull-up and
a 200Ω pull-down driver. This result in a LOW on the port A accommodating smaller voltage swings. The output
pull-down on the port A internal buffer LOW is set for approximately 0.2 V, while the input threshold of the internal
buffer is set about 50 mV lower than that of the output voltage LOW. When the port A I/O is driven LOW internally,
the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-
down on the port B drives a hard LOW and the input level is set at 0.3 of SMBus or I2C-bus voltage level which
enables port B to connect to any other I2C-bus devices or buffer.
The PI6ULS5V9509 drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above 2.5 V. The enable
(EN) pin can also be used to turn the drivers on and off under system control. Caution should be observed to only
change the state of the EN pin when the bus is idle.
Application Information
A typical application is shown in Figure 6. In this example, the system master is running on a 1.1 V I2C-bus while
the slave is connected to a 3.3 V bus. Both buses run at 400 kHz. Master devices can be placed on either bus.
When port B of the PI6ULS5V9509 is pulled LOW by a driver on the I2C-bus, a CMOS hysteresis detects the
falling edge when it goes below 0.3VCC(B) and causes the internal driver on port A to turn on, causing port A to pull
down to about 0.2 V. When port A of the PI6ULS5V9509 falls, first a comparator detects the falling edge and causes
the internal driver on port B to turn on and pull the port B pin down to ground. In order to illustrate what would be
seen in a typical application, refer to Figure 7 and Figure 8. If the bus master in Figure 6 were to write to the slave
through the PI6ULS5V9509, waveforms shown in Figure 7 would be observed on the B bus. This looks like a normal
I2C-bus transmission.
On the A bus side of the PI6ULS5V9509, the clock and data lines would have a positive offset from ground equal
to the VOL of the PI6ULS5V9509. After the eighth clock pulse, the data line will be pulled to the VOL of the master
device, which is very close to ground in this example. At the end of the acknowledge, the level rises only to the LOW
level set by the driver in the PI6ULS5V9509 for a short delay while the B bus side rises above 0.5 VCC(B), then it
continues HIGH. It is important to note that any arbitration or clock stretching events require that the LOW level on
the A bus side at the input of the PI6ULS5V9509 (VIL) is below VILC to be recognized by the PI6ULS5V9509 and then
transmitted to the B bus side.
2015-04-0005
PT0460-3
04/20/15
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PI6ULS5V9509
Level Translating I2C-Bus/SMBus
Repeater with Tiny Package
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PI6ULS5V9509
Figure 6: Typical Application
Figure 7: Bus B I2C/SMBusWaveform
VOL of PI6ULS=5V9509
Figure 8: Bus A Lower Voltage Waveform
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PI6ULS5V9509
Level Translating I2C-Bus/SMBus
Repeater with Tiny Package
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Mechanical Information
MSOP-8L
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PI6ULS5V9509
Level Translating I2C-Bus/SMBus
Repeater with Tiny Package
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UQFN1.6x1.6-8L
2015-04-0005
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PI6ULS5V9509
Level Translating I2C-Bus/SMBus
Repeater with Tiny Package
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SOIC-8L
Ordering Information
Part No.
Package Code
Package
PI6ULS5V9509UE
PI6ULS5V9509UEX
PI6ULS5V9509WE
PI6ULS5V9509WEX
PI6ULS5V9509XTEX
U
U
Lead free and Green 8-pin MSOP
Lead free and Green 8-pin MSOP, Tape & Reel
Lead free and Green 8-pin SOIC
W
W
XT
Lead free and Green 8-pin SOIC, Tape & Reel
Lead free and Green UQFN1.6x1.6-8L,
Tape & Reel
Note:
E = Pb-free
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
2015-04-0005
PT0460-3
04/20/15
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