PI74ALVCH162260 [PERICOM]
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-STATE Outputs; 12位至24位复用D类锁存器与三态输出
| 型号： | PI74ALVCH162260 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-STATE Outputs |
| 文件： | 总5页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI74ALVCH162260
12-Bit To 24-Bit Multiplexed D-Type Latch
with 3-STATE Outputs
ProductDescription
Product Features
PericomSemiconductor’sPI74ALVCHseriesoflogiccircuitsare
produced in the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
• PI74ALVCH162260 is designed for low voltage operation
• V = 2.3V to 3.6V
CC
• Hysteresis on all inputs
ThePI74ALVCH162260isa12-bitto24-bitmultiplexedD-type
latch designed for 2.3V to 3.6 VCC operation. It is used in
applicationswheretwoseparatedatapathsmustbemultiplexed
onto, or demultiplexed from, a single data path.
• Typical V
(Output Ground Bounce)
OLP
< 0.8V atV = 3.3V, T = 25°C
CC
A
• Typical V
(Output V Undershoot)
OH
OHV
< 2.0V atV = 3.3V, T = 25°C
CC
A
Typical applications include multiplexing and/or demulti-
plexing address and data information in microprocessor or
bus-interface applications. This device is also useful in
memory-interleavingapplications.
• Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
Three12-bitI/Oports(A1-A12,1B1-1B12,and2B1-2B12)are
available for address and/or data transfer. The output-enable
(OE1B, OE2B, and OEA) inputs control the bus transceiver
functions.TheOE1BandOE2Bcontrolsignalsalsoallowbank
control in the A-to-B direction.
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Address and/or data information can be stored using the
internalstoragelatches.Thelatch-enable(LE1B,LE2B,LEA1B,
andLEA2B)inputsareusedtocontroldatastorage. Whenthe
latch-enableinputisHIGH, thelatchistransparent. Whenthe
latch-enable input goes LOW, the data present at the inputs
is latched and remains latched until the latch-enable input is
returnedHIGH.
Logic Block Diagram
2
LE1B
27
LE2B
30
LEA1B
55
LEA2B
56
OE2B
To reduce overshoot and undershoot, the B-port outputs
include 26Ω series resistors.
29
OE1B
1
Toensurethehigh-impedancestateduringpoweruporpower
down, OE should be tied to Vcc through a pullup resistor, the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
OEA
28
SEL
G1
C1
1D
23
8
1
1
1
B
1
1
A1
Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
C1
1D
6
2B
C1
1D
C1
1D
TO 11 OTHER CHANNELS
PS8127 03/17/98
1
PI74ALVCH162260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
TruthTables(1)
ProductPinDescription
Pin Name
OE
Description
BtoA(OEB=H)
Output Enable Input (Active LOW)
Inputs
LE1B
Output
A
SEL
Select
LE
Latch Enable
Data Inputs
3-State Outputs
Ground
1B
H
L
2B
X
X
X
H
L
SEL
H
LE2B
X
OEA
L
A,1B,2B
A,1B,2B
GND
H
H
L
H
L
H
X
L
VCC
Power
X
X
X
X
X
H
X
L
A0
H
L
X
X
X
X
H
L
Product Pin Configuration
L
H
L
L
X
X
L
L
L
A0
Z
OE2B
LEA2B
2B4
OEA
LE1B
2B3
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
X
X
H
3
GND
2B2
GND
2B5
4
56-PIN
V56
A56
5
AtoB(OEA=H)
INPUTS
LEA1B LEA2B OE1B OE2B
2B1
2B6
6
OUTPUTS
V
CC
V
CC
7
A1
2B7
8
A
H
1B
H
2B
H
A2
2B8
9
A3
2B9
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
A4
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
L
L
L
A5
H
H
2B0
2B0
H
A6
L
L
L
A7
A8
H
H
H
L
1B0
1B0
1B0
Z
A9
L
L
L
GND
A10
A11
A12
X
L
2B0
Z
1B8
1B7
X
X
X
X
X
X
X
X
X
V
V
CC
CC
1B1
1B2
X
Active
Z
Z
1B6
1B5
X
Active
GND
1B4
GND
1B3
X
Active Active
LE2B
SEL
LEA1B
OE1B
Note:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
PS8127 03/17/98
2
PI74ALVCH162260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
MaximumRatings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ........................................................... 65°C to +150°C
Ambient Temperature with Power Applied ........................ 40°C to +85°C
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditionsabovethoseindicatedintheoperationalsectionsofthis
specificationisnotimplied. Exposuretoabsolutemaximumrating
conditions for extended periods may affect reliability.
Input Voltage Range, V ...................................................... 0.5V to V +0.5V
IN CC
Output Voltage Range, V
............................................... 0.5V to V +0.5V
CC
OUT
DC Input Voltage .................................................................... 0.5V to +5.0V
DC Output Current ............................................................................ 100 mA
Power Dissipation .................................................................................. 1.0W
Parameters
Description
Test Conditions
Min.
2.3
Typ.
Max.
Units
V
CC
Supply Voltage
3.6
V
= 2.7V to 3.6V
= 2.3V to 2.7V
= 2.7V to 3.6V
= 2.3V to 2.7V
2.0
CC
V
Input HIGH Voltage
Input LOW Voltage
IH
V
CC
1.7
V
CC
0.8
0.7
V
V
IL
V
CC
V
Input Voltage
0
0
V
CC
IN
V
OUT
Output Voltage
V
CC
V
= 2.3V
= 2.7V
= 3.0V
= 2.3V
= 2.7V
= 3.0V
= 2.3V
= 2.7V
-12
-12
-24
12
12
24
-6
CC
High-level output
current (A Port)
I
OH
V
CC
V
CC
V
CC
Low-level output
current (A Port)
I
OL
V
CC
V
CC
mA
V
CC
High-level output
current (B Port)
I
OH
V
CC
-8
V
C
= 3.0V
= 2.3V
= 2.7V
= 3.0V
-12
6
CC
V
CC
Low-level output
current (B Port)
I
OL
V
CC
8
V
CC
12
85
T
A
Operating free-air temperature
-40
°C
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
PS8127 03/17/98
3
PI74ALVCH162260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
(1)
(2)
Parameters
Test Conditions
= -100mA
V
CC
Min.
V -0.2
CC
Typ.
Max.
Units
I
Min. to Max.
2.3 V
OH
I
OH
= -6mA
V
= 1.7V
= 1.7V
= 2.0V
= 2.0V
= 2.0V
2.0
IH
V
IH
2.3 V
1.7
2.2
2.4
2.0
V
OH
(A PORT)
I
OH
= -12mA
V
IH
2.7 V
V
IH
3.0 V
I
OH
= -24mA
= -100mA
= -4mA
V
IH
3.0 V
I
OH
Min. to Max.
2.3 V
V
CC
-0.2
I
OH
V
IH
= 1.7V
= 1.7V
= 2.0V
= 2.0V
= 2.0V
1.9
1.7
2.4
2.0
2.0
V
IH
2.3 V
V
(B PORT)
(A PORT)
(B PORT)
I
OH
= -6mA
OH
V
IH
3.0 V
I
OH
= -8mA
= -12mA
= 100mA
= 6mA
V
IH
2.7 V
I
OH
V
IH
3.0 V
V
I
OL
Min. to Max.
2.3V
0.2
0.4
I
OL
V
= 0.7V
= 0.7V
= 0.8V
= 0.8V
IL
V
V
2.3V
0.7
OL
IL
I
OL
= 12mA
V
2.7V
0.4
IL
I
OL
= 24mA
= -100mA
= 4mA
V
3.0V
0.55
0.2
IL
I
OL
Min. to Max.
2.3V
I
OL
V
= 0.7V
= 0.7V
= 0.8V
= 0.8V
= 0.8V
0.4
IL
V
2.3V
0.55
0.55
0.6
IL
I
OL
= 6mA
V
OL
V
3.0V
IL
I
OL
= 8mA
V
2.7V
IL
I
OL
= 12mA
V
3.0V
0.8
IL
I
I
V = V or GND
3.6V
±5
I
CC
V
= 0.7V
= 1.7V
= 0.8V
45
-45
75
IN
2.3V
3.0V
V
IN
V
IN
I (Hold)
I
V
IN
= 2.0V
-75
mA
V
= 0 to 3.6V
3.6V
3.6V
3.6V
±500
±10
40
IN
(3)
I
OZ
V = V or GND
O CC
I
CC
V = V or GND
I CC
DI
CC
One input at V = 0.6V. Other inputs at V or GND 3.3V to 3.6V
750
CC
CC
C
C
Control Inputs V = V or GND
3.3V
3.3V
3.5
4.5
I
IN
CC
pF
A or B ports V = V or GND
IO
O
CC
Notes:
1. For Max. or Min. conditions use appropriate value specified under Electrical Characteristics for the applicable device type.
2. TypicalvaluesareatVcc=3.3V,+25°Cambientandmaximumloading.
3. This is the bus-hold maximum dynamic current required to swtich the input from one state to another.
PS8127 03/17/98
4
PI74ALVCH162260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
TimingRequirementsoverOperatingRange
V
CC
= 2.5V ± 0.2V
V
= 2.7V
V
= 3.3V ± 0.3V
CC
CC
Parameters
Description
Units
Min.
Max.
Min.
Max.
150
Min.
Max.
f
Clock Frequency
150
150
MHz
CLOCK
Pulse duration, LE1B, LE2B,
LEA1B, or LEA2B High
t
3.3
1.4
1.6
3.3
1.1
1.9
3.3
1.1
W
Setup time, data before LE1B,
LE2B, LEA1B, or LEA2B
t
SU
ns
Hold time, data after LE1B,
LE2B, LEA1B or LEA2B
t
1.5
0
H
(1)
Dt/D
Note:
Input Transition Rise or Fall
10
ns/V
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
Switching Characteristics over Operating Range(1)
V
= 2.5V ± 0.2V
V
= 2.7V
V
= 3.3V ± 0.3V
CC
CC
CC
From
To
Parameters
Units
MHz
(2)
(2)
(2)
(2)
(INPUT) (OUTPUT)
Min.
Max.
Min.
150
Max. Min.
Max.
f
150
1.2
1.2
1.0
1.0
1.2
1.0
1.0
1.7
1.7
150
MAX
A
B
B
A
A
B
A
A
B
A
B
6.5
6.0
6.2
6.7
7.5
7.2
7.7
5.9
6.4
5.8
5.1
5.2
5.9
6.6
6.4
7.1
5.0
5.5
1.2
1.2
1.0
1.0
1.1
1.0
1.0
1.3
1.3
4.9
4.3
4.4
5.0
5.6
5.4
6.0
4.6
5.1
t
PD
LE
LE
SEL
OE
OE
OE
OE
ns
t
EN
t
DIS
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
OperatingCharacteristics,T =25ºC
A
V
CC
= 2.5V ± 0.2V
V
= 3.3V ± 0.3V
CC
Parameter
Test Conditions
Units
Typical
Outputs Enabled
62
29
46
24
C
Power Dissipation
Capacitance
C = 50pF,
L
f = 10 MHz
PD
pF
Outputs Disabled
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8127 03/17/98
5
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