PI74ALVCH16524VX [PERICOM]

Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.300 INCH, PLASTIC, SSOP-56;


型号：	PI74ALVCH16524VX
厂家：	PERICOM SEMICONDUCTOR CORPORATION
描述：	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.300 INCH, PLASTIC, SSOP-56 光电二极管逻辑集成电路
文件：	总7页 (文件大小：508K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PI74ALVCH16524

18-Bit Registered Bus Transceiver

With 3-State Outputs

Product Description

Product Features

Pericom Semiconductors PI74ALVCH series of logic circuits are

produced using the Companys advanced 0.5 micron CMOS

technology, achieving industry leading speed.

• PI74ALVCH16524 is designed for low voltage operation

• V = 2.3V to 3.6V

• Typical V

(Output Ground Bounce)

OLP

The PI74ALVCH16524 data flow in each direction is controlled

by output-enable (OEAB and OEBA) and clock-enable

(CLKENBA) inputs. For the A-to-B data flow, the data flows

through a single buffer. The B-to-A data can flow through a four-

stage pipeline register path, or through a single register path,

depending on the state of the select (SEL) input.

< 0.8V at V = 3.3V, T = 25°C

• Typical V

(Output V Undershoot)

OHV

< 2.0V at V = 3.3V, T = 25°C

• Bus Hold retains last active bus state during 3-State

eliminating the need for external pullup resistors

• Industrial operation at 40°C to +85°C

• Packages available:

Data is stored in the internal registers on the low-to-high

transition of the clock (CLK) input, provided that the appropriate

CLKENBA input is low. The B-to-A data transfer is synchronized

with CLK.

56-pin 240 mil wide plastic TSSOP (A)

56-pin 300 mil wide plastic SSOP (V)

To ensure the high-impedance state during power up or power

down, OE should be tied to Vcc through a pull-up resistor; the

minimum value of the resistor is determined by the current-sinking

capability of the driver.

The PI74ALVCH16524 has Bus Hold which retains the data

inputs last state whenever the data input goes to high-impedance

preventing floating inputs and eliminating the need for pullup/

down resistors.

Logic Block Diagram

PS8447A

11/06/00

PI74ALVCH16524

18-Bit Registered Bus Transceiver

with3-StateOutputs

ProductPinDescription

Truth Table⁽¹⁾B to A Storage (OEBA = L)

Inputs

Pin Name

CLKEN

SEL

Description

Outputs

Clock Enable Input (Active LOW)

Select (Active LOW)

Clock Input (Active HIGH)

Data I/O

CLKENBA

CLK

SEL

CLK

Data I/O

GND

VCC

Ground

Power

L§

H§

ProductPinConfiguration

Note:

1. H = High Signal Level

L = Low Signal Level

Z = High Impedance

GND

OEAB

GND

SEL

↑ = LOW-to-HIGH Transition

Output level before the indicated steady-state input

conditions were established.

§ Four positive CLK edges are needed to propagate

data from B to A when SEL is low.

GND

56-Pin

A,V

GND

B10

B11

B12

GND

B13

B14

B15

VCC

B16

B17

GND

B18

CLK

GND

A10

A11

A12

GND

A13

A14

A15

A16

A17

GND

A18

OEBA

CLKENBA

PS8447A

11/06/00

PI74ALVCH16524

18-Bit Registered Bus Transceiver

with3-StateOutputs

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

StorageTemperature .................................................. 65°Cto+150°C

SupplyVoltageRange,V

.................................................... 0.5Vto4.6V

Note:

Stresses greater than those listed under MAXIMUM

RATINGS may cause permanent damage to the device.

Thisisastressratingonlyandfunctionaloperationofthe

device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

InputVoltageRange,V :Except

(1)

I/O ports .................................................................................. 0.5Vto4.6V

(1,2)

I/O ports

................................................................... 0.5VtoV +0.5V

(1,2)

Output Voltage Range, V

.................................. 0.5VtoV +0.5V

Input Clamp current, I (V <0) ................................................ 50mA

OutputClampcurrent, I (V <0)........................................... 50mA

Continous Output Current, I ................................................... ±50mA

Continous Current through each V or GND ........................ ±100mA

MaximumPowerDissipation:

A package ........................................................................................ 1W

V package ..................................................................................... 1.4W

Notes:

1. The input and output negative-voltage ratings maybe exceeded if the input and

outputclamp-current ratings are observed.

2. Thisvalueislimitedto4.6Vmaximum.

Recommended Operating Conditions⁽¹⁾

Parameters

Description

Supply Voltage

Test Conditions

Min.

2.3

Typ.

Max. Units

3.6

= 2.3V to 2.7V

= 2.7V to 3.6V

= 2.3V to 2.7V

= 2.7V to 3.6V

1.7

Input HIGH Voltage

Input LOW Voltage

2.0

0.7

0.8

Input Voltage

OUT

Output Voltage

= 2.3V

= 2.7V

= 3.0V

= 2.3V

= 2.7V

= 3.0V

High-level Output Current

Low-level Output Current

Operating Free-Air Temperature

Input Transition Rise or Fall

°C

(2)

∆t/∆v

ns/V

Note:

1. Unused control inputs must be held HIGH or LOW to prevent them from floating.

2. See test circuit and waveforms.

PS8447A

11/06/00

PI74ALVCH16524

18-Bit Registered Bus Transceiver

with3-StateOutputs

DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ± 10%)

(1)

(2)

Parameters

Test Conditions

Min.

-0.2

Typ.

Max. Units

= -100 µA

Min. to Max.

2.3V

= -6 MA

= 1.7V

= 2.0V

2.0

2.3V

1.7

2.2

2.4

2.0

= -12 mA

2.7V

3.0V

= -24 mA

= 100 µA

= 6 mA

3.0V

Min. to Max.

2.3V

0.2

= 0.7V

= 0.8V

0.4

2.3V

0.7

= 12 mA

= 24 mA

2.7V

0.4

3.0V

0.55

±5

V = V or GND

3.6V

V = 0.7V

-45

2.3V

3.0V

V = 1.7V

(3)

I (Hold)

V = 0.8V

V = 2.0V

-75

µA

V = 0 to 3.6V

3.6V

±500

±10

(4)

V = V or GND

O CC

V = V or GND

I = 0

3.6V

∆I

One input at V - 0.6V, Other inputs at V or GND

3V to 3.6V

3.3V

750

C Control Inputs V = V or GND

A or B ports V = V or GND

3.3V

Notes:

1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device typ e.

2. Typical values are at V = 3.3V, +25°C ambient and maximum loading.

3. Bus Hold maximum dynamic current required to switch the input from one state to another.

4. For I/O ports, the I includes the input leakage current.

PS8447A

11/06/00

PI74ALVCH16524

18-Bit Registered Bus Transceiver

with3-StateOutputs

Timing Requirements over Operating Range

= 2.5V ± 0.2V

= 2.7V

= 3.3V ± 0.3V

Parameters

Description

Clock frequency

Units

Min.

Max.

Min. Max.

Min.

Max.

120

125

150

MHz

CLOCK

Pulse

CLK high or low

3.2

3.0

Duration

B Data before CLK↑

SEL before CLK↑

1.5

2.7

1.0

0.5

0.1

1.2

2.4

2.6

0.6

0.2

0.1

1.1

2.1

2.0

1.2

0.8

0.3

Setup

time

CLKENBA before CLK↑

B Data after CLK↑

SEL after CLK↑

t Hold

time

CLKENBA after CLK↑

Switching Characteristics Over Operating Range⁽¹⁾

= 2.5V ± 0.2V

= 2.7V

V = 3.3V ± 0.V

From

(Input)

(Output)

Parameters

Units

(2)

Min.

Max. Min.

125

Max. Min.

Max.

120

150

MHz

MAX

3.9

6.1

3.8

6.2

3.2

5.2

CLK

OEAB or

OEBA

1.0

A or B

6.1

6.3

6.1

5.4

5.1

4.9

OEAB or

OEBA

DIS

Notes:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

Operating Characteristics, T = 25ºC

= 2.5V ± 0.2V

= 3.3V ± 0.3V

Parameter

Test Conditions

Units

Typical

Outputs Enabled

Power Dissipation

Capacitance

C = 50pF

f = 10 MHz

160

Outputs Disabled

PS8447A

11/06/00

PI74ALVCH16524

18-Bit Registered Bus Transceiver

with3-StateOutputs

ParameterMeasurement Information

= 2.5V ±0.2V

LoadCircuit

Test

Ω

t_pd

Open

Ω

t_{PLZ/ PZL}

2 x V_CC

GND

t_{PHZ/ PZH}

VoltageWaveformsSetup andHoldTimes

VoltageWaveformsPulseDuration

VoltageWaveformsEnableand DisableTimes

VoltageWaveformsPropagationDelayTimes

Figure1. LoadCircuitandVoltageWaveforms

Notes:

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z = 50Ω, t ≤ 2ns, t ≤ 2ns.

D. The outputs are measured one at a time with one transition per measurement.

E. t

F. t

and t

are the same as t .

PLZ

PHZ

dis

are the same as t

ten

PZL

PZH

G. t

and t are the same as t .

PHL pd

PLH

PS8447A

11/06/00

PI74ALVCH16524

18-Bit Registered Bus Transceiver

with3-StateOutputs

ParameterMeasurement Information

= 2.7V and 3.3V ±0.3V

LoadCircuit

Test

Ω

Open

Ω

PLZ/ PZL

GND

PHZ/ PZH

VoltageWaveformsSetup andHoldTimes

VoltageWaveformsPulseDuration

VoltageWaveformsEnableand DisableTimes

VoltageWaveformsPropagationDelayTimes

Figure2. LoadCircuitandVoltageWaveforms

Notes:

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50Ω, t ≤ 2 ns, t ≤ 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. t

F. t

and t

are the same as t .

PLZ

PHZ

dis

are the same as t

ten

PZL

PZH

G. t

and t are the same as t .

PHL pd

PLH

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com

PS8447A

11/06/00

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