PI74ALVTC16823KX [PERICOM]
Bus Driver, ALVT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.173 INCH, PLASTIC, TVSOP-56;
| 型号： | PI74ALVTC16823KX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Bus Driver, ALVT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.173 INCH, PLASTIC, TVSOP-56 驱动 光电二极管 逻辑集成电路 电视 |
| 文件： | 总8页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI74ALVTC16823
2.5V 18-Bit Bus Interface
Flip-Flop with 3-State Outputs
ProductDescription
ProductFeatures
Pericom Semiconductors PI74ALVTC series of logic circuits are
produced using the Companys advanced 0.35 micron CMOS
technology, achieving industry leading speed.
PI74ALVTC16823isdesignedforlowvoltageoperation,
V
DD
=1.65Vto3.6V
Supports Live Insertion
ThePI74ALVTC16823 18-bitbus-interfaceflip-flopisdesignedfor
3.6V I/O Tolerant Inputs and Outputs
Bus Hold
1.65V to 3.6V V operation. It features 3-state outputs designed
CC
specificallyfordrivinghighlycapacitiveorrelativelylow-impedance
loads. This device is particularly suitable for implementing wider
bufferregisters,I/Oports,bidirectionalbusdriverswithparity,and
workingregisters.
HighDrive,32/64mA@3.3V
Uses patented noise reduction circuitry
Power-off high impedance inputs and outputs
Industrial operation at 40°C to +85°C
Packagesavailable:
Thedevicecanbeusedastwo9-bitflip-flopsorone18-bitflip-flop.
WiththeClockEnable(CLKEN)inputLOW, theD-typeflip-flops
enter data on the low-to-high transitions of the clock. Taking
CLKEN HIGH disables the clock buffer, thus latching the outputs.
TakingtheClear(CLR)inputLOWcausestheQoutputstogoLOW
independently of the clock.
56-pin240-milwideplasticTSSOP(A56)
56-pin173-milwideplasticTVSOP(K56)
A buffered Output Enable (OE) input can be used to place the nine
outputs in either a normal logic state (high or low logic levels) or
high-impedance state. In the high-impedance state, the outputs
neither load n or drive the bus lines significantly. The high-
impedance state and increased drive provide the capability to drive
bus lines without need for interface or pullup components.
Logic Block Diagram
2
1OE
1
1CLR
Toensurethehigh-impedancestateduringpoweruporpowerdown,
OE should be tied to V through a pullup resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
55
DD
CE
R
1
CLKEN
56
54
3
C1
1CLK
1Q1
1D1
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.65/3.6V systems, and Bus Hold, which retains the data
inputs last state preventing floating inputs and eliminating the
need for pullup/down resistors.
1D
TO 8 OTHER CHANNELS
27
2OE
28
30
2
CLR
2
CLKEN
CE
R
C1
15
29
42
2CLK
2Q1
2D1
1D
TO 8 OTHER CHANNELS
PS8620
06/05/02
1
PI74ALVTC16823
2.5V 20-Bit Bus Interface
Flip-Flopw/3-StateOutputs
TruthTable(1)
ProductPinDescription
Inputs
Output
PinName
OE
Description
OE
L
CLR
L
CLKEN
CLK
X
D
X
H
L
Q
L
Output Enable Input (Active LOW)
Clear Input (Active LOW)
Clock Enable Input (Active LOW)
Clock Input (Active HIGH)
Data Inputs
X
L
CLR
L
H
↑
H
L
CLKEN
CLK
Dx
L
H
L
↑
L
H
L
L
X
X
X
Q
0
L
H
H
X
X
Q
Qx
3-State Outputs
0
H
X
X
Z
GND
VDD
Ground
Power
Note:
1. H = HighSignalLevel
L = LowSignalLevel
X = Irrelevant
ProductPinConfiguration
Z = HighImpedance
↑ = LOW-to-HIGHTransition
1CLR
1OE
1Q1
GND
1Q2
1Q3
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLK
1CLKEN
1D1
2
3
4
GND
1D2
5
6
1D3
V
DD
7
V
DD
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
8
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Pin
A,K
V
DD
V
DD
2Q7
2Q8
2D7
2D8
GND
2Q9
GND
2D9
2OE
2CLR
2CLKEN
2CLK
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06/05/02
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PI74ALVTC16823
2.5V 20-Bit Bus Interface
Flip-Flopw/3-StateOutputs
MaximumRatings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, V .................................................................. 0.5Vto4.6V
DD
Note:
Input Voltage Range, V .......................................................................... 0.5Vto4.6V
I
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periodsmayaffectreliability.
Output Voltage Range, V (3-Stated)...................................... 0.5Vto4.6V
O
(1)
Output Voltage Range, V
(Active) .......................... 0.5VtoV +0.5V
DD
O
DC Input Diode Current (I ) V < 0V ................................................ 50mA
IK
I
DC Output Diode Current (I
)
OK
V < 0V........................................................................................... 50mA
O
V > V ...............................................................................................................±50mA
DD
O
DC Output Source/Sink Current (I /I ) ................................. 64/128mA
OH OL
DCV orGNDCurrentperSupplyPin(I orGND).....................±100mA
DD
CC
Storage Temperature Range, T .......................................... 65°Cto150°C
stg
(2)
RecommendedOperatingConditions
Min.
Max.
3.6
Units
Operating
1.65
1.2
V
DD
Supply voltage
Data Retention Only
3.6
V
High-level input voltage
Low-level input voltage
Input voltage
V
= 2.7V to 3.6V
= 2.7V to 3.6V
DD
2.0
IH
DD
V
V
0.8
3.6
V
IL
V
0.3
0
I
Active State
Off State
V
DD
V
Output voltage
O
0
3.6
V
= 3.0V to 3.6V
= 3.0V to 3.6V
= 2.3V to 2.7V
= 1.65V to 1.95V
32/64
±24
±18
DD
V
DD
Output current in I /I
mA
OH OL
V
DD
V
DD
±6
(3)
∆t/∆v
Input transistion rise or fall rate
Operating free-air temperature
0
10
85
ns/V
C
T
A
−40
Notes:
1. Absolute maximum of I must be observed.
O
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, V =3.0V.
DD
PS8620
06/05/02
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PI74ALVTC16823
2.5V 20-Bit Bus Interface
Flip-Flopw/3-StateOutputs
ElectricalCharacteristicsoverRecommendedOperatingFree-AirTemperatureRange
(unless otherwise noted)
DC Characteristics (2.7V<V ≤ 3.6V)
DD
Parameter
Conditions
= −18mA
IK
V
Min.
Typ.
Max.
Units
DD
V
IK
Input Clamp Diode
I
3.0
2.7 - 3.6
2.7
1.2
I
OH
= −100µA
= −12mA
= −18mA
= −24mA
= −32mA
= 100µA
= 12mA
V
0.2
DD
I
OH
2.2
2.4
2.2
2.0
V
OH
HIGH Level Output Voltage
I
OH
I
OH
3.0
I
OH
V
I
OL
2.7 - 3.6
2.7
0.2
0.4
I
OL
I
= 18mA
0.4
OL
V
OL
LOW Level Output Voltage
I
OL
= 24mA
0.45
0.5
3.0
I
OL
= 32mA
I
= 64mA
0.55
±5.0
±10
10
OL
I
I
Input Leakage Current
V = V , or GND
3.6
2.7
0
I
DD
I
3-State Output Leakage
Power-OFF Leakage Current
V = 3.6V
O
OZ
I
V or V ≤ 3.6V
I O
OFF
V = 0.8V
75
I
3.0
3.6
I
Bus Hold Current
A or B Outputs
HOLD
V = 2.0V
I
75
µA
V = 0 to 3.6V
I
±500
50
V = V or GND
I
DD
I
DD
Quiescent Supply Current
V
DD
≤ (V ,V ) ≤ 3.6V
±50
I
O
2.7 - 3.6
V
= V 0.6V,
DD
IH
∆I
DD
Increase in I per input
400
DD
Other inputs at V or Gnd
DD
PS8620
06/05/02
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PI74ALVTC16823
2.5V 20-Bit Bus Interface
Flip-Flopw/3-StateOutputs
ElectricalCharacteristicsoverRecommendedOperatingFree-AirTemperatureRange(unlessotherwisenoted)
(continued from previous page)
DC Characteristics (2.3V ≤V ≤ 2.7V)
DD
Description
Parameters
Conditions
= 18mA
IK
V
Min.
Typ.
Max. Units
DD
V
IK
Input Clamp Diode
I
2.3
1.2
I
= 100µA
= 12mA
= 18mA
= 100µA
= 12mA
2.3 -2.7
V
DD
0.2
OH
V
HIGH Level Output Voltage
LOW Level Output Voltage
I
OH
1.8
1.7
OH
2.3
I
OH
V
I
OL
2.3 - 2.7
0.2
I
OL
0.4
0.5
V
OL
I
OL
= 18mA
2.3
I
= 24mA
0.55
±5.0
OL
I
I
Input Leakage Current
3-State Output Leakage
V
I
= V or GND
2.7
2.3
0
DD
I
V
= 3.6V
±10
10
µA
µA
OZ
O
I
Power-OFF Leakage Current V or V ≤ 3.6V
I O
OFF
V = 0.7V
90
I
Bus Hold Current
A or B Outputs
(1)
HOLD
I
2.5
V = 1.7V
I
90
V = V or GND
40
I
DD
I
DD
Quiescent Supply Current
V
DD
≤ (V ,V ) ≤ 3.6V
±40
I
O
2.3 - 2.7
V
= V 0.6V,
DD
IH
∆Ι
DD
Increase in I per input
400
DD
Inputs at V or Gnd
DD
Note:
1. Not Guaranteed
PS8620
06/05/02
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PI74ALVTC16823
2.5V 20-Bit Bus Interface
Flip-Flopw/3-StateOutputs
ElectricalCharacteristicsoverRecommendedOperatingFree-AirTemperatureRange(unlessotherwisenoted)
(continued from previous page)
DC Characteristics (1.65V ≤ V
≤ 1.95V)
DD
Description
Parameters
Conditions
IIK = 18mA
VDD
Min.
Typ.
Max.
Units
VIK
Input Clamp Diode
1.65
1.2
IOH = 100µA
IOH = 6mA
IOL = 100µA
IOL = 6mA
1.65-1.95 VDD 0.2
VOH
HIGH Level Output Voltage
LOW Level Output Voltage
1.4
V
1.65
0.2
0.3
VOL
II
Input Leakage Current
3-State Output Leakage
VI = VDD or GND
VO = 3.6V
1.95
1.65
0
±5.0
±10
10
IOZ
IOFF
Power-OFF Leakage Current VI = VO ≤ 3.6V
VI = 0.4
50
Bus Hold Current
A or B Outputs
(1)
IHOLD
1.65
µA
VI = 1.3
50
VI = VDD or GND
20
IDD
Quiescent Supply Current
VDD ≤ (VI,VO) ≤ 3.6V
±20
1.65-1.95
VI = VDD 06V,
Other inputs at VDD or Gnd
∆ΙDD
Increase in IDD per input
400
Note:
1. Not Guaranteed
PS8620
06/05/02
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PI74ALVTC16823
2.5V 20-Bit Bus Interface
Flip-Flopw/3-StateOutputs
TimingRequirementsoverrecommendedoperatingfree-airtemperaturerange
(unless otherwise noted, see figures 1 thru 4)
VDD = 1.8V ±0.15V
VDD = 2.5V ±0.2V
VDD = 3.3V ±0.3V
Units
Min.
Max.
Min.
Max.
Min.
Max.
f
clock Clock Frequency
150
180
180
MHz
ns
tw Pulse
duration
CLR Low
2.0
2.0
1.0
2.2
2.0
2.0
0.1
0.1
1.8
2.0
2.0
0.5
1.8
1.0
1.0
0.1
0.1
1.0
2.0
2.0
0.5
1.2
1.0
1.0
0.1
0.1
1.0
CLK high or low
CLR Low
tsu Setup
time
Data Low
Data High
CLKEΝ Low
Data High
th Hold
time
Data High
CLKEN Low
SwitchingCharacteristicsoverrecommendedoperatingfree-airtemperaturerange
(unless otherwise noted, see figures 1 thru 4)
Parameter
From
To
VDD = 1.8V ±0.15V
VDD = 2.5V ±0.2V
VCC = 3.3V ±0.3V
Units
(Input)
(Output)
Min.
Max.
Min.
Max.
Min.
Max.
fmax
tpd
150
180
180
MHz
ns
CLK
CLR
Q
4.9
5.0
5.5
5.6
4.2
4.5
5.3
5.6
3.1
3.0
4.0
4.0
ten
OE
OE
tdis
PS8620
06/05/02
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PI74ALVTC16823
2.5V 20-Bit Bus Interface
Flip-Flopw/3-StateOutputs
Switch Position
TestCircuitsandSwitchingWaveforms
ParameterMeasurementInformation(V =1.65V-3.6V)
DD
Test
tPD
S1
Open
2 x VDD
GND
3.3V/2.5V V
DD
2 x VDD
tPLZ/tPZL
tPHZ/tPZH
R1
500Ω
From Output
Under Test
Open
GND
RL
30pF
500Ω
Pulse Width
CL
(See Note A)
V
V
DD
Low-High-Low
Pulse
DD/2
0V
t
W
1.8V V
DD
VDD
2 x VDD
High-Low-High
Pulse
V
DD/2
R1
0V
1kΩ
From Output
Under Test
Open
GND
RL
1kΩ
30pF
CL
Propagation Delay
(See Note A)
VDD
VDD/2
Input
0V
tPHL
tPLH
tPLH
VDD
VDD/2
VOL
Setup, Hold, and Release Timing
Output
VDD
Data
Input
tPHL
VDD/2
VDD
VDD/2
0V
0V
tSU
tH
Opposite Phase
Input Transition
VDD
Timing
Input
VDD/2
0V
Enable Disable Timing
Notes:
A. CL includes probe and jig capacitance.
V
V
DD
Output
Control
DD/2
B. Waveform 1 is for an output with internal conditions such that
the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is HIGH except when disabled by the output control.
C. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, ZO = 50Ω,
tr ≤ 2ns, tf ≤ 2ns, measured from 10% to 90%, unless
otherwisespecified.
D. The outputs are measured one at a time with one transition per
measurement.
0V
(Active LOW)
t
PLZ
t
PZL
PZH
V
DD
V
DD
Output
Waveform 1
S1 at 2xVDD
(see Note B)
V
DD/2
+0.15V
–0.15V
V
V
OL
t
t
PHZ
OH
Output
Waveform 2
S1 at GND
(see Note B)
V
DD/2
0V
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8620
06/05/02
8
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