PI74ALVTC16841AX [PERICOM]

Bus Driver, ALVT Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.240 INCH, PLASTIC, TSSOP-56;


型号：	PI74ALVTC16841AX
厂家：	PERICOM SEMICONDUCTOR CORPORATION
描述：	Bus Driver, ALVT Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.240 INCH, PLASTIC, TSSOP-56 驱动光电二极管逻辑集成电路
文件：	总8页 (文件大小：172K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PI74ALVTC16841

2.5V 20-Bit Bus Interface

D-Type Latch with 3-State Outputs

ProductDescription

Pericom Semiconductor’s PI74ALVTC series of logic circuits are

produced using the Company’s advanced 0.35 micron CMOS

technology, achieving industry leading speed.

ThePI74ALVTC16841features3-Stateoutputsdesignedspecifically

fordrivinghighlycapacitiveorrelativelylow-impedenceloads.This

device is particularly suitable for implementing buffer registers,

unidirectional bus drivers, and working registers.

Thedevicecanbeusedastwo10-bitlatches,orone20-bitlatch.The

20 latches are transparent D-type latches. The device has non-

invertingdata(D)inputsandprovidestruedataatitsoutputs. While

the latch-enable (1LE or 2LE) input is high, the Q outputs of the

corresponding 10-bit latch follows the D inputs. When LE is taken

low, the Q outputs are latched at the levels set up at the D inputs.

ProductFeatures

• PI74ALVTC16841isdesignedforlowvoltageoperation,

=1.65Vto3.6V

• Supports Live Insertion

• 3.6V I/O Tolerant Inputs and Outputs

• Bus Hold

• HighDrive,–32/64mA@3.3V

• Uses patented noise reduction circuitry

• Power-off high impedance inputs and outputs

• Industrial operation at –40°C to +85°C

• Packagesavailable:

–56-pin240-milwideplasticTSSOP(A56)

–56-pin173-milwideplasticTVSOP(K56)

A buffered output-enable (1OE or 2OE) input can be used to place

theoutputsofthecorresponding10-bitlatchineitheranormallogic

state(highorlowlogiclevels)orahigh-impedencestate.Inthehigh-

impedence state, the outputs neither load nor drive the bus lines

significantly.

Logic Block Diagram

The output enable (OE) input does not affect the internal operation

of the latches. Old data can be retained or new data or new data can

be entered while the outputs are in the high-impedence state.

1OE

1LE

Toensurethehigh-impedancestateduringpoweruporpowerdown,

OE should be tied to V through a pullup resistor; the minimum

value of the resistor is determined by the current-sinking capability

of the driver.

1Q0

The family offers both I/O Tolerant, which allows it to operate in

mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data

input’s last state preventing “floating” inputs and eliminating the

need for pullup/down resistors.

1D0

To Nine Other Channels

2OE

2LE

2Q0

2D0

To Nine Other Channels

PS8643

10/29/02

PI74ALVTC16841

2.5V 20-Bit Bus Interface

D-TypeLatchw/3-StateOutputs

ProductPinDescription

TruthTable

PinName

nOE

Description

Inputs

Outputs

Output Enable Inputs (Active LOW)

nLE

Latch Enable Inputs (Active HIGH)

nDx

nQx

GND

Data Inputs

3-State Outputs

Ground

Q₀

Power

ProductPinConfiguration

Notes:

H = HighVoltageLevel

= LowVoltageLevel

X = Don’t Care

= High-Impedance "OFF" state

1OE

1Q0

1Q1

GND

1Q2

1Q3

1LE

1D0

1D1

GND

1D2

1D3

1Q4

1Q5

1D4

1D5

1D6

GND

1D7

1D8

1D9

2D0

2D1

2D2

GND

2D3

2D4

2D5

56-Pin

A, K

1Q6 10

GND 11

1Q7 12

1Q8 13

1Q9 14

2Q0 15

2Q1 16

2Q2 17

GND 18

2Q3 19

2Q4 20

2Q5 21

2Q6 23

2Q7 24

GND 25

2Q8 26

2Q9 27

2OE 28

2D6

2D7

GND

2D8

2D9

2LE

PS8643

10/29/02

PI74ALVTC16841

2.5V 20-Bit Bus Interface

D-TypeLatchw/3-StateOutputs

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Supply Voltage Range, V ........................................................ –0.5Vto4.6V

Input Voltage Range, V ................................................................. -0.5Vto4.6V

Output Voltage Range, V (3-Stated)............................... -0.5Vto4.6V

(1)

Note:

Output Voltage Range, V

(Active) .................. –0.5VtoV +0.5V

Stresses greater than those listed under MAXIMUM

RATINGSmaycausepermanentdamagetothedevice.This

is a stress rating only and functional operation of the device

at these or any other conditions above those indicated in the

operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

DC Input Diode Current (I ) V < 0V ......................................... -50mA

)

DC Output Diode Current (I

V < 0V.................................................................................... -50mA

V > V .................................................................................................... ±50mA

DC Output Source/Sink Current (I /I ) .......................... -64/128mA

OH OL

DCV orGNDCurrentperSupplyPin(I orGND)............ ±100mA

Storage Temperature Range, T .................................. –65°Cto150°C

stg

(2)

RecommendedOperatingConditions

Min.

Max.

3.6

Units

Operating

1.65

1.2

Supply voltage

Data Retention Only

3.6

High-level input voltage

Low-level input voltage

Input voltage

= 2.7V to 3.6V

2.0

0.8

3.6

–0.3

Active State

Off State

Output voltage

3.6

= 3.0V to 3.6V

= 2.3V to 2.7V

= 1.65V to 1.95V

–32/64

±24

Output current in I /I

OH OL

±18

±6

(3)

∆t/∆v

Input transistion rise or fall rate

Operating free-air temperature

ns/V

−40

Notes:

1. Absolute maximum of I must be observed.

2. Unused control inputs must be held HIGH or LOW to prevent them from floating.

3 As measured between 0.8V and 2.0V, V =3.0V.

PS8643

10/29/02

PI74ALVTC16841

2.5V 20-Bit Bus Interface

D-TypeLatchw/3-StateOutputs

ElectricalCharacteristicsoverRecommendedOperatingFree-AirTemperatureRange

(unless otherwise noted)

DC Characteristics (2.7V<V ≤ 3.6V)

Parameter

Conditions

= −18mA

Min.

Typ.

Max.

Units

Input Clamp Diode

3.0

2.7 - 3.6

2.7

–1.2

= −100µA

= −12mA

= −18mA

= −24mA

= −32mA

= 100µA

= 12mA

– 0.2

2.2

2.4

2.2

2.0

HIGH Level Output Voltage

3.0

2.7 - 3.6

2.7

0.2

0.4

= 18mA

0.4

LOW Level Output Voltage

= 24mA

0.45

0.5

3.0

= 32mA

= 64mA

0.55

±5.0

±10

Input Leakage Current

V = V , or GND

3.6

2.7

3-State Output Leakage

Power-OFF Leakage Current

V = 3.6V

V or V ≤ 3.6V

I O

OFF

V = 0.8V

3.0

3.6

Bus Hold Current

A or B Outputs

HOLD

V = 2.0V

–75

µA

V = 0 to 3.6V

±500

V = V or GND

Quiescent Supply Current

≤ (V ,V ) ≤ 3.6V

±50

2.7 - 3.6

= V –0.6V,

∆I

Increase in I per input

400

Other inputs at V or Gnd

PS8643

10/29/02

PI74ALVTC16841

2.5V 20-Bit Bus Interface

D-TypeLatchw/3-StateOutputs

ElectricalCharacteristicsoverRecommendedOperatingFree-AirTemperatureRange(unlessotherwisenoted)

(continued from previous page)

DC Characteristics (2.3V ≤V ≤ 2.7V)

Description

Parameters

Conditions

= –18mA

Min.

Typ.

Max. Units

Input Clamp Diode

2.3

–1.2

= –100µA

= –12mA

= –18mA

= 100µA

= 12mA

2.3 -2.7

– 0.2

HIGH Level Output Voltage

LOW Level Output Voltage

1.8

1.7

2.3

2.3 - 2.7

0.2

0.4

0.5

= 18mA

2.3

= 24mA

0.55

±5.0

Input Leakage Current

3-State Output Leakage

= V or GND

2.7

2.3

= 3.6V

±10

µA

Power-OFF Leakage Current V or V ≤ 3.6V

I O

OFF

V = 0.7V

Bus Hold Current

A or B Outputs

(1)

HOLD

2.5

V = 1.7V

–90

V = V or GND

Quiescent Supply Current

≤ (V ,V ) ≤ 3.6V

±40

2.3 - 2.7

= V –0.6V,

∆Ι

Increase in I per input

400

Inputs at V or Gnd

Note:

1. Not Guaranteed

PS8643

10/29/02

PI74ALVTC16841

2.5V 20-Bit Bus Interface

D-TypeLatchw/3-StateOutputs

ElectricalCharacteristicsoverRecommendedOperatingFree-AirTemperatureRange^{(unlessotherwisenoted)}

(continued from previous page)

DC Characteristics (1.65V ≤ V

≤ 1.95V)

Description

Parameters

Conditions

V_DD

Min.

Typ.

Max.

Units

V_IK

Input Clamp Diode

I_IK= –18mA

1.65

–1.2

I_OH= –100µA

I_OH= –6mA

I_OL= 100µA

I_OL= 6mA

1.65-1.95 V_DD–0.2

V_OH

V_OL

HIGH Level Output Voltage

LOW Level Output Voltage

1.4

1.65

0.2

0.3

I_I

Input Leakage Current

3-State Output Leakage

V_I= V_DDor GND

V_O= 3.6V

1.95

1.65

±5.0

±10

I_OZ

I_OFF

Power-OFF Leakage Current V_I= V_O≤ 3.6V

V_I= 0.4

Bus Hold Current

A or B Outputs

(1)

I_HOLD

1.65

µA

V_I= 1.3

–50

V_I= V_DDor GND

V_DD≤ (V_I,V_O) ≤ 3.6V

I_DD

Quiescent Supply Current

Increase in I_DDper input

±20

1.65-1.95

V_I= V_DD–06V,

Other inputs at V_DDor Gnd

∆Ι

400

Note:

1. Not Guaranteed

PS8643

10/29/02

PI74ALVTC16841

2.5V 20-Bit Bus Interface

D-TypeLatchw/3-StateOutputs

ACElectricalCharacteristics

T = –40°C to +85°C, C = 50pF, R = 500Ω

= 1.8V

= 2.5V

= 3.3V

Symbol

Parameter

Units

±0.15V

±0.2V

±0.3V

Min.

1.5

Max. Min.

Max. Min. Max.

Prop Delay, D to Q

Prop Delay, LE to Q

Output Enable Time

Output Disable Time

4.0

5.0

1.0

1.5

3.2

4.2

4.7

4.0

0.5

2.7

3.1

3.7

PLH, PHL

2.0

PLH, PHL

, t

2.0

1.0

1.5

PZH PZL

, t

2.0

PHZ PLZ

OSHL

OSLH

(1)

Output to Output Skew

0.5

Note

1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

separate outputs of the same device. The specification applies to any outputs switching in the same

direction, eitherHIGHorLOW(t

)orLOWtoHIGH(t

OSHL

OSLH

ACSetupRequirements

T_A= –40ºC to +85ºC, C_L= 50pF, R_L= 500Ω

Symbol

Parameter

V_DD= 1.8V

±0.15V

V_DD= 2.5V

±0.2V

V_DD= 3.3V

±0.3V

Units

Min.

1.0

Typ.

Min.

0.5

1.5

Typ.

Min.

0.5

0.8

1.5

Typ.

t_SU

t_H

Setup Time, D to LE

Hold Time, D to LE

LE Pulse Width, High

1.0

t_W

1.5

Capacitance

T = +25°C

Symbol

Parameter

Conditions

= 1.8, 2.5V or 3.3V,

Units

Typical

Input Capacitance

Output Capacitance

V = 0V or V

OUT

= 1.8V, 2.5V or 3.3V

Power Dissipation

Capacitance

V = 0V or V , F = 10 MHz

= 1.8V, 2.5V or 3.3V

PS8643

10/29/02

PI74ALVTC16841

2.5V 20-Bit Bus Interface

D-TypeLatchw/3-StateOutputs

Switch Position

TestCircuitsandSwitchingWaveforms

ParameterMeasurementInformation(V =1.65V-3.6V)

Test

t_PD

Open

3.3V/2.5V V

2 x VDD

t_PLZ/t_PZL

t_PHZ/t_PZH

2 x V_DD

GND

500Ω

From Output

Under Test

Open

GND

30pF

500Ω

(See Note A)

Pulse Width

VDD

Low-High-Low

Pulse

DD/2

VDD

High-Low-High

Pulse

1.8V V

DD/2

2 x VDD

1kΩ

From Output

Under Test

Open

GND

1kΩ

30pF

Propagation Delay

(See Note A)

VDD

VDD/2

Input

tPHL

tPLH

VDD

VDD/2

VOL

Setup, Hold, and Release Timing

Output

tPHL

VDD

VDD/2

DD/2

Data

Input

Opposite Phase

Input Transition

DD/2

Timing

Input

Enable Disable Timing

Notes:

A. C_Lincludes probe and jig capacitance.

Output

Control

DD/2

(Active LOW)

B. Waveform 1 is for an output with internal conditions such that

the output is LOW except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that

the output is HIGH except when disabled by the output control.

C. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 10 MHz, Z_O= 50Ω,

PLZ

PZL

PZH

Output

Waveform 1

S1 at 2xVDD

(see Note B)

DD/2

+0.15V

–0.15V

PHZ

Output

Waveform 2

S1 at GND

(see Note B)

t_r≤ 2ns, t_f≤ 2ns, measured from 10% to 90%, unless

otherwisespecified.

DD/2

D. The outputs are measured one at a time with one transition per

measurement.

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com

PS8643

10/29/02

PI74ALVTC16841AX [PERICOM]

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