PI90LVT14LEX [PERICOM]
Low Skew Clock Driver, 90LV Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 0.173 INCH, GREEN, MO-153AC, TSSOP-20;
| 型号： | PI90LVT14LEX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Low Skew Clock Driver, 90LV Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 0.173 INCH, GREEN, MO-153AC, TSSOP-20 时钟 |
| 文件： | 总6页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI90LV14/PI90LVT14
1:5 Clock Distribution
Features
Description
• Meets and Exceeds the Requirements of ANSI
TIA/EIA-644-1995
ThePI90LV14implementslowvoltagedifferentialsignaling(LVDS)
to achieve clocking rates as high as 320MHz with low skew.
• Designed for clocking rates up to 320MHz
• Operates from a single 3.3V Supply
• LowVoltageDifferentialSignaling(LVDS)withOutput
Voltages of ±350mV into a 100Ωload
• Choice between LVDS or TTL clock input
• Synchronous Enable/Disable
The PI90LV14 is a low-skew 1:5 clock distribution chip which
incorporates multiplexed clock inputs to allow for distribution of a
lower-speed, single-ended clock or a high-speed system clock.
When LOWthe SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control.Becausetheinternalflip-flopisclockedonthefallingedge
oftheinputclock, allassociatedspecificationlimitsarereferenced
to the negative edge of the clock input.
• Clock outputs default LOW when inputs open
• Multiplexedclockinput
- Internal 300kΩpullup resistor on input pins
-CLKandCLKhave110Ωinternaltermination(PI90LVT14)
• 50ps Output-to-Output Skew
• 475ps typical propagation delay
• Bus Pins are high impedance when disabled or with
The intended application of these devices and signaling technique
is for high-speed clock distribution between boards.
V
CC
less than 1.5V
• TTL inputs are 5V Tolerant
• Power Dissipation at 400Mbits/s of 150mW
• FunctioncompatibletoMotorola(PECL)
MC100EL14andMicrel/Synergy(PECL)
SY100EL14V
PI90LV14 Block Diagram
• >9kVESDProtection
1
CLK1OUT+
• 20-pinTSSOP(L)andQSOP(Q)packages
V
20
19
CC
2
CLK1OUT–
Pin Descriptions
EN
Pin
CLK, CLK
SCLK
Funtion
3
4
CLK2OUT+
CLK2OUT–
D
Differential Clock Outputs
LVTTL Clock Input
Synchronous Enable
Clock Select Input
V
18
17
CC
Q
GND
EN
5
6
16
15
1
0
CLK3OUT+
CLK3OUT–
SCLK
CLK
SEL
Ω
CLK1-5OUT±
Differential Clock Inputs
14
13
Function Table
7
8
CLK
CLK4OUT+
CLK4OUT–
CLK
L
SCLK
SEL
L
EN*
L
CLKOUT+
GND
X
X
L
L
H
12
11
SEL
H
L
L
9
CLK5OUT+
CLK5OUT–
X
H
L
L
10
X
H
↓
H
L
H
GND
↓
X
H
Z*
* On next negative transition of CLK, or SCLK
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PI90LV14/PI90LVT14
1:5 Clock Distribution
ElectricalCharacteristicsoverRecommendedOperatingConditions(unlessotherwisenoted).
(1)
Symbol
V
Parameter
Test Conditions
Min.
Typ.
Max. Units
Differential output voltage magnitude
247
340
454
OD
R = 100Ω
L
mV
50
Change in differential output voltage
magnitude between logic states
See Figures 1 and 2
∆V
–50
1.125
–50
OD
Steady-state common-mode output
voltage
V
OC(SS)
1.40
1.7
50
V
Change in steady-state common-mode
output voltage between logic states
∆V
See Figure 3
OC(SS)
mV
Peak-to-peak common-mode
output voltage
V
OC(PP)
60
100
Enabled, R = 100Ω V = V or GND
21
2.5
3.0
5.0
35
4.0
20
20
7.4
4.7
1
L
IN
CC
I
Supply Current
mA
µA
CC
Disabled, V = V or GND
0.5
IN
CC
I
High-level input current
Low-level input current
V
V
V
V
= 2V
IH
IH
I
= 0.8V
IL
IL
or V
= 0V
ODOUT+
ODOUT–
I
Short-circuit output current
mA
µA
OS
= 0V
OD
I
OZ
High-impedance output current
Power-off output current
Input capacitance,
V = 0V or V
O CC
I
V
CC
= 1.5V, V = 2.4V
1
O(OFF)
O
C
V = 0.4 sin (4E6πt) +0.5V
I
9
IN
pF
C
Output capacitance
V = 0.4 sin (4E6πt) +0.5V, Disabled
I
10
O
R
TERM
Termination Resistor
PI90LVT14
90
110
132
Ω
PS8538
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PI90LV14/PI90LVT14
1:5 Clock Distribution
SwitchingCharacteristicsoverRecommendedOperatingConditions(unlessotherwisenoted)(8,9).
Characteristic
Symbol
Min.
Typ.
Max.
Units
Condition
Propagation Delay to Output
CLK to CLKOUT ±
SCLK to CLKOUT ±
SEL to CLKOUT ±
tPLH
tPHL
3.0
2.5
2.6
4.0
3.5
3.6
ns
Disable Time
CLK or SCLK to CLKOUT ±
tPHZ
tPLZ
tPZH
tPZL
2.7
2.7
4.7
3.7
3.5
3.5
6.0
6.0
ns
2
1
Part-to-Part Skew
CLK (Diff) to Q
CLK (SE), SCLK to Q
With Device Skew
tskew
tskew
tskew
TBD
TBD
TBD
Setup Time
ENx to CLK
CEN to CLK
ps
V
ts
ts
100
100
–100
–100
2
2
Hold Time
ENx, CEN to SCLK
ENx, CEN to CLKx
th
th
550
500
720
720
Minimum Input Swing (CLK)
Com. Mode Range (CLK)
VPP
0.20
0.800
3
4
VCMR
0.125
1.5
VCC - 0.20
Rise/Fall Times (20 – 80%)
SCLK to CLKOUT±
SCLK to CLKOUT±
tr
tf
150
150
1200
1200
ps
Duty Cycle Distortion Pulse Skew ( tPLH - tPHL
Channel-to-Channel Skew, same edge
Maximum Operating Frequency
Notes:
)
tSK1R
tSK2R
200
70
300
190
5
6
7
250
MHz
1. Within-Device skew is defined for identical transitions on similar paths through a device.
2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.
3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated
with only 50mV input swings.
4. The range in which the high level of the input swing must fall while meeting the V spec.
PP
5. tSKIR is the difference in receiver propagation delay (tPLH-tPHL) of one device, and is the duty cycle distortion of
the output at any given temperature and VCC. The propagation delay specification is a device-to-device worst
case over process, voltage, and temperature.
6. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs
switching in the same direction. This parameter is guaranteed by design and characterization.
7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).
OutputCriteria:60%/40%dutycycle,VOL(max)0-4V,VOH(min)2.7V,Load-7pF(strayplusprobes).
8. CL includes probe and fixture capacitance.
9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr = 1ns, tf = 1ns (35%-65%). To
ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V;
control signals not slower than 3ns/V.
PS8538
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PI90LV14/PI90LVT14
1:5 Clock Distribution
ParameterMeasurementInformation
IOY
DOUT+
II
DIN
VOD
IOZ
VODOUT+
VOC
DOUT–
VI
VODOUT–
GND
(VODOUT++VODOUT–)/2
Figure 1. Voltage and Current Definitions
3.75kΩ
100Ω
3.75kΩ
DOUT+
VOD
Input
DOUT–
±
0V ≤ V
≤ 2.4V
TEST
Figure 2. VOD Test Circuit
3V
0V
49.9Ω ±1% (2 places)
DOUT+
VI
V
OC(PP)
Input
V
V
OC(SS)
OC
DOUT–
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1ns, Pulse Repetition Rate
(PRR) = 50 Mpps, Pulse width = 10 ±0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
The measurement of VOC(PP) is made on test equipment with a –3dB bandwidth of at least 300MHz.
Figure 3. Test Circuit & Definitions for the Driver Common-Mode Output Voltage
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PI90LV14/PI90LVT14
1:5 Clock Distribution
ParameterMeasurementInformation(continued)
32V
Input
1.4V
0.8V
DOUT+
t
t
PLH
PHL
V
V
100Ω ±1%
Input
OD
100%
80%
Output
V
DOUT–
C = 10pF
L
(2 places)
OD(H)
0V
OD(L)
20%
0%
t
t
r
f
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1ns, Pulse Repetition Rate
(PRR) = 15 Mpps, Pulse width = 10 ±0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
Figure 4. Test Circuit, Timing, & Voltage Definitions for the Differential Output Signal
49.9Ω ±1% (2 places)
DOUT+
0.8V or 2V
Input
+
1.2V
DOUT–
–
VODOUT+ VODOUT–
2V
1.4V
0.8V
Input
t
t
PHZ
PZH
≅1.4V
V
ODOUT+
or
ODOUT–
1.3V
1.2V
V
t
t
PLZ
PZL
1.2V
V
ODOUT–
or
1.1V
≅1V
VODOUT+
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1ns, Pulse Repetition Rate
(PRR) = 0.5 Mpps, Pulse width = 500 ±10ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
Figure 5. Enable & Disable Time Circuit & Definitions
PS8538
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PI90LV14/PI90LVT14
1:5 Clock Distribution
20-PinQSOP(Q)Package
20
.008
0.20
MIN.
.008
.013
0.20
0.33
.150
.157
3.81
3.99
Guage Plane
0˚-6˚
.010
.016
.035
0.41
0.89
0.254
1
Detail A
.337 8.56
.344 8.74
.041
1.04
REF
.015 x 45˚
0.38
.058
1.47
REF
.053 1.35
.069 1.75
Detail A
0.178
0.254
.007
.010
SEATING
PLANE
.016 0.41
.050 1.27
.004 0.101
.010 0.254
.025
BSC
0.635
.228
.244
.008
.012
0.203
0.305
5.79
6.19
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
20-PinTSSOP(L)Package
20
.169
.177
4.3
4.5
1
.252
0.09
0.20
.004
.008
.260
6.4
6.6
.047
1.20
Max
0.45 .018
0.75 .030
SEATING
PLANE
.238
.269
6.1
6.7
.002
.006
0.05
0.15
.0256
BSC
.007
.012
0.19
0.30
0.65
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
OrderingInformation
Ordering Code
PI90LV14L
Package Type
Ordering Range
20-Pin 173-mil TSSOP
20-Pin 150-mil QSOP
PI90LVT14L
PI90LV14Q
PI90LVT14Q
–40°C to 85°C
Pericom Semiconductor Corporation
2380BeringDrive • SanJose,CA95131•1-800-435-2336 • Fax(408)435-1100• http://www.pericom.com
PS8538
04/25/01
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