74ABTH16374BDL-T [PHILIPS]

D Flip-Flop, 16-Func, Positive Edge Triggered, PDSO48;
74ABTH16374BDL-T
型号: 74ABTH16374BDL-T
厂家: PHILIPS SEMICONDUCTORS    PHILIPS SEMICONDUCTORS
描述:

D Flip-Flop, 16-Func, Positive Edge Triggered, PDSO48

驱动 信息通信管理 光电二极管 逻辑集成电路
文件: 总10页 (文件大小:87K)
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INTEGRATED CIRCUITS  
74ABT16374B  
74ABTH16374B  
16-bit D-type flip-flop;  
positive-edge trigger (3-State)  
Product specification  
1998 Feb 27  
Supersedes data of 1995 Sep 28  
IC23 Data Handbook  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
16-bit D-type flip-flop; positive-edge trigger  
(3-State)  
74ABT16374B  
74ABTH16374B  
FEATURES  
DESCRIPTION  
The 74ABT16374B high-performance BiCMOS device combines  
low static and dynamic power dissipation with high speed and high  
output drive.  
Two 8-bit positive edge triggered registers  
Live insertion/extraction permitted  
Power-up 3-State  
The 74ABT16374B has two 8-bit, edge triggered registers, with each  
register coupled to eight 3-State output buffers. The two sections of  
each register are controlled independently by the clock (nCP) and  
Output Enable (nOE) control gates.  
Power-up reset  
Multiple V and GND pins minimize switching noise  
CC  
Each register is fully edge triggered. The state of each D input, one  
set-up time before the Low-to-High clock transition, is transferred to  
the corresponding flip-flop’s Q output.  
3-State output buffers  
74ABTH16373B incorporates bus-hold data inputs which  
eliminate the need for external pull-up resistors to hold unused  
inputs  
The 3-State output buffers are designed to drive heavily loaded  
3-State buses, MOS memories, or MOS microprocessors. Each  
active-Low Output Enable (nOE) controls all eight 3-State buffers for  
its register independent of the clock operation.  
Bus-hold data inputs eliminate the need for external pull-up  
resistors to hold unused inputs  
When nOE is Low, the stored data appears at the outputs for that  
register. When nOE is High, the outputs for that register are in the  
High-impedance “OFF” state, which means they will neither drive  
nor load the bus.  
Output capability: +64mA/–32mA  
Latch-up protection exceeds 500mA per JEDEC Std 17  
ESD protection exceeds 2000V per MIL STD 883 Method 3015  
Two options are available, 74ABT16374B which does not have the  
bus-hold feature and 74ABTH16374B which incorporates the  
bus-hold feature.  
and 200V per Machine Model  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
T
amb  
t
t
Propagation delay  
nCP to nQx  
2.6  
2.2  
PLH  
PHL  
C = 50pF; V = 5V  
ns  
L
CC  
C
Input capacitance  
Output capacitance  
V = 0V or V  
CC  
4
7
pF  
pF  
IN  
I
C
V = 0V or V ; 3-State  
O CC  
OUT  
CCZ  
I
Outputs disabled; V = 5.5V  
500  
8
µA  
mA  
CC  
Quiescent supply current  
I
Outputs Low; V = 5.5V  
CCL  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE OUTSIDE NORTH AMERICA  
NORTH AMERICA  
BT16374B DL  
DWG NUMBER  
SOT370-1  
48-Pin Plastic SSOP Type III  
48-Pin Plastic TSSOP Type II  
48-Pin Plastic SSOP Type III  
48-Pin Plastic TSSOP Type II  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
74ABT16374B DL  
74ABT16374B DGG  
74ABTH16374B DL  
74ABTH16374B DGG  
BT16374B DGG  
BH16374B DL  
SOT362-1  
SOT370-1  
BH16374B DGG  
SOT362-1  
PIN DESCRIPTION  
LOGIC SYMBOL  
PIN NUMBER  
SYMBOL  
FUNCTION  
47 46 44 43 41 40 38 37  
47, 46, 44, 43, 41, 40, 38, 37 1D0 – 1D7  
36, 35, 33, 32, 30, 29, 27, 26 2D0 – 2D7  
Data inputs  
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7  
1CP  
2, 3, 5, 6, 8, 9, 11, 12  
1Q0 – 1Q7  
48  
1
Data outputs  
13, 14, 16, 17, 19, 20, 22, 23 2Q0 – 2Q7  
1OE  
Output enable  
inputs (active-Low)  
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7  
1, 24  
1OE, 2OE  
Clock pulse inputs  
(active rising edge)  
2
3
5
6
8
9
11 12  
48, 25  
1CP, 2CP  
GND  
36 35 33 32 30 29 27 26  
4, 10, 15, 21, 28, 34, 39, 45  
7, 18, 31, 42  
Ground (0V)  
Positive supply  
voltage  
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7  
V
CC  
25  
24  
2CP  
2OE  
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7  
13 14 16 17 19 20 22 23  
SH00078  
2
1998 Feb 27  
853-1752 19027  
Philips Semiconductors  
Product specification  
16-bit D-type flip-flop; positive-edge trigger  
(3-State)  
74ABT16374B  
74ABTH16374B  
LOGIC SYMBOL (IEEE/IEC)  
PIN CONFIGURATION  
1
2
48  
47  
1OE  
1Q0  
1Q1  
GND  
1Q2  
1Q3  
1CP  
1D0  
1
1OE  
1CP  
2OE  
2CP  
1EN  
C1  
2EN  
C2  
48  
24  
25  
3
46 1D1  
GND  
1D2  
4
45  
44  
5
47  
46  
44  
43  
2
3
6
43 1D3  
1D  
1
1D0  
1D1  
1D2  
1D3  
1D4  
1D5  
1D6  
1D7  
2D0  
1Q0  
1Q1  
1Q2  
1Q3  
1Q4  
1Q5  
1Q6  
1Q7  
2Q0  
7
42  
V
V
CC  
CC  
5
8
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
1Q4  
1Q5  
1D4  
1D5  
6
9
41  
40  
8
GND  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
9
1Q6  
1Q7  
2Q0  
2Q1  
GND  
1D6  
1D7  
2D0  
2D1  
GND  
38  
37  
11  
12  
13  
36  
2
2D  
35  
33  
14  
16  
2D1  
2D2  
2D3  
2D4  
2D5  
2D6  
2D7  
2Q1  
2Q2  
2Q3  
2Q4  
2Q5  
2Q6  
2Q7  
2Q2  
2Q3  
2D2  
2D3  
32  
30  
29  
17  
19  
20  
V
V
CC  
CC  
2Q4  
2D4  
27  
26  
22  
23  
2Q5 20  
29 2D5  
21  
22  
23  
24  
28  
27  
26  
25  
GND  
2Q6  
GND  
2D6  
SH00077  
2Q7  
2OE  
2D7  
2CP  
SA00326  
LOGIC DIAGRAM  
nD0  
nD1  
nD2  
nD3  
nD4  
nD5  
nD6  
nD7  
D
D
D
D
D
D
D
D
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP  
Q
CP Q  
nCP  
nOE  
nQ0  
nQ1  
nQ2  
nQ3  
nQ4  
nQ5  
nQ6  
nQ7  
SA00327  
3
1998 Feb 27  
Philips Semiconductors  
Product specification  
16-bit D-type flip-flop; positive-edge trigger  
(3-State)  
74ABT16374B  
74ABTH16374B  
FUNCTION TABLE  
INPUTS  
nCP  
OUTPUTS  
INTERNAL  
REGISTER  
OPERATING MODE  
nOE  
nDx  
nQ0 – nQ7  
L
L
l
h
L
H
L
H
Load and read register  
L
X
NC  
NC  
Hold  
H
H
X
nDx  
NC  
nDx  
Z
Z
Disable outputs  
H
h
L
l
=
=
=
=
High voltage level  
High voltage level one set-up time prior to the High-to-Low E transition  
Low voltage level  
Low voltage level one set-up time prior to the High-to-Low E transition  
NC= No change  
X
Z
=
=
=
=
Don’t care  
High impedance “off” state  
Low-to-High clock transition  
Not a Low-to-High clock transition  
1, 2  
ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
PARAMETER  
DC supply voltage  
CONDITIONS  
RATING  
–0.5 to +7.0  
–18  
UNIT  
V
V
CC  
I
IK  
DC input diode current  
V < 0  
I
mA  
V
3
V
I
DC input voltage  
–1.2 to +7.0  
–50  
I
DC output diode current  
V
O
< 0  
mA  
V
OK  
3
V
OUT  
DC output voltage  
output in Off or High state  
output in Low state  
–0.5 to +5.5  
128  
I
DC output current  
mA  
OUT  
output in High state  
–64  
T
stg  
Storage temperature range  
–65 to 150  
°C  
NOTES:  
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the  
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to  
absolute-maximum-rated conditions for extended periods may affect device reliability.  
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction  
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.  
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
RECOMMENDED OPERATING CONDITIONS  
LIMITS  
SYMBOL  
PARAMETER  
UNIT  
MIN  
4.5  
0
MAX  
V
CC  
DC supply voltage  
5.5  
V
V
V
I
Input voltage  
V
CC  
V
High-level input voltage  
Low-level Input voltage  
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Operating free-air temperature range  
2.0  
V
IH  
V
0.8  
–32  
64  
V
IL  
I
mA  
mA  
ns/V  
°C  
OH  
I
OL  
t/v  
0
10  
T
amb  
–40  
+85  
4
1998 Feb 27  
Philips Semiconductors  
Product specification  
16-bit D-type flip-flop; positive-edge trigger  
(3-State)  
74ABT16374B  
74ABTH16374B  
DC ELECTRICAL CHARACTERISTICS  
LIMITS  
= +25°C  
T
= –40°C  
to +85°C  
amb  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
T
amb  
UNIT  
MIN  
TYP  
MAX  
MIN  
MAX  
V
Input clamp voltage  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 4.5V; I = –18mA  
–0.9  
2.9  
–1.2  
–1.2  
V
V
IK  
IK  
= 4.5V; I = –3mA; V = V or V  
2.5  
3.0  
2.0  
2.5  
3.0  
2.0  
OH  
I
IL  
IH  
IH  
V
OH  
High-level output voltage  
= 5.0V; I = –3mA; V = V or V  
3.4  
OH  
I
IL  
= 4.5V; I = –32mA; V = V or V  
IH  
2.4  
OH  
I
IL  
V
OL  
Low-level output voltage  
= 4.5V; I = 64mA; V = V or V  
IH  
0.42  
0.13  
0.55  
0.55  
0.55  
0.55  
V
V
OL  
I
IL  
3
V
RST  
Power-up output voltage  
= 5.5V; I = 1mA; V = GND or V  
O I CC  
Input leakage current  
74ABT16374B  
I
V
V
= 5.5V; V = V or GND  
0.01  
±1  
±1  
±1  
±1  
µA  
I
I
CC  
I
CC  
= 5.5V; V = V or  
CC  
I
CC  
Control pins  
±0.01  
GND  
Input leakage current  
74ABTH16374B  
I
µA  
V
CC  
V
CC  
V
CC  
= 5.5V; V = V  
0.01  
–1  
1
1
I
CC  
5
Data pins  
= 5.5V; V = 0  
–3  
–5  
I
= 4.5V; V = 0.8V  
50  
50  
I
6
Bus Hold current inputs  
74ABTH16374B  
I
µA  
V
V
V
= 4.5V; V = 2.0V  
–75  
–75  
HOLD  
CC  
I
= 5.5V; V = 0 to 5.5V  
±800  
CC  
I
I
Power-off leakage current  
Power-up/down 3-State  
= 0.0V; V or V 4.5V  
±5.0  
±5.0  
±100  
±50  
±100  
±50  
µA  
µA  
OFF  
CC  
O
I
V
CC  
= 2.1V; V = 0.5V;  
O
I
PU/PD  
4
output current  
V = GND or V ; V  
I
= GND  
CC  
OE  
I
3-State output High current  
3-State output Low current  
Output High leakage current  
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V  
0.5  
–0.5  
5.0  
–70  
0.5  
8
10  
–10  
50  
10  
–10  
50  
µA  
µA  
OZH  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
O
I
IL  
IH  
IH  
I
= 5.5V; V = 0.5V; V = V or V  
O I IL  
OZL  
I
= 5.5V; V = 5.5V; V = GND or V  
CC  
µA  
CEX  
O
I
1
I
O
Output current  
= 5.5V; V = 2.5V  
–50  
–180  
2
–50  
–180  
2
mA  
mA  
mA  
O
I
I
= 5.5V; Outputs High, V = GND or V  
I
CCH  
CC  
I
Quiescent supply current  
= 5.5V; Outputs Low, V = GND or V  
19  
19  
CCL  
I
CC  
= 5.5V; Outputs 3-State;  
0.5  
5
2
2
mA  
CCZ  
V = GND or V  
I
CC  
Additional supply current  
V
CC  
V
CC  
= 5.5V; one input at 3.4V, other inputs at  
or GND  
2
per input pin  
I  
I  
100  
100  
µA  
CC  
74ABT16374B  
Additional supply current  
V
CC  
V
CC  
= 5.5V; one input at 3.4V, other inputs at  
or GND  
2
per input pin  
0.5  
1.5  
1.5  
mA  
CC  
74ABTH16374B  
NOTES:  
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
2. This is the increase in supply current for each input at 3.4V.  
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.  
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10% a  
CC  
CC  
CC  
transition time of up to 100µsec is permitted.  
5. Unused pins at V or GND.  
CC  
6. This is the bus hold overdrive current required to force the input to the opposite logic state.  
5
1998 Feb 27  
Philips Semiconductors  
Product specification  
16-bit D-type flip-flop; positive-edge trigger  
(3-State)  
74ABT16374B  
74ABTH16374B  
AC CHARACTERISTICS  
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω  
R
F
L
L
LIMITS  
T
V
= +25°C  
= +5.0V  
T
V
= –40 to +85°C  
UNIT  
amb  
CC  
amb  
CC  
SYMBOL  
PARAMETER  
WAVEFORM  
= +5.0V ±0.5V  
MIN  
TYP  
MAX  
MIN  
MAX  
f
Maximum clock frequency  
1
1
180  
260  
MHz  
MAX  
t
t
Propagation delay  
nCP to nQx  
1.7  
1.4  
2.6  
2.2  
4.0  
3.4  
1.7  
1.4  
4.7  
ns  
PLH  
PHL  
3.9  
t
t
Output enable time  
to High and Low level  
3
4
1.3  
1.3  
2.4  
2.3  
3.7  
3.4  
1.3  
1.3  
4.7  
ns  
PZH  
PZL  
4.6  
t
t
Output disable time  
from High and Low level  
3
4
1.9  
1.7  
3.1  
2.6  
4.6  
4.0  
1.9  
1.7  
5.5  
ns  
PHZ  
PLZ  
4.4  
AC SETUP REQUIREMENTS  
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω  
R
F
L
L
LIMITS  
T
V
= +25°C  
= +5.0V  
T
V
= –40 to +85°C  
UNIT  
amb  
CC  
amb  
CC  
SYMBOL  
PARAMETER  
WAVEFORM  
= +5.0V ±0.5V  
MIN  
TYP  
MIN  
t (H)  
t (L)  
s
Setup time, High or Low  
nDx to nCP  
1.0  
1.0  
0.3  
0.1  
1.0  
1.0  
s
2
2
1
ns  
ns  
ns  
t (H)  
Hold time, High or Low  
nDx to nCP  
1.0  
1.0  
–0.1  
–0.3  
1.0  
1.0  
h
t (L)  
h
t (H)  
nCP pulse width  
High or Low  
2.8  
2.8  
1.2  
1.5  
2.8  
2.8  
w
t (L)  
w
AC WAVEFORMS  
V
M
= 1.5V, V = GND to 3.0V  
IN  
1/f  
MAX  
nDx  
V
V
V
V
M
M
M
M
nCP  
nQx  
VM  
t
VM  
VM  
t (H)  
t
(H)  
t (L)  
t (L)  
h
s
h
s
t
(H)  
t (L)  
w
w
nCP  
t
PHL  
PLH  
V
V
M
M
VM  
VM  
NOTE: The shaded areas indicate when the input is permitted to  
change for predictable output performance.  
SA00329  
SA00328  
Waveform 2. Data Setup and Hold Times  
Waveform 1. Propagation Delay, Clock Input to Output, Clock  
Pulse Width, and Maximum Clock Frequency  
6
1998 Feb 27  
Philips Semiconductors  
Product specification  
16-bit D-type flip-flop; positive-edge trigger  
(3-State)  
74ABT16374B  
74ABTH16374B  
OE  
V
V
M
M
V
V
M
OE  
M
t
t
t
PLZ  
PZL  
t
PZH  
PHZ  
V
V
OH  
OH  
–0.3V  
0V  
nQx  
V
M
V
nQx  
M
V
V
+ 0.3V  
OL  
OL  
SH00079  
SH00080  
Waveform 3. 3-State Output Enable Time to High Level and  
Output Disable Time from High Level  
Waveform 4. 3-State Output Enable Time to Low Level and  
Output Disable Time from Low Level  
TEST CIRCUIT AND WAVEFORM  
t
W
V
AMP (V)  
CC  
90%  
90%  
7.0V  
NEGATIVE  
PULSE  
V
V
M
M
10%  
10%  
90%  
R
L
0V  
(t  
V
V
OUT  
IN  
PULSE  
GENERATOR  
D.U.T.  
t
t
(t  
(t  
)
t
TLH  
)
THL  
F
R
)
t
(t )  
R
R
L
C
TLH  
R
THL F  
T
L
AMP (V)  
90%  
M
POSITIVE  
PULSE  
V
V
M
Test Circuit for 3-State Outputs  
10%  
10%  
t
W
0V  
SWITCH POSITION  
V
= 1.5V  
M
TEST  
SWITCH  
Input Pulse Definition  
t
closed  
PLZ  
PZL  
t
closed  
open  
All other  
INPUT PULSE REQUIREMENTS  
DEFINITIONS  
R = Load resistor; see AC CHARACTERISTICS for value.  
L
FAMILY  
Amplitude  
3.0V  
Rep. Rate  
1MHz  
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;  
L
see AC CHARACTERISTICS for value.  
74ABT/H16  
500ns 2.5ns 2.5ns  
R = Termination resistance should be equal to Z  
T
of  
OUT  
pulse generators.  
SA00018  
7
1998 Feb 27  
Philips Semiconductors  
Product specification  
Dual octal D-type flip-flop;  
positive-edge trigger (3-State)  
74ABT16374B  
74ABTH16374B  
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm  
SOT370-1  
8
1998 Feb 27  
Philips Semiconductors  
Product specification  
Dual octal D-type flip-flop;  
positive-edge trigger (3-State)  
74ABT16374B  
74ABTH16374B  
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm  
SOT362-1  
9
1998 Feb 27  
Philips Semiconductors  
Product specification  
16-bit D-type flip-flop; positive-edge trigger  
(3-State)  
74ABT16374B  
74ABTH16374B  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make chages at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
RighttomakechangesPhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1998  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
print code  
Date of release: 05-96  
9397-750-03492  
Document order number:  
Philips  
Semiconductors  

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