74ALVCH16843 [NXP]
18-bit bus-interface D-type latch 3-State; 18位总线接口D型锁存三态
| 型号： | 74ALVCH16843 |
| 厂家： | 
NXP |
| 描述： | 18-bit bus-interface D-type latch 3-State |
| 文件： | 总12页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ALVCH16843
18-bit bus-interface D-type latch (3-State)
Product specification
IC24 Data Handbook
1998 Aug 04
Philips
Semiconductors
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
FEATURES
PIN CONFIGURATION
• Wide supply voltage range of 1.2V to 3.6V
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLR
1OE
1LE
1PRE
1D
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
1Q
0
3
0
GND
4
GND
1Q
1
5
1D
1
1Q
2
6
1D
2
TM
• MULTIBYTE flow-through standard pin-out architecture
V
7
V
CC
CC
• Low inductance multiple V and GND pins for minimum noise
CC
1Q
3
1Q
4
1Q
5
8
1D
1D
1D
3
4
5
and ground bounce
9
• All data inputs have bus hold
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
GND
• Output drive capability 50Ω transmission lines @ 85°C
1Q
6
1Q
7
1Q
8
2Q
0
2Q
1
2Q
2
1D
1D
1D
2D
2D
2D
6
7
8
0
1
2
DESCRIPTION
The 74ALVCH16843 has two 9–bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE), clear (nCLR),
preset (nPRE) and output enable (nOE) control gates.
GND
GND
2Q
2Q
2Q
2D
2D
2D
3
4
3
4
When nOE is LOW, the data in the registers appear at the outputs.
When nOE is HIGH, the outputs are in the high impedance OFF
state. Operation of the nOE input does not affect the state of the
flip-flops.
5
5
V
V
CC
CC
The 74ALVCH16843 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
2Q
2Q
2D
2D
6
6
7
7
GND
2Q
GND
2D
8
8
2OE
2PRE
2LE
2CLR
SH00143
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t = t ≤ 2.5ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
nDn to nQn
V
V
= 2.5V, C = 30pF
2.2
2.1
CC
CC
L
ns
= 3.3V, C = 50pF
L
t
/t
PHL PLH
Propagation delay
nLE to nQn
V
CC
V
CC
= 2.5V, C = 30pF
2.3
2.0
L
ns
= 3.3V, C = 50pF
L
C
C
Input capacitance
5.0
pF
I
transparent mode
Output enabled
Output disabled
17
3
1
Power dissipation capacitance per buffer
V = GND to V
I CC
pF
PD
Clocked mode
Output enabled
Output disabled
19
9
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW):
PD
D
2
2
P
= C × V
× f + S (C × V
× f ) where: f = input frequency in MHz; C = output load capacitance in pF;
CC o i L
D
PD
CC
i
L
2
f = output frequency in MHz; V = supply voltage in V; S (C × V
o
× f ) = sum of outputs.
o
CC
L
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE NORTH
AMERICA
DRAWING
NUMBER
NORTH AMERICA
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
–40°C to +85°C
74ALVCH16843 DGG
ACH16843 DGG
SOT364-1
2
1998 Aug 04
853–2108 019833
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
PIN DESCRIPTION
LOGIC SYMBOL
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
55
2
56
1
1CLR
Clear input (active LOW)
Output enable input (active
LOW)
1PRE
1LE
1D
1CLR
1OE
2
1OE
1PRE
1LE
3
5
54
52
51
49
48
47
45
44
43
1Q
0
1
2
3
4
5
6
7
8
0
1
55
56
Preset input (active LOW)
1D
1D
1D
1D
1D
1D
1D
1D
1Q
1Q
1Q
1Q
1Q
1Q
1Q
6
2
3
4
5
6
7
Latch enable input (active
HIGH)
8
9
54, 52, 51, 49, 48,
47, 45, 44, 43
1D0 to 1D8
1Q0 to 1Q8
GND
Data inputs
10
12
13
3, 5, 6, 8, 9,
10, 12, 13, 14
Data outputs
14
15
16
17
19
20
21
23
24
26
1Q
2Q
8
4, 11, 18, 25,
32, 39, 46, 53
Ground (0V)
0
2D
42
41
0
2Q
2Q
1
2D
1
7, 22, 35, 50
V
CC
Positive supply voltage
2
40
38
37
36
34
33
31
2D
2D
2D
2D
2D
2
3
4
5
6
Output enable input (active
LOW)
27
28
29
30
2OE
2CLR
2Q
3
2Q
4
2Q
5
2Q
6
Clear input (active LOW)
Latch enable input (active
HIGH)
2LE
2Q
2Q
7
2D
2D
7
8
2PRE
Preset input (active LOW)
Data inputs
8
2PRE
30
2LE
2CLR
2OE
27
42, 41, 40, 38, 37,
36, 34, 33, 31
2D0 to 2D8
28
29
15, 16, 17, 19, 20,
21, 23, 24, 26
2Q0 to 2Q8
Data outputs
FUNCTION TABLE
SH00144
INPUTS
OUTPUT
nPRE
nCLR
nOE
LE
X
D
Q
H
L
X
L
H
H
H
H
X
X
L
L
L
L
L
L
H
X
X
X
L
H
H
H
X
H
H
H
H
L
H
X
X
H
Q
0
Z
H
L
X
Z
=
=
=
=
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
3
1998 Aug 04
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
LOGIC DIAGRAM
LOGIC SYMBOL (IEEE/IEC)
nD
0
1OE
2
56
1
EN4
S2
1PRE
1CLR
R3
56
1LE
C1
D
2OE 27
CLR
PDRE
EN8
S6
30
28
2PRE
2CLR
LE
R7
29
2LE
C5
nCLR
nPRE
1D
54
52
51
49
48
47
45
1D
0
2, 3, 4
3
5
6
8
9
1Q
1Q
1Q
1Q
1Q
0
1
2
3
4
5
6
7
1D
1
1D
2
nLE
1D
3
nOE
1D
4
1D
5
10 1Q
12 1Q
13 1Q
nQ
0
1D
6
1D
7
44
43
SH00146
14
1D
8
1Q
8
42
41
15 2Q
6, 7, 8
5D
0
2D
0
BUS HOLD CIRCUIT
2Q
16
1
2
3
2D
1
2Q
2Q
V
17
19
20
21
23
24
26
2D 40
CC
2
2D 38
3
2Q
4
2D 37
4
2Q
5
2Q
6
2Q
7
2D 36
5
2D
34
33
31
6
2D
2D
7
8
Data Input
To internal circuit
2Q
8
SH00145
SW00044
4
1998 Aug 04
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
2.3
2.7
V
CC
V
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
3.0
3.6
V
DC Input voltage range
0
0
V
V
V
V
I
CC
V
O
DC output voltage range
CC
T
amb
Operating free-air temperature range
–40
+85
°C
V
CC
V
CC
= 2.3 to 3.0V
= 3.0 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +4.6
–50
UNIT
V
V
CC
IK
I
DC input diode current
V t0
I
mA
2
For control pins
–0.5 to +4.6
V
DC input voltage
V
I
2
For data inputs
uV or V t 0
–0.5 to V +0.5
CC
I
DC output diode current
DC output voltage
V
O
mA
V
"50
OK
CC
O
V
O
Note 2
= 0 to V
CC
–0.5 to V +0.5
CC
I
O
DC output source or sink current
V
O
mA
mA
°C
"50
"100
I
, I
DC V or GND current
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
–plastic medium-shrink (SSOP)
–plastic thin-medium-shrink (TSSOP) above +55°C derate linearly with 8 mW/K
For temperature range: –40 to +125 °C
above +55°C derate linearly with 11.3 mW/K
850
600
P
TOT
mW
NOTE:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5
1998 Aug 04
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
1.7
TYP
1.2
1.5
1.2
1.5
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 to 2.7V
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 2.3 to 2.7V
= 2.7 to 3.6V
2.0
0.7
0.8
V
IL
= 2.3 to 3.6V; V = V or V ; I = –100µA
V
*0.2
V
CC
I
IH
IL
O
CC
= 2.3V; V = V or V ; I = –6mA
V
V
V
V
V
0.3
0.6
0.5
0.6
V
V
V
V
V
0.08
0.26
0.14
0.09
0.28
*
*
*
*
*
I
IH
IL
O
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 2.3V; V = V or V ; I = –12mA
*
*
*
*
I
IH
IL
O
V
OH
HIGH level output voltage
V
= 2.7V; V = V or V ; I = –12mA
I
IH
IL
O
= 3.0V; V = V or V ; I = –12mA
I
IH
IL
O
= 3.0V; V = V or V
I
= –24mA
*1.0
CC
I
IH
IL; O
= 2.3 to 3.6V; V = V or V ; I = 100µA
GND
0.07
0.15
0.14
0.27
0.20
0.40
0.70
0.40
0.55
V
V
I
IH
IL
O
= 2.3V; V = V or V ; I = 6mA
I
IH
IL
O
= 2.3V; V = V or V ; I = 12mA
V
OL
LOW level output voltage
I
IH
IL
O
= 2.7V; V = V or V ; I = 12mA
V
I
IH
IL
O
= 3.0V; V = V or V
I = 24mA
IL; O
I
IH
V
= 2.3 to 3.6V;
CC
CC
I
Input leakage current
0.1
5
µA
µA
I
V = V or GND
I
V
V
= 2.3 to 3.6V; V = V or V ;
I IH IL
CC
O
I
3-State output OFF-state current
0.1
0.2
10
OZ
= V or GND
CC
I
Quiescent supply current
V
CC
= 2.3 to 3.6V; V = V or GND; I = 0
40
µA
µA
CC
I
CC
O
∆I
CC
Additional quiescent supply current
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3V to 3.6V; V = V – 0.6V; I = 0
150
–
750
I
CC
O
= 2.3V; V = 0.7V
45
I
2
I
Bus hold LOW sustaining current
Bus hold HIGH sustaining current
µA
µA
BHL
= 3.0V; V = 0.8V
75
–45
–75
500
–500
150
I
= 2.3V; V = 1.7V
I
2
I
BHH
= 3.0V; V = 2.0V
–175
I
2
2
I
Bus hold LOW overdrive current
Bus hold HIGH overdrive current
= 3.6V
= 3.6V
µA
µA
BHLO
I
BHHO
NOTES:
1. All typical values are at T
= 25°C.
amb
2. Valid for data inputs of bus hold parts.
6
1998 Aug 04
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
AC CHARACTERISTICS FOR V = 2.3V TO 2.7V RANGE
CC
GND = 0V; t = t ≤ 2.0ns; C = 30pF
r
f
L
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 2.3 to 2.7V
UNIT
1
MIN
TYP
MAX
Propagation delay
nDn to nQn
1, 6
2, 6
1, 6
1, 6
5, 6
5, 6
1.0
2.2
2.3
2.5
2.5
2.8
2.2
4.3
Propagation delay
nLE to nQn
1.0
1.0
1.0
1.0
1.1
4.6
4.8
4.8
5.8
4.3
t
/t
ns
PHL PLH
Propagation delay
nPRE to nQn
Propagation delay
nCLR to nQn
3-State output enable time
nOE to nQn
t
t
/t
ns
ns
PZH PZL
3-State output disable time
nOE to nQn
/t
PHZ PLZ
t
Set-up time nDn to nLE
Hold time nDn to nLE
3, 6
3, 6
2, 6
4, 6
4, 6
4, 6
4, 6
0.5
0.9
1.5
1.5
1.5
0.5
0.5
–0.1
0.5
0.5
0.5
0.5
1.1
1.0
–
–
–
–
–
–
–
ns
ns
SU
t
h
nLE pulse width HIGH
nPRE pulse width LOW
nCLR pulse width LOW
Recovery time nPRE to nLE
Recovery time nCLR to nLE
t
ns
ns
W
t
REM
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
AC CHARACTERISTICS FOR V = 3.0V TO 3.6V RANGE AND V = 2.7V
CC
CC
GND = 0V; t = t ≤ 2.5ns; C = 50pF
r
f
L
LIMITS
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3 ± 0.3V
V
CC
= 2.7V
UNIT
1, 2
1
MIN
TYP
MAX
MIN
TYP
MAX
Propagation delay
nDn to nQn
1, 6
2, 6
1, 6
1, 6
5, 6
5, 6
1.0
1.0
1.0
1.0
1.0
1.3
2.1
3.5
1.0
2.3
2.1
2.6
2.5
3.0
2.8
4.0
Propagation delay
nLE to nQn
2.0
2.2
2.3
2.5
2.6
3.5
3.8
3.9
4.4
4.0
1.0
1.0
1.0
1.0
1.3
3.9
4.5
4.3
5.3
4.4
t
/t
ns
PHL PLH
Propagation delay
nPRE to nQn
Propagation delay
nCLR to nQn
3-State output enable time
nOE to nQn
t
t
/t
ns
ns
PZH PZL
3-State output disable time
nOE to nQn
/t
PHZ PLZ
t
Set-up time nDn to nLE
Hold time nDn to nLE
3, 6
3, 6
2, 6
4, 6
4, 6
4, 6
4, 6
0.5
0.9
1.5
1.5
1.5
1.0
0.8
0.0
0.5
0.5
0.5
0.5
0.4
0.2
–
–
–
–
–
–
–
0.5
0.9
1.5
1.5
1.5
0.8
0.6
–0.3
0.5
–
–
–
–
–
–
–
ns
ns
SU
t
h
nLE pulse width HIGH
nPRE pulse width LOW
nCLR pulse width LOW
Recovery time nPRE to nLE
Recovery time nCLR to nLE
0.5
t
0.6
ns
ns
W
0.5
–0.2
–0.4
t
REM
NOTES:
1. All typical values are measured T
= 25°C.
amb
2. Typical value is measured at V = 3.3V
CC
7
1998 Aug 04
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
AC WAVEFORMS FOR V = 2.3V TO 2.7V AND
CC
V
I
V
< 2.3V RANGE
CC
Dn
INPUT
V
M
V
V
V
V
= 0.5 V
M
X
Y
= V + 0.15V
GND
OL
th
th
= V –0.15V
OH
and V are the typical output voltage drop that occur with the
t
t
SU
SU
OL
OH
V
I
output load.
V
LE
INPUT
= V
V
I
CC
M
GND
AC WAVEFORMS FOR V = 3.0V TO 3.6V AND
CC
NOTE: The shaded areas indicate when the input is permitted to change
V
= 2.7V RANGE
for predictable output performance.
CC
V
V
V
V
= 1.5 V
M
X
Y
SH00149
= V + 0.3V
OL
= V –0.3V
Waveform 3. Data set-up and hold times for the Dn input to the
LE input
OH
and V are the typical output voltage drop that occur with the
OL
OH
output load.
V
= 2.7V
I
V
I
CLR, D
V
I
n
V
M
CLR, PRE
GND
V
M
t
PRE
GND
t
W(L)
t
t
REM
PHL
PLH
V
I
V
OH
LE
V
M
Q
n
OUTPUT
V
M
GND
V
OL
SH00148
SH00147
Waveform 4. Clear (CLR) and preset (PRE) pulse width, the
clear (CLR) and preset (PRE) to latch (LE) removal time
Waveform 1. Data input (Dn) to output (Qn), clear input (CLR)
to output (Qn) and preset input (PRE) to output (Qn)
propagation delay
V
I
V
I
V
nOE INPUT
GND
M
V
V
M
M
LE INPUT
GND
t
W
t
t
PLH
PHL
t
t
PZL
PLZ
V
OH
V
CC
Qn OUTPUT
V
M
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
V
OL
V
X
V
OL
SH00150
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Qn) propagation delay
t
t
PZH
PHZ
V
OH
OUTPUT
V
Y
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
SH00137
Waveform 5. 3-State enable and disable times
8
1998 Aug 04
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
TEST CIRCUIT
S
1
2 * V
V
CC
CC
Open
GND
R
R
= 500 Ω
= 500 Ω
L
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
R
T
C
L
Test Circuit for switching times
DEFINITIONS
R
L
C
L
R
T
= Load resistor
= Load capacitance includes jig and probe capacitance
= Termination resistance should be equal to Z of pulse generators.
OUT
SWITCH POSITION
TEST
S
V
V
I
1
CC
t
t
Open
< 2.7V
V
CC
PLH/ PHL
t
t
t
2.7–3.6V
2.7V
PLZ/ PZL
2 < V
CC
t
GND
PHZ/ PZH
SV00906
Waveform 6. Load circuitry for switching times
9
1998 Aug 04
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
10
1998 Aug 04
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
NOTES
11
1998 Aug 04
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 07-98
9397-750-04562
Document order number:
Philips
Semiconductors
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