74AVC16373DGG,512 [NXP]
74AVC16373 - 16-bit D-type transparent latch; 3.6 V tolerant; 3-state TSSOP 48-Pin;
| 型号： | 74AVC16373DGG,512 |
| 厂家： | 
NXP |
| 描述： | 74AVC16373 - 16-bit D-type transparent latch; 3.6 V tolerant; 3-state TSSOP 48-Pin |
| 文件： | 总16页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AVC16373
16-bit D-type transparent latch;
3.6 V tolerant; 3-state
Product Specification
2000 Mar 09
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC24
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.2 to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7
• CMOS low power consumption
The 74AVC16373 is a 16-bit D-type transparent latch
featuring separate D-type inputs for each latch, and
3-state outputs for bus oriented applications. One Latch
Enable (LE) input and one Output Enable (OE) input are
provided per 8-bit section. The 74AVC16373 consist of
two sections of eight D-type transparent latches with
3-state true outputs.
• Input/output tolerant up to 3.6 V
• Dynamic Controlled Output (DCO) circuit dynamically
changes output impedance, resulting in noise reduction
without speed degradation
The 74AVC16373 is designed to have an extremely fast
propagation delay and a minimum amount of power
consumption.
• Low inductance multiple VCC and GND pins to minimize
noise and ground bounce
• Supports Live Insertion.
To ensure the high-impedance output state during
power-up or power-down, pin OEn should be tied to VCC
through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is
implemented to support termination line drive during
transient (see Figs 1 and 2).
MNA506
MNA507
0
300
handbook, halfpage
handbook, halfpage
I
I
OH
OL
(mA)
(mA)
3.3 V
1.8 V
−100
200
2.5 V
2.5 V
−200
100
1.8 V
3.3 V
−300
0
0
1
2
3
4
0
1
2
3
4
V
(V)
V
(V)
OL
OH
Fig.1 Output voltage as a function of the
HIGH-level output current.
Fig.2 Output voltage as a function of the
LOW-level output current.
2000 Mar 09
2
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns.
SYMBOL
PARAMETER
propagation delay
CONDITIONS
TYP.
UNIT
tPHL/tPLH
VCC = 1.2 V
3.6
3.1
2.2
1.6
1.4
5.0
ns
ns
ns
ns
ns
pF
nDn to nQn
V
CC = 1.5 V
CC = 1.8 V
V
VCC = 2.5 V
CC = 3.3 V
V
CI
input capacitance
CPD
power dissipation
capacitance per buffer
notes 1 and 2
outputs enabled 34
outputs disabled
pF
pF
1
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
∑ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC
.
FUNCTION TABLE
See note 1.
INPUTS
LE
OUTPUTS
nYn
INTERNAL
LATCHES
OPERATING MODES
nOE
nAn
Enable and read register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
Latch and read register
(hold mode)
L
L
L
L
l
h
L
H
L
H
Latch register and disable outputs
H
H
L
L
l
h
L
H
Z
Z
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high impedance OFF-state.
2000 Mar 09
3
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
ORDERING AND PACKAGE INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74AVC16373DGG
−40 to +85 °C
48
TSSOP
plastic
SOT362-1
PINNING
PIN
SYMBOL
DESCRIPTION
1
1OE
output enable input (active LOW)
data outputs
2, 3, 5, 6, 8, 9, 11 and 12
1Q0 to 1Q7
GND
4, 10, 15, 21, 28, 34, 39 and 45
ground (0 V)
7, 18, 31 and 42
VCC
DC supply voltage
13, 14, 16, 17, 19, 20, 22 and 23
2Q0 to 2Q7
2OE
data outputs
24
output enable input (active LOW)
latch enable input (active HIGH)
data inputs
25
2LE
26, 27, 29, 30, 32, 33, 35 and 36
37, 38, 40, 41, 43, 44, 46 and 47
48
2D7 to 2D0
1D7 to 1D0
1LE
data inputs
latch enable input (active HIGH)
2000 Mar 09
4
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
handbook, halfpage
1OE
1
2
3
4
5
6
7
8
9
48 1LE
1Q
0
47 1D
0
1Q
1
46 1D
1
1
24
GND
45 GND
handbook, halfpage
1Q
2
44 1D
2
1OE
2OE
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D
1Q
0
1Q
3
43 1D
3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
3
1D
1D
1D
1D
1D
1D
1D
2D
2D
2D
2D
2D
2D
2D
2D
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
V
42
V
CC
CC
5
1Q
4
41 1D
40 1D
4
6
1Q
5
8
5
9
GND 10
39 GND
11
12
13
14
16
17
19
20
22
23
1Q 11
6
38 1D
6
1Q 12
7
37 1D
7
16373
2Q 13
0
36 2D
0
2Q 14
1
35 2D
1
GND 15
34 GND
2Q 16
2
33 2D
2
2Q 17
3
32 2D
3
V
18
31
V
CC
CC
1LE
2LE
2Q 19
4
30 2D
4
5
MNA547
48
25
2Q 20
5
29 2D
GND 21
28 GND
2Q 22
6
27 2D
6
2Q 23
7
26 2D
7
2OE 24
25 2LE
MNA541
Fig.3 Pin configuration.
Fig.4 Logic symbol.
2000 Mar 09
5
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
1
48
24
25
handbook, halfpage
1EN
C3
1OE
1LE
2OE
2LE
2EN
C4
2
3
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D
0
1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
3D
1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1D
1
5
1D
2
6
1D
3
8
1D
4
9
1D
5
11
12
13
14
16
17
19
20
22
23
1D
6
1D
7
2D
0
4D
2
2D
1
2D
2
2D
3
2D
4
2D
5
2D
6
2D
7
MNA546
Fig.5 IEEE/IEC logic symbol.
1D
D
Q
1Q
2D
0
D
Q
2Q
0
0
0
LATCH
1
LATCH
9
LE
LE
1LE
2LE
1OE
2OE
to 7 other channels
to 7 other channels
MNA545
Fig.6 Logic diagram.
6
2000 Mar 09
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
MAX.
1.6
UNIT
VCC
according to JEDEC Low Voltage 1.4
Standards
V
V
V
V
V
V
V
V
1.65
1.95
2.7
3.6
3.6
3.6
3.6
VCC
+85
40
2.3
3.0
1.2
0
for low-voltage applications
VI
DC input voltage
DC output voltage
VO
output 3-state
0
output HIGH or LOW state
in free air
0
Tamb
tr, tf
operating ambient temperature
input rise and fall time ratios
−40
0
°C
VCC = 1.4 to 1.6 V
ns/V
ns/V
ns/V
ns/V
V
V
V
CC = 1.65 to 2.3 V
CC = 2.3 to 3.0 V
CC = 3.0 to 3.6 V
0
30
0
20
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+4.6
UNIT
VCC
IIK
V
DC input diode current
DC input voltage
VI < 0
for inputs; note 1
−
−50
+4.6
−50
mA
V
VI
−0.5
−
IOK
VO
DC output clamping diode current VO < 0
mA
DC output voltage
output HIGH or LOW state; note 1 −0.5
VCC + 0.5 V
output 3-state; note 1
VO = 0 to VCC
−0.5
−
+4.6
50
V
IO
DC output sink current
mA
mA
°C
ICC, IGND DC VCC or GND current
−
±100
+150
500
Tstg
PD
storage temperature
−65
−
power dissipation per package
for temperature range:
mW
−40 to +85 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 60 °C the value of PD derates linearly with 5.5 mW/K.
2000 Mar 09
7
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
OTHER VCC (V)
Tamb = −40 to +85 °C
SYMBOL
PARAMETER
UNIT
MAX.
MIN.
VCC
0.65 × VCC 0.9
TYP.(1)
VIH
HIGH-level input
voltage
1.2
−
−
V
V
V
V
V
V
V
V
V
V
1.4 to 1.6
−
1.65 to 1.95 0.65 × VCC 0.9
−
2.3 to 2.7
3.0 to 3.6
1.2
1.7
2.0
−
1.2
1.5
−
−
−
VIL
LOW-level input
voltage
GND
1.4 to 1.6
−
0.9
0.9
1.2
1.5
0.35 × VCC
0.35 × VCC
0.7
1.65 to 1.95 −
2.3 to 2.7
3.0 to 3.6
−
−
0.8
VOH
HIGH-level output VI = VIH or VIL
voltage
IO = −100 µA
1.65 to 3.6
1.4
V
V
V
V
V
CC − 0.20 VCC
−
−
−
−
−
V
V
V
V
V
IO = −3 mA
IO = −4 mA
IO = −8 mA
IO = −12 mA
CC − 0.35
CC − 0.45
CC − 0.55
CC − 0.70
VCC − 0.23
VCC − 0.25
VCC − 0.38
VCC − 0.48
1.65
2.3
3.0
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 3 mA
1.65 to 3.6
1.4
−
−
−
−
−
−
GND
0.18
0.22
0.37
0.51
0.1
0.20
0.35
0.45
0.55
0.70
2.5
V
V
IO = 4 mA
1.65
V
IO = 8 mA
2.3
V
IO = 2 mA
3.0
V
II
input leakage
current per pin
VI = VCC or GND
1.4 to 3.6
µA
Ioff
power-off leakage VI or VO = 3.6 V
current
0
−
−
0.1
0.1
±10
µA
µA
IIHZ/IILZ
input current for
common I/O pins
VI = VCC or GND
1.4 to 3.6
12.5
IOZ
3-state output
OFF−state current VO = VCC or GND
VI = VIH or VIL;
1.4 to 2.7
3.0 to 3.6
1.4 to 2.7
3.0 to 3.6
−
−
−
−
0.1
0.1
0.1
0.2
5
µA
µA
µA
µA
10
20
40
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
Note
1. All typical values are measured at Tamb = 25 °C.
2000 Mar 09
8
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.0 ns.
TEST CONDITIONS
Tamb = −40 to +85 °C
MIN. TYP.(1) MAX.
SYMBOL
PARAMETER
UNIT
ns
WAVEFORMS
VCC (V)
1.2
tPHL/tPLH
propagation delay nDn to nQn
see Figs 7 and 11
−
3.6
3.1
2.2
1.6
1.4
3.6
3.1
2.2
1.6
1.4
5.9
4.2
3.5
2.4
2.0
5.8
4.6
3.6
1.9
2.1
2.4
1.9
1.7
1.6
1.4
0.4
0.2
0.1
−0.1
−0.1
−0.2
−0.1
0.0
0.1
0.2
−
1.40 to 1.60 1.2
1.65 to 1.95 1.0
6.8
5.7
3.3
2.8
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.3 to 2.7
3.0 to 3.6
1.2
0.7
0.7
−
propagation delay nLE to nQn
see Figs 8 and 11
see Figs 9 and 11
see Figs 9 and 11
see Figs 8 and 11
1.40 to 1.60 2.5
1.65 to 1.95 2.3
9.4
7.8
4.2
3.9
−
2.3 to 2.7
3.0 to 3.6
1.2
1.3
0.7
−
t
PZH/tPZL
3-state output enable time
nOE to nQn
1.40 to 1.60 1.6
1.65 to 1.95 1.6
8.8
6.7
4.3
3.4
−
2.3 to 2.7
3.0 to 3.6
1.2
1.4
0.7
−
tPHZ/tPLZ
3-state output disable time
nOE to nQn
1.40 to 1.60 2.5
1.65 to 1.95 2.3
9.4
7.8
4.2
3.9
−
2.3 to 2.7
3.0 to 3.6
1.2
1.3
1.2
−
tW
tsu
th
nLE pulse width HIGH
set-up time nDn to nLE
hold time nDn to nLE
1.40 to 1.60
−
−
1.65 to 1.95 2.2
−
2.3 to 2.7
3.0 to 3.6
2.0
1.8
−
−
−
see Figs 10 and 11 1.2
−
1.40 to 1.60 1.2
1.65 to 1.95 1.1
−
−
2.3 to 2.7
3.0 to 3.6
+0.9
−
+0.8
−
see Figs 10 and 11 1.2
−
−
1.40 to 1.60 +1.1
1.65 to 1.95 1.1
−
−
2.3 to 2.7
3.0 to 3.6
1.1
1.0
−
−
Note
1. All typical values are measured at Tamb = 25 °C and at VCC respectively 1.2, 1.5, 1.8, 2.5 and 3.3 V.
2000 Mar 09
9
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
AC WAVEFORMS
V
I
nD input
n
V
M
GND
t
t
PHL
PLH
V
OH
V
nQ output
n
M
V
OL
MNA544
VCC
VM
VI
≤2.3 to 2.7 V
0.5 × VCC
0.5 × VCC
VCC
VCC
3.0 to 3.6 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 The input (nDn) to output (nQn) propagation delay.
V
I
nLE input
V
V
t
M
t
M
GND
t
W
PLH
PHL
V
OH
nQ output
n
V
M
V
MNA543
OL
VCC
VM
VI
≤2.3 to 2.7 V
0.5 × VCC
0.5 × VCC
VCC
VCC
3.0 to 3.6 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.8 The latch enable input (nLE) pulse width to output (nQn) propagation delays.
10
2000 Mar 09
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
V
I
nOE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA478
VCC
VM
VX
VY
VI
≤2.3 to 2.7 V 0.5 × VCC
3.0 to 3.6 V 0.5 × VCC
VOL + 0.15 V
VOL + 0.3 V
V
OH − 0.15 V
OH − 0.3 V
VCC
VCC
V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.9 3-state enable and disable times.
V
I
nD input
V
n
M
GND
t
t
h
h
t
t
su
su
V
I
nLE input
GND
V
M
MNA542
VCC
VM
VI
≤2.3 to 2.7 V 0.5 × VCC
3.0 to 3.6 V 0.5 × VCC
VCC
VCC
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.10 Data set-up and hold times for nDn input to nLE input.
11
2000 Mar 09
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
S1
2 × V
open
GND
CC
V
CC
R
R
load
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
L
load
T
MNA505
VCC (V)
VI
Rload
CL
1.2
VCC
VCC
2000 Ω 15 pF
2000 Ω 15 pF
1000 Ω 30 pF
TEST
S1
open
1.4 to 1.6
tPLH/tPHL
1.65 to 1.95 VCC
t
PLZ/tPZL
2 × VCC
2.3 to 2.7
3.0 to 3.6
VCC
VCC
500 Ω
500 Ω
30 pF
30 pF
tPHZ/tPZH
GND
Fig.11 Load circuitry for switching times.
2000 Mar 09
12
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
PACKAGE OUTLINE
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
H
v
M
A
y
E
Z
48
25
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.8
0.4
mm
1.2
0.25
0.5
1
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-10
99-12-27
SOT362-1
MO-153
2000 Mar 09
13
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Mar 09
14
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Mar 09
15
Philips Semiconductors – a worldwide company
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613507/02/pp16
Date of release: 2000 Mar 09
Document order number: 9397 750 06897
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