74HC283N [PHILIPS]
Adder/Subtractor, CMOS, PDIP16,;
| 型号： | 74HC283N |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | Adder/Subtractor, CMOS, PDIP16, 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT283
4-bit binary full adder with fast carry
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
C
IN + (A1 + B1) + 2(A2 + B2) + +4(A3 + B3) + 8(A4 + B4) =
FEATURES
= ∑1 + 2∑2 + 4∑3 + 8∑4 + 16COUT
• High-speed 4-bit binary addition
• Cascadable in 4-bit increments
• Fast internal look-ahead carry
• Output capability: standard
• ICC category: MSI
Where (+) = plus.
Due to the symmetry of the binary add function, the “283”
can be used with either all active HIGH operands (positive
logic) or all active LOW operands (negative logic); see
function table. In case of all active LOW operands the
results ∑1 to ∑4 and COUT should be interpreted also as
active LOW. With active HIGH inputs, CIN must be held
LOW when no “carry in” is intended. Interchanging inputs
of equal weight does not affect the operation, thus CIN, A1,
B1 can be assigned arbitrarily to pins 5, 6, 7, etc.
GENERAL DESCRIPTION
The 74HC/HCT283 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
See the “583” for the BCD version.
The 74HC/HCT283 add two 4-bit binary words (An plus Bn)
plus the incoming carry. The binary sum appears on the
sum outputs (∑1 to ∑4) and the out-going carry (COUT
)
according to the equation:
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC = 5 V
C
C
C
C
IN to ∑1
IN to ∑2
IN to ∑3
IN to ∑4
16
18
20
23
21
20
20
15
ns
21
23
27
25
23
24
3.5
92
ns
ns
ns
ns
ns
ns
pF
pF
An or Bn to ∑n
IN to COUT
C
An or Bn to COUT
input capacitance
CI
3.5
88
CPD
power dissipation capacitance per package notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
December 1990
2
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
4, 1, 13, 10
∑1 to ∑4
A1 to A4
B1 to B4
CIN
sum outputs
5, 3, 14, 12
A operand inputs
B operand inputs
carry input
6, 2, 15, 11
7
8
GND
ground (0 V)
9
COUT
carry output
16
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
Fig.4 Functional diagram.
FUNCTION TABLE
COUT EXAMPLE(2)
∑
∑
∑
∑
4
PINS
CIN A1 A2 A3
A4 B1
B2
B3 B4
1
2
3
logic levels
active HIGH
active LOW
L
0
1
L
0
1
H
1
0
L
0
1
H
1
0
H
1
0
L
0
1
L
0
1
H
1
0
H
H
L
L
H
(3)
1
0
1
0
0
1
0
1
1
(4)
0
Note
1. H = HIGH voltage level
L = LOW voltage level
2. example
1001
1010
-----
10011
3. for active HIGH, example = (9 + 10 = 19)
4. for active LOW, example = (carry + 6 + 5 = 12)
December 1990
4
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
52
19
15
160
32
27
200
40
34
240
48
41
ns
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
CIN to ∑1
t
t
t
t
PHL/ tPLH propagation delay
58
21
17
180
36
31
225
45
38
270
54
46
2.0
4.5
6.0
CIN to ∑2
PHL/ tPLH propagation delay
63
23
18
195
39
33
245
49
42
295
59
50
2.0
4.5
6.0
CIN to ∑3
PHL/ tPLH propagation delay
74
27
22
230
46
39
290
58
49
345
69
59
2.0
4.5
6.0
C
IN to ∑4
PHL/ tPLH propagation delay
69
25
20
210
42
36
265
53
45
315
63
54
2.0
4.5
6.0
An or Bn to ∑n
tPHL/ tPLH propagation delay
CIN to COUT
63
23
18
195
39
33
245
49
42
295
59
50
2.0
4.5
6.0
t
t
PHL/ tPLH propagation delay
An or Bn to COUT
63
23
18
195
39
33
245
49
42
295
59
50
2.0
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
December 1990
6
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
CIN
B2, A2, A1
B1
1.50
1.00
0.40
B4, A4, A3, B3
0.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
74HCT
TEST CONDITIONS
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
18
25
27
31
29
27
28
7
31
43
46
53
49
46
48
15
39
54
58
66
61
58
60
19
47
65
69
80
74
69
72
22
ns
ns
ns
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
Fig.6
CIN to ∑1
t
t
t
t
t
PHL/ tPLH propagation delay
IN to ∑2
C
PHL/ tPLH propagation delay
CIN to ∑3
PHL/ tPLH propagation delay
CIN to ∑4
PHL/ tPLH propagation delay
An or Bn to ∑n
PHL/ tPLH propagation delay
CIN to COUT
tPHL/ tPLH propagation delay
An or Bn to COUT
t
THL/ tTLH output transition time
December 1990
7
Philips Semiconductors
Product specification
4-bit binary full adder with fast carry
74HC/HCT283
AC WAVEFORMS
APPLICATION INFORMATION
Fig.7 3-bit adder.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the inputs (CIN, An, Bn)
to the outputs (∑n, COUT) propagation delays
and the output transition times.
Fig.8 2-bit and 1-bit adder.
Fig.9 5-input encoder.
Notes to Figs 7 to 10
Figure 7 shows a 3-bit adder using the “283”. Tying the
operand inputs of the fourth adder (A3, B3) LOW makes ∑3
dependent on, and equal to, the carry from the third adder.
Based on the same principle, Figure 8 shows a method of
dividing the “283” into a 2-bit and 1-bit adder. The third
stage adder (A2, B2, ∑ 2) is used simply as means of
transferring the carry into the fourth stage (via A2 and B2)
and transferring the carry from the second stage on ∑ 2.
Note that as long as long as A2 and B2 are the same, HIGH
or LOW, they do not influence ∑ 2. Similarly, when A2 and
B2 are the same, the carry into the third stage does not
influence the carry out of the third stage. Figure 9 shows a
method of implementing a 5-input encoder, where the
Fig.10 5-input majority gate.
inputs are equally weighted. The outputs ∑ 0, ∑1 and ∑ 2
produce a binary number equal to the number inputs (I1 to
I5) that are HIGH. Figure 10 shows a method of
implementing a 5-input majority gate. When three or more
inputs (I1 to I5) are HIGH, the output M5 is HIGH.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
8
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