933372600652 [NXP]
IC 4000/14000/40000 SERIES, DUAL 4-INPUT NOR GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate;
| 型号： | 933372600652 |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, DUAL 4-INPUT NOR GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate 栅 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总3页 (文件大小：25K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4002B
gates
Dual 4-input NOR gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4002B
gates
Dual 4-input NOR gate
DESCRIPTION
The HEF4002B provides the positive dual 4-input NOR
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.2 Pinning diagram.
HEF4002BP(N):
HEF4002BD(F):
HEF4002BT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
Fig.1 Functional diagram.
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4002B
gates
Dual 4-input NOR gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
SYMBOL
TYP. MAX.
FORMULA
Propagation delays
5
60
25
20
60
30
20
60
30
20
120 ns 33 ns + (0,55 ns/pF) CL
50 ns 14 ns + (0,23 ns/pF) CL
40 ns 12 ns + (0,16 ns/pF) CL
120 ns 10 ns + (1,0 ns/pF) CL
In → On
10
15
5
tPHL; tPLH
Output transition times
HIGH to LOW
10
15
5
tTHL
60 ns
40 ns
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
120 ns 10 ns + (1,0 ns/pF) CL
LOW to HIGH
10
15
tTLH
60 ns
40 ns
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
1050 fi + ∑ (foCL) × VDD
where
2
10
15
4300 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
11 700 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
V
DD = supply voltage (V)
January 1995
3
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