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SC18IS602B

I²C-bus to SPI bridge

Rev. 5 — 3 August 2010

Product data sheet

1. General description

The SC18IS602B is designed to serve as an interface between a standard I²C-bus of a

microcontroller and an SPI bus. This allows the microcontroller to communicate directly

with SPI devices through its I²C-bus. The SC18IS602B operates as an I²C-bus

slave-transmitter or slave-receiver and an SPI master. The SC18IS602B controls all the

SPI bus-specific sequences, protocol, and timing. The SC18IS602B has its own internal

oscillator, and it supports four SPI chip select outputs that may be configured as GPIO

when not used.

2. Features and benefits

I²C-bus slave interface operating up to 400 kHz

SPI master operating up to 1.8 Mbit/s

200-byte data buffer

Up to four slave select outputs

Up to four programmable I/O pins

Operating supply voltage: 2.4 V to 3.6 V

Low power mode

Internal oscillator option

Active LOW interrupt output

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 that exceeds 100 mA

Very small 16-pin TSSOP

3. Applications

Converting I²C-bus to SPI

Adding additional SPI bus controllers to an existing system

SC18IS602B

NXP Semiconductors

I²C-bus to SPI bridge

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

SC18IS602BIPW

TSSOP16

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

5. Block diagram

MOSI

MISO

SPICLK

SS0

SCL

SDA

2

I C-BUS

BUFFER

SPI

SS1

(1)

SS2

SS3

CONTROL

REGISTER

SC18IS602B

RESET

INT

INTERRUPT

CONTROL

LOGIC

INTERNAL

OSCILLATOR

002aac443

(1) Unused slave select outputs may be used for GPIO.

Fig 1. Block diagram of SC18IS602B

SC18IS602B

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I²C-bus to SPI bridge

6. Pinning information

6.1 Pinning

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SS0/GPIO0

SS1/GPIO1

RESET

A2

A1

A0

V

SS3/GPIO3

SS

SC18IS602BIPW

MISO

MOSI

SDA

V

DD

SPICLK

SS2/GPIO2

INT

SCL

002aac441

Fig 2. Pin configuration for TSSOP16

6.2 Pin description

Table 2.

Symbol

Pin description

Type

Description

SS0/GPIO0

SS1/GPIO1

RESET

V_SS

1

I/O

I

SPI slave select output 0 (active LOW) or GPIO 0

SPI slave select output 1 (active LOW) or GPIO 1

reset input (active LOW)

ground supply

2

3

4

-

MISO

5

I

Master In, Slave Out

MOSI

6

O

I/O

I

Master Out, Slave In

I²C-bus data

I²C-bus clock

SDA

7

SCL

8

INT

9

O

I/O

O

-

interrupt output (active LOW)

SPI slave select output 2 (active LOW) or GPIO 2

SPI clock

SS2/GPIO2

SPICLK

V_DD

10

11

12

13

14

15

16

supply voltage

SS3/GPIO3

A0

I/O

I

SPI slave select output 3 (active LOW) or GPIO 3

address input 0

A1

I

address input 1

A2

I

address input 2

SC18IS602B

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SC18IS602B

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I²C-bus to SPI bridge

7. Functional description

The SC18IS602B acts as a bridge between an I²C-bus and an SPI interface. It allows an

I²C-bus master device to communicate with any SPI-enabled device.

7.1 I²C-bus interface

The I²C-bus uses two wires (SDA and SCL) to transfer information between devices

connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi-master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I²C-bus may be used for test and diagnostic purposes

A typical I²C-bus configuration is shown in Figure 3. (Refer to NXP Semiconductors

UM10204, “I²C-bus specification and user manual”, at

www.nxp.com/documents/user_manual/UM10204.pdf.)

V

DD

R

PU

SDA

SCL

2

I C-bus

2

I C-BUS

DEVICE

I C-BUS

SC18IS602B

DEVICE

002aac445

Fig 3. I²C-bus configuration

The SC18IS602B device provides a byte-oriented I²C-bus interface that supports data

transfers up to 400 kHz. When the I²C-bus master is reading data from SC18IS602B, the

device will be a slave-transmitter. The SC18IS602B will be a slave-receiver when the

I²C-bus master is sending data. At no time does the SC18IS602B act as an I²C-bus

master, however, it does have the ability to hold the SCL line LOW between bytes to

complete its internal processes.

SC18IS602B

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I²C-bus to SPI bridge

7.1.1 Addressing

R/W

X

slave address

0

1

0

1

A2 A1 A0

programmable

fixed

002aac446

Fig 4. Slave address

The first seven bits of the first byte sent after a START condition defines the slave address

of the device being accessed on the bus. The eighth bit determines the direction of the

message. A ‘0’ in the least significant position of the first byte means that the master will

write information to a selected slave. A ‘1’ in this position means that the master will read

information from the slave. When an address is sent, each device in a system compares

the first seven bits after the START condition with its address. If they match, the device

considers itself addressed by the master as a slave-receiver or slave-transmitter,

depending on the R/W bit.

A slave address of the SC18IS602B is comprised of a fixed and a programmable part.

The programmable part of the slave address enables the maximum possible number of

such devices to be connected to the I²C-bus. Since the SC18IS602B has three

programmable address bits (defined by the A2, A1, and A0 pins), it is possible to have

eight of these devices on the same bus.

The state of the A2, A1, and A0 pins are latched at reset. Changes made after reset will

not alter the address.

When SC18IS602B is busy after the address byte is transmitted, it will not acknowledge

its address.

7.1.2 Write to data buffer

All communications to or from the SC18IS602B occur through the data buffer. The data

buffer is 200 bytes deep. A message begins with the SC18IS602B address, followed by

the Function ID. Depending upon the Function ID, zero to 200 data bytes can follow.

The SC18IS602B will place the data received into a buffer and continue loading the buffer

until a STOP condition is received. After the STOP condition is detected, further

communications will not be acknowledged until the function designated by the Function ID

has been completed.

S

SLAVE ADDRESS

W

A

FUNCTION ID

A

0 TO 200 BYTES

A

P

002aac447

Fig 5. Write to data buffer

7.1.3 SPI read and write - Function ID 01h to 0Fh

Data in the buffer will be sent to the SPI port if the Function ID is 01h to 0Fh. The Function

ID contains the Slave Select (SS) to be used for the transmission on the SPI port. There

are four Slave Selects that can be used, with each SS being selected by one of the bits in

SC18IS602B

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Product data sheet

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SC18IS602B

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I²C-bus to SPI bridge

the Function ID. There is no restriction on the number or combination of Slave Selects that

can be enabled for an SPI message. If more than one SSn pin is enabled at one time, the

user should be aware of possible contention on the data outputs of the SPI slave devices.

Table 3.

Function ID 01h to 0Fh

7

6

5

4

3

2

1

0

SS3

SS2

SS1

SS0

The data on the SPI port will contain the same information as the I²C-bus data, but without

the slave address and Function ID. For example, if the message shown in Figure 6 is

transmitted on the I²C-bus, the SPI bus will send the message shown in Figure 7.

write to buffer

SLAVE ADDRESS

FUNCTION

S

W

A

DATA 1

A

DATA n

A

P

ID

002aac448

Fig 6. I²C-bus message

SPI data

DATA 1

DATA n

002aac451

Fig 7. SPI message

The SC18IS602B counts the number of data bytes sent to the I²C-bus port and will

automatically send this same number of bytes to the SPI bus. As the data is transmitted

from the MOSI pin, it is also read from the MISO pin and saved in the data buffer.

Therefore, the old data in the buffer is overwritten. The data in the buffer can then be read

back.

If the data from the SPI bus needs to be returned to the I²C-bus master, the process must

be completed by reading the data buffer. Section 8 gives an example of an SPI read.

7.1.4 Read from buffer

A read from the data buffer requires no Function ID. The slave address with the R/W bit

set to a ‘1’ will cause the SC18IS602B to send the buffer contents to the I²C-bus master.

The buffer contents are not modified during the read process.

S

SLAVE ADDRESS

R

A

DATA 1

A

DATA n

NA

P

002aac449

Fig 8. Read from buffer

A typical write and read from an SPI EEPROM is shown in Section 8.

SC18IS602B

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Product data sheet

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SC18IS602B

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I²C-bus to SPI bridge

7.1.5 Configure SPI Interface - Function ID F0h

The SPI hardware operating mode, data direction, and frequency can be changed by

sending a ‘Configure SPI Interface’ command to the I²C-bus.

S

SLAVE ADDRESS

W

A

F0h

A

DATA

A

P

002aac450

Fig 9. Configure SPI Interface

After the SC18IS602B address is transmitted on the bus, the Configure SPI Interface

Function ID (F0h) is sent followed by a byte which will define the SPI communications.

The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing

data. The Clock Polarity bit (CPOL) allows the user to set the clock polarity. Figure 19 and

Figure 20 show the different settings of Clock Phase bit CPHA.

Table 4.

Bit

Configure SPI Interface (F0h) bit allocation

7

X

6

X

5

ORDER

0

4

X

3

2

1

F1

0

F0

0

Symbol

Reset

MODE1 MODE0

0

Table 5.

Configure SPI Interface (F0h) bit description

Bit

7:6

5

Symbol

-

Description

reserved

ORDER

When logic 0, the MSB of the data word is transmitted first.

If logic 1, the LSB of the data word is transmitted first.

4

-

reserved

3:2

MODE1:MODE0 Mode selection

00 - SPICLK LOW when idle; data clocked in on leading edge

(CPOL = 0, CPHA = 0)

01 - SPICLK LOW when idle; data clocked in on trailing edge

(CPOL = 0, CPHA = 1)

10 - SPICLK HIGH when idle; data clocked in on trailing edge

(CPOL = 1, CPHA = 0)

11 - SPICLK HIGH when idle; data clocked in on leading edge

(CPOL = 1, CPHA = 1)

1:0

F1:F0

SPI clock rate

00 - 1843 kHz

01 - 461 kHz

10 - 115 kHz

11 - 58 kHz

SC18IS602B

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I²C-bus to SPI bridge

7.1.6 Clear Interrupt - Function ID F1h

An interrupt is generated by the SC18IS602B after any SPI transmission has been

completed. This interrupt can be cleared (INT pin HIGH) by sending a ‘Clear Interrupt’

command. It is not necessary to clear the interrupt; when polling the device, this function

may be ignored.

S

SLAVE ADDRESS

W

A

F1h

A

P

002aac452

Fig 10. Clear Interrupt

7.1.7 Idle mode - Function ID F2h

A low-power mode may be entered by sending the ‘Idle Mode’ command.

S

SLAVE ADDRESS

W

A

F2h

A

P

002aac453

Fig 11. Idle mode

The Idle mode will be exited when its I²C-bus address is detected.

7.1.8 GPIO Write - Function ID F4h

The state of the pins defined as GPIO may be changed using the Port Write function.

S

SLAVE ADDRESS

W

A

F4h

A

DATA

A

P

002aac454

Fig 12. GPIO Write

The data byte following the F4h command will determine the state of SS3, SS2, SS1, and

SS0, if they are configured as GPIO. The Port Enable function will define if these pins are

used as SPI Slave Selects or if they are GPIO.

Table 6.

Bit

GPIO Write (F0h) bit allocation

7

X

6

X

5

X

4

X

3

SS3

0

2

SS2

0

1

SS1

0

SS0

0

Symbol

Reset

SC18IS602B

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I²C-bus to SPI bridge

7.1.9 GPIO Read - Function ID F5h

The state of the pins defined as GPIO may be read into the SC18IS602B data buffer using

the GPIO Read function.

S

SLAVE ADDRESS

W

A

F5h

A

DATA

A

P

002aac455

Fig 13. GPIO Read

Note that this function does not return the value of the GPIO. To receive the GPIO

contents, a one-byte Read Buffer command would be required. The value of the Read

Buffer command will return the following byte.

Table 7.

GPIO Read (F5h) bit allocation

7

6

5

4

3

2

1

0

X

SS3

SS2

SS1

SS0

Data for pins not defined as GPIO are undefined.

A GPIO Read is always performed to update the GPIO data in the buffer. The buffer is

undefined after the GPIO data is read back from the buffer. Therefore, reading data from

the GPIO always requires a two-message sequence (GPIO Read, followed by Read

Buffer).

7.1.10 GPIO Enable - Function ID F6h

At reset, the Slave Select pins (SS0, SS1, SS2 and SS3) are configured to be used as

slave select outputs. If these pins are not required for the SPI functions, they can be used

as GPIO after they are enabled as GPIO. Any combination of pins may be configured to

function as GPIO or Slave Selects.

After the GPIO Enable function is sent, the ports defined as GPIO will be configured as

quasi-bidirectional.

S

SLAVE ADDRESS

W

A

F6h

A

DATA

A

P

002aac456

Fig 14. GPIO Enable

The data byte following the F6h command byte will determine which pins can be used as

GPIO. A logic 1 will enable the pin as a GPIO, while a logic 0 will disable GPIO control.

Table 8.

GPIO Enable (F6h) bit allocation

7

6

5

4

3

2

1

0

X

SS3

SS2

SS1

SS0

SC18IS602B

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I²C-bus to SPI bridge

7.1.11 GPIO Configuration - Function ID F7h

The pins defined as GPIO may be configured by software to one of four types on a

pin-by-pin basis. These are: quasi-bidirectional, push-pull, open-drain, and input-only.

Two bits select the output type for each port pin.

Table 9.

7

GPIO Configuration (F7h) bit allocation

6

5

4

3

2

1

0

SS3.1

SS3.0

SS2.1

SS2.0

SS1.1

SS1.0

SS0.1

SS0.0

Table 10. GPIO Configuration (F7h) bit description

Bit

7

Symbol

SS3.1

Description

SS3[1:0] = 00: quasi-bidirectional

SS3[1:0] = 01: push-pull

6

SS3.0

SS3[1:0] = 10: input-only (high-impedance)

SS3[1:0] = 11: open-drain

5

4

SS2.1

SS2.0

SS2[1:0] = 00: quasi-bidirectional

SS2[1:0] = 01: push-pull

SS2[1:0] = 10: input-only (high-impedance)

SS2[1:0] = 11: open-drain

3

2

SS1.1

SS1.0

SS1[1:0] = 00: quasi-bidirectional

SS1[1:0] = 01: push-pull

SS1[1:0] = 10: input-only (high-impedance)

SS1[1:0] = 11: open-drain

1

0

SS0.1

SS0.0

SS0[1:0] = 00: quasi-bidirectional

SS0[1:0] = 01: push-pull

SS0[1:0] = 10: input-only (high-impedance)

SS0[1:0] = 11: open-drain

The SSn pins defined as GPIO, for example SS0.0 and SS0.1, may be configured by

software to one of four types. These are: quasi-bidirectional, push-pull, open-drain, and

input-only. Two configuration bits in GPIO Configuration register for each pin select the

type for each pin. A pin has Schmitt-triggered input that also has a glitch suppression

circuit.

7.1.11.1 Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used both as an input and output without the need to

reconfigure the pin. This is possible because when the pin outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a large current. There are three pull-up

transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch

for the pin contains a logic 1. This very weak pull-up sources a very small current that will

pull the pin HIGH if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin

contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the

primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is

SC18IS602B

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SC18IS602B

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I²C-bus to SPI bridge

pulled LOW by an external device, the weak pull-up turns off, and only the very weak

pull-up remains on. In order to pull the pin LOW under these conditions, the external

device has to sink enough current to overpower the weak pull-up and pull the pin below its

input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up

LOW-to-HIGH transitions on a quasi-bidirectional pin when the port latch changes from a

logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks

quickly pulling the pin HIGH.

The quasi-bidirectional pin configuration is shown in Figure 15.

Although the SC18IS602B is a 3 V device, most of the pins are 5 V tolerant. If 5 V is

applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from

the pin to V_DDcausing extra power consumption. Therefore, applying 5 V to pins

configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression

circuit.

V

DD

2 SYSTEM

CLOCK

CYCLES

P

very

weak

strong

weak

GPIO pin

pin latch data

V

SS

input data

glitch rejection

002aac548

Fig 15. Quasi-bidirectional output configuration

7.1.11.2 Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down

transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a

pin configured in this manner must have an external pull-up, typically a resistor tied to

V

_DD. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open-drain pin configuration is shown in Figure 16.

An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.

SC18IS602B

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I²C-bus to SPI bridge

GPIO pin

pin latch data

V

SS

input data

glitch rejection

002aab883

Fig 16. Open-drain output configuration

7.1.11.3 Input-only configuration

The input-only pin configuration is shown in Figure 17. It is a Schmitt-triggered input that

also has a glitch suppression circuit.

input data

GPIO pin

glitch rejection

002aab884

Fig 17. Input-only configuration

7.1.11.4 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a pin output.

The push-pull pin configuration is shown in Figure 18.

A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit.

V

DD

P

N

strong

GPIO pin

pin latch data

V

SS

input data

glitch rejection

002aab885

Fig 18. Push-pull output configuration

SC18IS602B

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I²C-bus to SPI bridge

7.2 SPI interface

The SPI interface can support Mode 0 through Mode 3 of the SPI specification and can

operate up to 1.8 Mbit/s. The SPI interface uses at least four pins: SPICLK, MOSI, MISO,

and Slave Select (SSn).

SSn are the slave select pins. In a typical configuration, an SPI master selects one SPI

device as the current slave.

There are actually four SSn pins (SS0, SS1, SS2 and SS3) to allow the SC18IS602B to

communicate with multiple SPI devices.

The SC18IS602B generates the SPICLK (SPI clock) signal in order to send and receive

data. The SCLK, MOSI, and MISO are typically tied together between two or more SPI

devices. Data flows from the SC18IS602B (master) to slave on the MOSI pin (Pin 6) and

the data flows from slave to SC18IS602B (master) on the MISO pin (Pin 5).

8. I²C-bus to SPI communications example

The following example describes a typical sequence of events required to read the

contents of an SPI-based EEPROM. This example assumes that the SC18IS602B is

configured to respond to address 50h. A START condition is shown as ‘ST’, while a STOP

condition is ‘SP’. The data is presented in hexadecimal format.

1. The first message is used to configure the SPI port for mode and frequency.

ST,50,F0,02,SP

SPI frequency 115 kHz using Mode 0

2. An SPI EEPROM first requires that a Write Enable command be sent before data can

be written.

ST,50,04,06,SP

EEPROM write enable using SS2, assuming the Write Enable is

06h

3. Clear the interrupt. This is not required if using a polling method rather than interrupts.

ST,50,F1,SP

Clear interrupt

4. Write the 8 data bytes. The first byte (Function ID) tells the SC18IS602B which Slave

Select output to use. This example uses SS2 (shown as 04h). The first byte sent to

the EEPROM is normally 02h for the EEPROM write command. The next one or two

bytes represent the subaddress in the EEPROM. In this example, a two-byte

subaddress is used. Bytes 00 and 30 would cause the EEPROM to write to

subaddress 0030h. The next eight bytes are the eight data bytes that will be written to

subaddresses 0030h through 0037h.

ST,50,04,02,00,30,01,02,03,04,05,06,07,08,SP

Write 8 bytes using SS2

5. When an interrupt occurs, do a Clear Interrupt or wait until the SC18IS602B responds

to its I²C-bus address.

ST,50,F1,SP

Clear interrupt

SC18IS602B

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I²C-bus to SPI bridge

6. Read the 8 bytes from the EEPROM. Note that we are writing a command, even

though we are going to perform a read from the SPI port. The Function ID is again

04h, indicating that we are going to use SS2. The EEPROM requires that you send a

03h for a read, followed by the subaddress you would like to read. We are going to

read back the same data previously written, so this means that the subaddress should

be 0030h. We would like to read back 8 bytes so we can send eight bytes of FFh to

tell the SC18IS602B to send eight more bytes on MOSI. While it is sending these

eight data bytes, it is also reading the MISO pin and saving the data in the buffer.

ST,50,04,03,00,30,FF,FF,FF,FF,FF,FF,FF,FF,SP

Read 8 bytes using SS2

7. The interrupt can be cleared, if needed.

ST,50,F1,SP

Clear interrupt

8. Read back the data buffer. Note that we will actually need to read back 11 data bytes

since the first three bytes sent on the SPI port were the read code (03h) and the two

subaddress bytes.

ST,50,00,00,00,01,02,03,04,05,06,07,08,SP

Read the data buffer

You can see that on the I²C-bus the first four bytes do not contain the data from the

SPI bus. The first byte is the SC18IS602B address, followed by three dummy data

bytes. These dummy data bytes correspond to the three bytes sent to the EEPROM

before it actually places data on the bus (command 03h, subaddress 0030h).

9. Limiting values

Table 11. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1][2]

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

Max

+125

+150

+5.5

8

Unit

°C

bias ambient temperature

operating

−55

storage temperature

−65

°C

V_n

voltage on any other pin

referenced to V_SS

−0.5

V

I_OH(I/O)

I_OL(I/O)

I_{I/O(tot)(max)}

P_tot/pack

HIGH-level output current per input/output pin

LOW-level output current per input/output pin

maximum total I/O current

-

mA

W

20

120

1.5

[3]

total power dissipation per package

[1] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

[2] Parameters are valid over the operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[3] Based on package heat transfer, not device power consumption.

SC18IS602B

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Product data sheet

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SC18IS602B

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10. Static characteristics

Table 12. Static characteristics

V_DD= 2.4 V to 3.6 V; T_amb= −40 °C to +85 °C (industrial); unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

5.6

Max

Unit

mA

V

I_DD(oper)

I_DD(idle)

V_th(HL)

V_th(LH)

V_hys

operating supply current

Idle mode supply current

V_DD= 3.6 V; f = 7.3728 MHz

-

6.7

-

3.3

3.9

HIGH-LOW threshold voltage Schmitt trigger input

LOW-HIGH threshold voltage Schmitt trigger input

hysteresis voltage

0.22V_DD

0.4V_DD

0.6V_DD

0.2V_DD

-

0.7V_DD

-

V

V_OL

LOW-level output voltage

all pins

I_OL= 20 mA

-

0.6

0.3

0.2

1.0

0.5

0.3

V

I_OL= 10 mA

I_OL= 3.2 mA

V_OH

HIGH-level output voltage

all pins

I_OH= −8 mA;

push-pull mode

V_DD− 1

-

V

I_OH= −3.2 mA;

V_DD− 0.7 V_DD− 0.4

V_DD− 0.3 V_DD− 0.2

push-pull mode

I_OH= −20 μA;

quasi-bidirectional mode

[2]

[3]

C_ig

I_IL

input capacitance at gate

LOW-level input current

input leakage current

-

15

pF

μA

logical 0; V_I= 0.4 V

-

−80

±10

−450

[4]

I_LI

all ports; V_I= V_ILor V_IH

-

[5][6]

I_THL

HIGH-LOW transition current all ports; logical 1-to-0;

V_I= 2.0 V at V_DD= 3.6 V

−30

R_{RESET_N(int)}internal pull-up resistance on

pin RESET

10

-

30

kΩ

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] Pin capacitance is characterized but not tested.

[3] Measured with pins in quasi-bidirectional mode.

[4] Measured with pins in high-impedance mode.

[5] Pins in quasi-bidirectional mode with weak pull-up (applies to all pins with pull-ups).

[6] Pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is

highest when V_Iis approximately 2 V.

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I²C-bus to SPI bridge

11. Dynamic characteristics

Table 13. Dynamic characteristics

V_DD= 2.4 V to 3.6 V; T_amb= −40 °C to +85 °C (industrial); unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

f_osc(RC)

internal RC oscillator

frequency

nominal f = 7.3728 MHz;

trimmed to ±1 % at T_amb= 25 °C

7.189

-

7.557

MHz

Glitch filter

t_gr

glitch rejection time

RESET pin

-

50

-

ns

any pin except RESET

RESET pin

125

-

t_sa

signal acceptance time

15

-

any pin except RESET

50

SPI master interface

f_SPI

SPI operating frequency

1.843 MHz

-

1.843

MHz

ns

T_SPICYC

t_SPICLKH

t_SPICLKL

t_SPIDSU

t_SPIDH

SPI cycle time

543

271

100

-

SPICLK HIGH time

SPICLK LOW time

SPI data set-up time

SPI data hold time

-

ns

-

ns

-

ns

-

ns

t_SPIDV

SPI enable to output data

valid time

160

ns

t_SPIOH

t_SPIR

SPI output data hold time

SPI rise time

0

-

ns

SPI outputs (SPICLK, MOSI, MISO)

SPI inputs (SPICLK, MOSI, MISO, SSn)

SPI outputs (SPICLK, MOSI, MISO)

SPI inputs (SPICLK, MOSI, MISO, SSn)

100

2000

100

2000

-

t_SPIF

SPI fall time

-

T

SPICYC

t

SPIR

SPIF

t

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

t

SPIR

SPIF

t

SPICLKH

SPICLKL

SPICLK

(CPOL = 1)

(output)

t

SPIDSU

SPIDH

MISO

(input)

MSB/LSB in

LSB/MSB in

t

SPIR

SPIDV

SPIOH

SPIDV

t

SPIF

MOSI

(output)

master MSB/LSB out

master LSB/MSB out

002aac457

Fig 19. SPI master timing (CPHA = 0)

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T

SPICYC

t

SPIR

SPIF

t

SPICLKH

SPICLKL

SPICLK

(CPOL = 0)

(output)

t

SPIR

SPIF

t

SPICLKL

SPICLKH

SPICLK

(CPOL = 1)

(output)

t

SPIDSU

SPIDH

MISO

(input)

MSB/LSB in

LSB/MSB in

t

SPIDV

SPIOH

SPIDV

t

SPIF

SPIR

MOSI

(output)

master MSB/LSB out

master LSB/MSB out

002aac458

Fig 20. SPI master timing (CPHA = 1)

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I²C-bus to SPI bridge

12. Package outline

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 21. Package outline SOT403-1 (TSSOP16)

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I²C-bus to SPI bridge

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

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13.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 22) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 14 and 15

Table 14. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 15. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 22.

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I²C-bus to SPI bridge

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 22. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Abbreviations

Table 16. Abbreviations

Acronym

CDM

CPU

Description

Charged Device Model

Central Processing Unit

Electrically Erasable Programmable Read-Only Memory

ElectroStatic Discharge

General Purpose Input/Output

Human Body Model

EEPROM

ESD

GPIO

HBM

I/O

Input/Output

I²C-bus

Inter-Integrated Circuit bus

Least Significant Bit

LSB

MM

Machine Model

MSB

Most Significant Bit

SPI

Serial Peripheral Interface

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I²C-bus to SPI bridge

15. Revision history

Table 17. Revision history

Document ID

SC18IS602B v.5

Modifications:

Release date

20100803

Data sheet status

Change notice

Supersedes

Product data sheet

SC18IS602_602B_603 v.4

• Type number SC18IS603IPW (basic type SC18IS603) removed from data sheet.

• Type number SC18IS602IPW (basic type SC18IS602) removed from data sheet.

• Deleted (old) Section 7.2, “External clock input (SC18IS603)”

• Table 11 “Limiting values”: deleted (old) table note [1]. Refer to Section 16.3

“Disclaimers”, sub-section “Limiting values”.

• Table 12 “Static characteristics”:

–

I

_DD(oper): removed characteristics for condition f = 12 MHz

I

_DD(oper): removed characteristics for condition f = 18 MHz

I_DD(idle): removed characteristics for condition f = 12 MHz

_DD(idle): removed characteristics for condition f = 18 MHz

I

• Table 13 “Dynamic characteristics”:

–

deleted sub-section “External clock input”

deleted “Variable clock” Min and Max columns

f

_SPI: changed Condition from “4.5 MHz” to “1.843 MHz”

f_SPIMax. value changed from “4.5 MHz” to “1.843 MHz”

T

_SPICYC: changed Condition from “4.5 MHz” to 1.843 MHz”

_SPICYCMin value changed from “222 ns” to “543 ns”

T

t_SPICLKH: changed Min value from “111 ns” to “271 ns”

_SPICLKL: changed Min value from “111 ns” to “271 ns”

t_SPIDV: removed characteristics for condition “4.5 MHz”

_SPIDV: removed condition “3.0 MHz”

t

• Figure 19 “SPI master timing (CPHA = 0)” modified: changed from “T_CLCL” to “T_SPICYC

• Figure 20 “SPI master timing (CPHA = 1)” modified: changed from “T_CLCL” to “T_SPICYC

• Deleted (old) Fig. 22. “External clock timing”

”

SC18IS602_602B_603 v.4

SC18IS602_603 v.3

SC18IS602_603 v.2

SC18IS602_603 v.1

20080311

20070813

20061213

20060926

Product data sheet

-

SC18IS602_603 v.3

SC18IS602_603 v.2

SC18IS602_603 v.1

-

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16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

16.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

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Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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NXP Semiconductors

I²C-bus to SPI bridge

18. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

Functional description . . . . . . . . . . . . . . . . . . . 4

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . . 4

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Write to data buffer . . . . . . . . . . . . . . . . . . . . . . 5

SPI read and write - Function ID 01h to 0Fh . . 5

Read from buffer. . . . . . . . . . . . . . . . . . . . . . . . 6

Configure SPI Interface - Function ID F0h . . . . 7

Clear Interrupt - Function ID F1h . . . . . . . . . . . 8

Idle mode - Function ID F2h. . . . . . . . . . . . . . . 8

GPIO Write - Function ID F4h. . . . . . . . . . . . . . 8

GPIO Read - Function ID F5h . . . . . . . . . . . . . 9

GPIO Enable - Function ID F6h . . . . . . . . . . . . 9

GPIO Configuration - Function ID F7h . . . . . . 10

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.6

7.1.7

7.1.8

7.1.9

7.1.10

7.1.11

7.1.11.1 Quasi-bidirectional output configuration . . . . . 10

7.1.11.2 Open-drain output configuration. . . . . . . . . . . 11

7.1.11.3 Input-only configuration . . . . . . . . . . . . . . . . . 12

7.1.11.4 Push-pull output configuration . . . . . . . . . . . . 12

7.2

SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 13

I²C-bus to SPI communications example . . . 13

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

Static characteristics. . . . . . . . . . . . . . . . . . . . 15

Dynamic characteristics . . . . . . . . . . . . . . . . . 16

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18

8

9

10

11

12

13

Soldering of SMD packages . . . . . . . . . . . . . . 19

Introduction to soldering . . . . . . . . . . . . . . . . . 19

Wave and reflow soldering . . . . . . . . . . . . . . . 19

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 19

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 20

13.1

13.2

13.3

13.4

14

15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 23

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 24

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 August 2010

Document identifier: SC18IS602B


型号：	935286182128
厂家：	NXP
描述：	I2C BUS CONTROLLER, PDSO16 时钟光电二极管外围集成电路
文件：	总25页 (文件大小：207K)
中文：	中文翻译
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935286182128 [NXP]

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