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INTEGRATED CIRCUITS

DATA SHEET

UDA1330ATS

Low-cost stereo filter DAC

Product specification

2001 Feb 02

Supersedes data of 2000 April 18

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

FEATURES

General

• Low power consumption

• Power supply voltage from 2.7 to 5.5 V

• Selectable control via L3 microcontroller interface or via

static pin control

• System clock frequencies of 256f_s, 384f_sand 512f_s

selectable via L3 interface or 256f_sand 384f_svia static

pin control

APPLICATIONS

• Supports sampling frequencies (f_s) from 8 to 55 kHz

• PC audio applications

• Car radio applications.

• Integrated digital filter plus non inverting

Digital-to-Analog Converter (DAC)

• No analog post filtering required for DAC

• Slave mode only applications

• Easy application

GENERAL DESCRIPTION

The UDA1330ATS is a single-chip stereo DAC employing

bitstream conversion techniques.

• Small package size (SSOP16)

• TTL tolerant input pads

The UDA1330ATS supports the I²S-bus data format with

word lengths of up to 20 bits, the MSB-justified data format

with word lengths of up to 20 bits and the LSB-justified

serial data format with word lengths of 16, 18 and 20 bits.

• Pin and function compatible with the UDA1320ATS.

Multiple format input interface

The UDA1330ATS can be used in two modes: L3 mode or

the static pin mode.

• L3 mode: I²S-bus, MSB-justified or LSB-justified

16, 18 and 20 bits format compatible

• Static pin mode: I²S-bus and LSB-justified

In the L3 mode, all digital sound processing features must

be controlled via the L3 interface, including the selection of

the system clock setting.

16, 18 and 20 bits format compatible

• 1f_sinput format data rate.

In the two static modes, the UDA1330ATS can be

operated in the 256f_sand 384f_ssystem clock mode.

Muting, de-emphasis for 44.1 kHz and four digital input

formats (I²S-bus or LSB-justified 16, 18, and 20 bits) can

be selected via static pins. The L3 interface cannot be

used in this application mode, so volume control is not

available in this mode.

DAC digital sound processing

• Digital logarithmic volume control in L3 mode

• Digital de-emphasis for 32, 44.1 and 48 kHz sampling

frequencies in L3 mode or 44.1 kHz sampling frequency

in static pin mode

• Soft mute control both in static pin mode and L3 mode.

Advanced audio configuration

• Stereo line output (volume control in L3 mode)

• High linearity, wide dynamic range and low distortion.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

plastic shrink small outline package; 16 leads; body width 4.4 mm

VERSION

UDA1330ATS

2001 Feb 02

SSOP16

SOT369-1

2

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

V_DDA

DAC analog supply voltage

digital supply voltage

2.7

5.0

5.5

V

V_DDD

2.7

5.0

5.5

V

I_DDA

DAC analog supply current

V_DDA= 5.0 V

operating

power-down

V_DDA= 3.3 V

operating

−

9.5

−

mA

400

μA

−

7.0

250

5.5

3.0

−

mA

μA

power-down

V_DDD= 5.0 V

V_DDD= 3.3 V

−

I_DDD

digital supply current

ambient temperature

−

mA

°C

−

T_amb

−40

+85

Digital-to-analog converter (V_DDA= V_DDD= 5.0 V)

V_o(rms)output voltage (RMS value)

note 1

−

1.45

−90

−40

100

−

V

(THD + N)/S total harmonic distortion-plus-noise to at 0 dB

signal ratio

−85

−35

95

−

dB

at −60 dB; A-weighted

S/N

signal-to-noise ratio

channel separation

code = 0; A-weighted

α_cs

Digital-to-analog converter (V_DDA= V_DDD= 3.3 V)

V_o(rms)output voltage (RMS value)

note 1

−

1.0

−

V

(THD + N)/S total harmonic distortion-plus-noise to at 0 dB

signal ratio

−85

−38

100

dB

at −60 dB; A-weighted

S/N

signal-to-noise ratio

channel separation

code = 0; A-weighted

α_cs

Power dissipation

P

power dissipation

playback mode

V_DDA= V_DDD= 5.0 V

V_DDA= V_DDD= 3.3 V

−

75

33

−

mW

Note

1. The output voltage scales linearly with the power supply voltage.

2001 Feb 02

3

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

BLOCK DIAGRAM

V

handbook, full pagewidth

SSD

5

DDD

4

7

11

10

9

APPSEL

1

2

3

BCK

WS

APPL0

APPL1

APPL2

APPL3

CONTROL

INTERFACE

DIGITAL INTERFACE

DATAI

8

VOLUME/MUTE/DE-EMPHASIS

INTERPOLATION FILTER

NOISE SHAPER

UDA1330ATS

6

SYSCLK

16

DAC

14

VOUTL

VOUTR

13

15

12

MGL401

V

ref(DAC)

DDA

SSA

Fig.1 Block diagram.

PINNING

SYMBOL

DESCRIPTION

BCK

1

2

3

4

5

6

bit clock input

word select input

data input

WS

handbook, halfpage

BCK

WS

1

2

3

4

5

6

7

8

16 VOUTR

DATAI

V_DDD

V_SSD

digital supply voltage

digital ground

15

V

SSA

DATAI

14 VOUTL

SYSCLK

system clock input: 256f_s, 384f_s

and 512f_s

V

13

12

DDD

DDA

UDA1330ATS

V

SSD

ref(DAC)

APPSEL

APPL3

APPL2

APPL1

APPL0

V_ref(DAC)

V_DDA

7

application mode select input

application input 3

SYSCLK

APPSEL

APPL3

11 APPL0

10 APPL1

8

9

application input 2

10

11

12

13

14

15

16

application input 1

9

APPL2

application input 0

MGL402

DAC reference voltage

analog supply voltage for DAC

left channel output

VOUTL

V_SSA

analog ground

Fig.2 Pin configuration.

VOUTR

right channel output

2001 Feb 02

4

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

FUNCTIONAL DESCRIPTION

System clock

In the L3 mode, pin APPL0 must be set to LOW. It should

be noted that when the L3 mode is used, an initialization

must be performed when the IC is powered-up.

The UDA1330ATS operates in slave mode only.

Therefore, in all applications the system devices must

provide the system clock. The system frequency (f_sys) is

selectable and depends on the application mode. The

options are: 256f_s, 384f_sand 512f_sfor the L3 mode and

256f_sor 384f_sfor the static pin mode. The system clock

must be locked in frequency to the digital interface input

signals.

Multiple format input interface

DATA FORMATS

The digital interface of the UDA1330ATS supports multiple

format inputs (see Fig.3).

Left and right data-channel words are time multiplexed.

The WS signal must have a 50% duty factor for all

LSB-justified formats.

The UDA1330ATS supports sampling frequencies from

8 to 55 kHz.

The BCK clock can be up to 64f_s, or in other words the

BCK frequency is 64 times the Word Select (WS)

Application modes

The application mode can be set with the three-level

pin APPSEL (see Table 1):

frequency or less: f_BCK≤ 64 × f_WS.

Important: the WS edge MUST fall on the negative edge

of the BCK at all times for proper operation of the digital

interface.

• L3 mode

• Static pin mode with f_sys= 384f_s

• Static pin mode with f_sys= 256f_s.

The UDA1330ATS also accepts double speed data for

double speed data monitoring purposes

Table 1 Selecting application mode and system clock

frequency via pin APPSEL

L3 MODE

VOLTAGE ON

PIN APPSEL

This mode supports the following input formats:

MODE

L3 mode

f_sys

• I²S-bus format with data word length of up to 20 bits

• MSB-justified format with data word length up to 20 bits

V_SSD

256f_s, 384f_sor 512f_s

0.5V_DDD

V_DDD

384f_s

256f_s

• LSB-justified format with data word length of

16, 18 or 20 bits.

static pin mode

STATIC PIN MODE

The function of an application input pin (active HIGH)

depends on the application mode (see Table 2).

This mode supports the following input formats:

• I²S-bus format with data word length of up to 20 bits

Table 2 Functions of application input pins

• LSB-justified format with data word length of

FUNCTION

16, 18 or 20 bits.

L3 MODE

STATIC PIN MODE

These four formats are selectable via the static pin codes

SF0 and SF1 (see Table 3).

APPL0

APPL1

APPL2

APPL3

TEST

MUTE

DEEM

SF0

L3CLOCK

L3MODE

L3DATA

Table 3 Input format selection using SF0 and SF1

FORMAT

SF0

0

SF1

0

SF1

I²S-bus

LSB-justified 16 bits

LSB-justified 18 bits

LSB-justified 20 bits

0

1

For example, in the static pin mode the output signal can

be soft muted by setting pin APPL0 to HIGH.

De-emphasis can be switched on for 44.1 kHz by setting

pin APPL1 to HIGH; setting pin APPL1 to LOW will disable

de-emphasis.

1

0

1

2001 Feb 02

5

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

Interpolation filter (DAC)

Filter stream DAC

The digital filter interpolates from 1f_sto 128f_sby cascading

a recursive filter and an FIR filter (see Table 4).

The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an

analog output voltage. The filter coefficients are

Table 4 Interpolation filter characteristics

implemented as current sources and are summed at virtual

ground of the output operational amplifier. In this way very

high signal-to-noise performance and low clock jitter

sensitivity is achieved. A post-filter is not needed due to

the inherent filter function of the DAC. On-board amplifiers

convert the FSDAC output current to an output voltage

signal capable of driving a line output.

ITEM

CONDITION

0 to 0.45f_s

>0.55f_s

VALUE (dB)

±0.1

Pass-band ripple

Stop band

−50

Dynamic range

0 to 0.45f_s

108

The output voltage of the FSDAC scales linearly with the

power supply voltage.

Noise shaper

The 3rd-order noise shaper operates at 128f_s. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise shaping technique enables high

signal-to-noise ratios to be achieved. The noise shaper

output is converted into an analog signal using a Filter

Stream DAC (FSDAC).

Pin compatibility

In the L3 mode the UDA1330ATS can be used on boards

that are designed for the UDA1320ATS.

Remark: It should be noted that the UDA1330ATS is

designed for 5 V operation while the UDA1320ATS is

designed for 3 V operation. This means that the

UDA1330ATS can be used with the UDA1320ATS supply

voltage range, but the UDA1320ATS can not be used with

the 5 V supply voltage.

2001 Feb 02

6

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

L3 INTERFACE

The fundamental timing of data transfers (see Fig.5) is

essentially the same as the address mode. The maximum

input clock frequency and data rate is 64f_s.

The following system and digital sound processing

features can be controlled in the L3 mode of the

UDA1330ATS:

Data transfer can only be in one direction, consisting of

input to the UDA1330ATS to program sound processing

and other functional features. All data transfers are by 8-bit

bytes. Data will be stored in the UDA1330ATS after

reception of a complete byte.

• System clock frequency

• Data input format

• De-emphasis for 32, 44.1 and 48 kHz

• Volume

A multibyte transfer is illustrated in Fig.6.

• Soft mute.

Registers

The exchange of data and control information between the

microcontroller and the UDA1330ATS is accomplished

through a serial interface comprising the following signals:

The sound processing and other feature values are stored

in independent registers. The first selection of the registers

is achieved by the choice of data type that is transferred.

This is performed in the address mode using bit 1 and bit 0

(see Table 5).

• L3DATA

• L3MODE

• L3CLOCK.

Table 5 Selection of data transfer

Information transfer through the microcontroller bus is

organized in accordance with the L3 interface format, in

which two different modes of operation can be

BIT 1 BIT 0

TRANSFER

0

1

0

1

0

data (volume, de-emphasis, mute)

not used

distinguished: address mode and data transfer mode.

Address mode

status (system clock frequency,

data input format)

The address mode (see Fig.4) is required to select a

device communicating via the L3 interface and to define

the destination registers for the data transfer mode.

1

not used

The second selection is performed by the 2 MSBs of the

data byte (bit 7 and bit 6). The other bits in the data byte

(bit 5 to bit 0) represent the value that is placed in the

selected registers.

Data bits 7 to 2 represent a 6-bit device address where

bit 7 is the MSB. The address of the UDA1330ATS is

000101 (bit 7 to bit 2). If the UDA1330ATS receives a

different address, it will deselect its microcontroller

interface logic.

The ‘status’ settings are given in Table 6 and the ‘data’

settings are given in Table 7.

Data transfer mode

The selected address remains active during subsequent

data transfers until the UDA1330ATS receives a new

address command.

2001 Feb 02

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NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

handbook, full pagewidth

L3MODE

t

su(L3)A

h(L3)A

t

CLK(L3)L

t

CLK(L3)H

su(L3)A

h(L3)A

L3CLOCK

T

cy(CLK)(L3)

t

h(L3)DA

su(L3)DA

BIT 0

BIT 7

L3DATA

MGL723

Fig.4 Timing address mode.

t

stp(L3)

handbook, full pagewidth

L3MODE

t

CLK(L3)L

t

T

h(L3)D

cy(CLK)L3

t

CLK(L3)H

su(L3)D

L3CLOCK

t

h(L3)DA

su(L3)DA

L3DATA

WRITE

BIT 0

BIT 7

MGL882

Fig.5 Timing data transfer mode.

9

2001 Feb 02

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

t

stp(L3)

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

MGL725

address

data byte #1

data byte #2

address

Fig.6 Multibyte data transfer.

Programming the features

When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format

can be controlled.

Table 6 Data transfer of type ‘status’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

REGISTER SELECTED

0

SC1

SC0

IF2

IF1

IF0

0

SC = system clock frequency (2 bits); see Table 8

IF = data input format (3 bits); see Table 9

not used

1

0

When the data transfer of type ‘data’ is selected, the features for volume, de-emphasis and mute can be controlled.

Table 7 Data transfer of type ‘data’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

REGISTER SELECTED

0

1

0

1

0

VC5

0

VC4

0

VC3

0

VC2

0

VC1

0

VC0 VC = volume control (6 bits); see Table 11

0

not used

0

DE1

DE0

MT

0

DE = de-emphasis (2 bits); see Table 10

MT = mute (1 bit); see Table 12

default setting

1

0

1

2001 Feb 02

10

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

SYSTEM CLOCK FREQUENCY

VOLUME CONTROL

The system clock frequency is a 2-bit value to select the

external clock frequency.

The volume control is a 6-bit value to program the volume

attenuation from 0 to −60 dB and −∞ dB in steps of 1 dB.

Table 8 System clock settings

Table 11 Volume settings

SC1 SC0

FUNCTION

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

0

1

0

1

0

1

512f_s

0

:

0

:

0

:

0

:

0

1

:

0

1

0

1

:

0

384f_s

256f_s

−1

−2

:

not used

DATA FORMAT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

−51

−52

−54

The data format is a 3-bit value to select the used data

format.

Table 9 Data input format settings

IF2

IF1

IF0

FORMAT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I²S-bus

LSB-justified 16 bits

LSB-justified 18 bits

LSB-justified 20 bits

MSB-justified

not used

−57

−60

−∞

not used

MUTE

DE-EMPHASIS

Mute is a 1-bit value to enable the digital mute.

De-emphasis is a 2-bit value to enable the digital

de-emphasis filter.

Table 12 Mute setting

MT

0

FUNCTION

Table 10 De-emphasis settings

no muting

muting

DE1 DE0

FUNCTION

no de-emphasis

1

0

1

0

1

0

1

de-emphasis, 32 kHz

de-emphasis, 44.1 kHz

de-emphasis, 48 kHz

2001 Feb 02

11

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL

PARAMETER

digital supply voltage

CONDITIONS

MIN.

MAX.

6.0

UNIT

V_DDD

V_DDA

T_xtal(max)

T_stg

note 1

−

V

analog supply voltage

6.0

maximum crystal temperature

storage temperature

150

°C

V

−65

+125

+85

T_amb

V_es

ambient temperature

−40

electrostatic handling voltage

note 2

note 3

note 4

−3000

−250

+3000

+250

V

I_sc(DAC)

short-circuit current of DAC

output short-circuited to V_SSA(DAC)

output short-circuited to V_DDA(DAC)

−

450

300

mA

Notes

1. All supply connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 μH series inductor.

4. Short-circuit test at T_amb= 0 °C and V_DDA= 3 V. DAC operation after short-circuiting cannot be warranted.

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling MOS devices.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

in free air

VALUE

UNIT

R_th(j-a)

thermal resistance from junction to ambient

190

K/W

QUALITY SPECIFICATION

In accordance with “SNW-FQ-611-E”.

2001 Feb 02

12

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

DC CHARACTERISTICS

V_DDD= V_DDA= 5.0 V; T_amb= 25 °C; R_L= 5 kΩ; all voltages referenced to ground (pins V_SSAand V_SSD); unless

otherwise specified.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_DDA

V_DDD

I_DDA

DAC analog supply voltage note 1

digital supply voltage note 1

2.7

5.0

5.5

V

5.5

DAC analog supply current V_DDA= 5.0 V

operating

power-down

V_DDA= 3.3 V

operating

−

9.5

−

mA

400

μA

−

7.0

250

5.5

3.0

−

mA

μA

power-down

I_DDD

digital supply current

V_DDD= 5.0 V

V_DDD= 3.3 V

mA

Power dissipation

power dissipation

P

playback mode

V_DDA= V_DDD= 5.0 V

V_DDA= V_DDD= 3.3 V

−

75

33

−

mW

Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3 (note 2)

V_IH

HIGH-level input voltage

V_DDD= 5.0 V

_DDD= 3.3 V

2.2

1.45

−

V

−

V

V_IL

LOW-level input voltage

V_DDD= 5.0 V

V_DDD= 3.3 V

0.8

0.5

1

V

−

V

⎪I_LI⎪

input leakage current

input capacitance

−

μA

pF

C_i

−

10

Three-level input: APPSEL

V_IH

V_IM

HIGH-level input voltage

0.9V_DDD

0.4V_DDD

−

V

_DDD+ 0.5 V

MIDDLE-level input

voltage

0.6V_DDD

V

V_IL

LOW-level input voltage

−0.5

−

+0.1V_DDD

V

2001 Feb 02

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NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

SYMBOL

DAC

V_ref(DAC)

I_o(max)

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

reference voltage

with respect to V_SSA

0.45V_DDA0.5V_DDA

0.55V_DDA

V

maximum output current

(THD + N)/S < 0.1%;

−

0.36

−

mA

R_L= 5 kΩ

R_o

R_L

C_L

output resistance

load resistance

load capacitance

−

3

−

0.15

2.0

−

Ω

−

kΩ

pF

note 3

50

Notes

1. All supply connections must be made to the same external power supply unit.

2. The digital input pads are TTL compatible at 5 V, but the pads are not 5 V tolerant in the voltage range between

2.7 and 4.5 V.

3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent

oscillations in the output operational amplifier.

AC CHARACTERISTICS

f_i= 1 kHz; T_amb= 25 °C; R_L= 5 kΩ; all voltages referenced to ground (pins V_SSAand V_SSD); unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

Digital-to-analog converter (V_DDA= V_DDD= 5.0 V)

V_o(rms)

output voltage (RMS value)

unbalance between channels

1.45

−

V

ΔV_o

0.1

dB

(THD + N)/S total harmonic distortion-plus-noise to

signal ratio

at 0 dB

−90

−85

−35

95

at −60 dB; A-weighted −40

S/N

signal-to-noise ratio

channel separation

code = 0; A-weighted

100

α_cs

−

Digital-to-analog converter (V_DDA= V_DDD= 3.3 V)

V_o(rms)

output voltage (RMS value)

unbalance between channels

1.0

0.1

−85

−

V

ΔV_o

dB

(THD + N)/S total harmonic distortion-plus-noise to

signal ratio

at 0 dB

at −60 dB; A-weighted −38

S/N

signal-to-noise ratio

code = 0; A-weighted

100

60

α_cs

channel separation

PSRR

power supply ripple rejection

f_ripple= 1 kHz;

V

_ripple= 100 mV (p-p)

2001 Feb 02

14

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

TIMING

V_DDD= V_DDA= 4.5 to 5.5 V; T_amb= −40 to +85 °C; R_L= 5 kΩ; all voltages referenced to ground (pins V_SSAand V_SSD);

unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

System clock (see Fig.7)

T_sys

system clock cycle time

f_sys= 256f_s

71

88

488

ns

f_sys= 384f_s

47

59

44

−

325

244

ns

f_sys= 512f_s

36

t_CWL

LOW-level system clock pulse width

HIGH-level system clock pulse width

f_sys< 19.2 MHz

f_sys≥ 19.2 MHz

f_sys< 19.2 MHz

f_sys≥ 19.2 MHz

0.3T_sys

0.4T_sys

0.3T_sys

0.4T_sys

0.7T_sysns

0.6T_sysns

0.7T_sysns

0.6T_sysns

−

t_CWH

−

Digital interface (see Fig.8)

T_cy(BCK)

t_BCKH

t_BCKL

t_r

bit clock cycle time

300

100

−

ns

bit clock HIGH time

bit clock LOW time

rise time

−

20

−

t_f

fall time

−

t_su(DATAI)

t_h(DATAI)

t_su(WS)

t_h(WS)

data input set-up time

data input hold time

word select set-up time

word select hold time

20

0

−

20

10

−

Control interface L3 mode (see Figs 4 and 5)

T_cy(CLK)L3

t_CLK(L3)H

t_CLK(L3)L

t_su(L3)A

L3CLOCK cycle time

500

250

190

−

ns

L3CLOCK HIGH time

L3CLOCK LOW time

L3MODE set-up time for address mode

L3MODE hold time for address mode

t_h(L3)A

t_su(L3)D

L3MODE set-up time for data transfer

mode

t_h(L3)D

L3MODE hold time for data transfer

mode

190

30

−

ns

t_su(L3)DA

t_h(L3)DA

t_stp(L3)

L3DATA set-up time for data transfer and

address mode

L3DATA hold time for data transfer and

address mode

L3MODE stop time for data transfer

mode

190

2001 Feb 02

15

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

t

handbook, full pagewidth

CWH

MGR984

t

CWL

T

sys

Fig.7 System clock timing.

handbook, full pagewidth

WS

t

h(WS)

t

BCKH

t

su(WS)

t

f

r

BCK

t

su(DATAI)

t

BCKL

T

t

cy(BCK)

h(DATAI)

DATAI

MGL880

Fig.8 Serial interface timing.

16

2001 Feb 02

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

APPLICATION INFORMATION

handbook, full pagewidth

analog

digital

supply voltage

R2

1 Ω

R3

1 Ω

C1

100 μF

(16 V)

C5

C6

100 nF

(63 V)

100 nF

(63 V)

V

SSA

DDA

SSD

DDD

14

15

13

5

4

R1

SYSCLK

system

clock

6

47 Ω

C2

R4

VOUTL

VOUTR

V

left

output

100 Ω

BCK

WS

47 μF

(16 V)

1

2

3

7

R5

10 kΩ

DATAI

APPSEL

C3

R6

100 Ω

right

output

16

12

UDA1330ATS

47 μF

(16 V)

R7

10 kΩ

APPL0

APPL1

APPL2

APPL3

11

10

9

ref(DAC)

8

C7

100 nF

(63 V)

C4

47 μF

(16 V)

MGL403

Fig.9 Application diagram.

2001 Feb 02

17

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

PACKAGE OUTLINE

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

10^o

0^o

0.15

0.00

1.4

1.2

0.32

0.20

0.25

0.13

5.3

5.1

4.5

4.3

6.6

6.2

0.75

0.45

0.65

0.45

0.48

0.18

mm

1

1.5

0.65

0.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT369-1

MO-152

2001 Feb 02

18

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

SOLDERING

If wave soldering is used the following conditions must be

observed for optimal results:

Introduction to soldering surface mount packages

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population densities. In these situations reflow

soldering is often used.

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

Reflow soldering

The footprint must incorporate solder thieves at the

downstream end.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Wave soldering

Manual soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

To overcome these problems the double-wave soldering

method was specifically developed.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

2001 Feb 02

19

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

Suitability of surface mount IC packages for wave and reflow soldering methods

SOLDERING METHOD

PACKAGE

BGA, LFBGA, SQFP, TFBGA

WAVE

not suitable

REFLOW⁽¹⁾

suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS

PLCC⁽³⁾, SO, SOJ

not suitable⁽²⁾

suitable

LQFP, QFP, TQFP

not recommended⁽³⁾⁽⁴⁾suitable

not recommended⁽⁵⁾

suitable

SSOP, TSSOP, VSO

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2001 Feb 02

20

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

DATA SHEET STATUS

DOCUMENT

STATUS⁽¹⁾

PRODUCT

STATUS⁽²⁾

DEFINITION

Objective data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary data sheet

Product data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

Notes

1. Please consult the most recently issued document before initiating or completing a design.

2. The product status of device(s) described in this document may have changed since this document was published

and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

DISCLAIMERS

property or environmental damage. NXP Semiconductors

accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at

the customer’s own risk.

Limited warranty and liability ⎯ Information in this

document is believed to be accurate and reliable.

However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to

the accuracy or completeness of such information and

shall have no liability for the consequences of use of such

information.

Applications ⎯ Applications that are described herein for

any of these products are for illustrative purposes only.

NXP Semiconductors makes no representation or

warranty that such applications will be suitable for the

specified use without further testing or modification.

In no event shall NXP Semiconductors be liable for any

indirect, incidental, punitive, special or consequential

damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the

removal or replacement of any products or rework

charges) whether or not such damages are based on tort

(including negligence), warranty, breach of contract or any

other legal theory.

Customers are responsible for the design and operation of

their applications and products using NXP

Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or

customer product design. It is customer’s sole

responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the

customer’s applications and products planned, as well as

for the planned application and use of customer’s third

party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks

associated with their applications and products.

Notwithstanding any damages that customer might incur

for any reason whatsoever, NXP Semiconductors’

aggregate and cumulative liability towards customer for

the products described herein shall be limited in

accordance with the Terms and conditions of commercial

sale of NXP Semiconductors.

NXP Semiconductors does not accept any liability related

to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications

or products, or the application or use by customer’s third

party customer(s). Customer is responsible for doing all

necessary testing for the customer’s applications and

products using NXP Semiconductors products in order to

avoid a default of the applications and the products or of

the application or use by customer’s third party

customer(s). NXP does not accept any liability in this

respect.

Right to make changes ⎯ NXP Semiconductors

reserves the right to make changes to information

published in this document, including without limitation

specifications and product descriptions, at any time and

without notice. This document supersedes and replaces all

information supplied prior to the publication hereof.

Suitability for use ⎯ NXP Semiconductors products are

not designed, authorized or warranted to be suitable for

use in life support, life-critical or safety-critical systems or

equipment, nor in applications where failure or malfunction

of an NXP Semiconductors product can reasonably be

expected to result in personal injury, death or severe

2001 Feb 02

21

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

Limiting values ⎯ Stress above one or more limiting

values (as defined in the Absolute Maximum Ratings

System of IEC 60134) will cause permanent damage to

the device. Limiting values are stress ratings only and

(proper) operation of the device at these or any other

conditions above those given in the Recommended

operating conditions section (if present) or the

Characteristics sections of this document is not warranted.

Constant or repeated exposure to limiting values will

permanently and irreversibly affect the quality and

reliability of the device.

Quick reference data ⎯ The Quick reference data is an

extract of the product data given in the Limiting values and

Characteristics sections of this document, and as such is

not complete, exhaustive or legally binding.

Non-automotive qualified products ⎯ Unless this data

sheet expressly states that this specific NXP

Semiconductors product is automotive qualified, the

product is not suitable for automotive use. It is neither

qualified nor tested in accordance with automotive testing

or application requirements. NXP Semiconductors accepts

no liability for inclusion and/or use of non-automotive

qualified products in automotive equipment or

applications.

Terms and conditions of commercial sale ⎯ NXP

Semiconductors products are sold subject to the general

terms and conditions of commercial sale, as published at

http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an

individual agreement is concluded only the terms and

conditions of the respective agreement shall apply. NXP

Semiconductors hereby expressly objects to applying the

customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

In the event that customer uses the product for design-in

and use in automotive applications to automotive

specifications and standards, customer (a) shall use the

product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and

specifications, and (b) whenever customer uses the

product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at

customer’s own risk, and (c) customer fully indemnifies

NXP Semiconductors for any liability, damages or failed

product claims resulting from customer design and use of

the product for automotive applications beyond NXP

Semiconductors’ standard warranty and NXP

No offer to sell or license ⎯ Nothing in this document

may be interpreted or construed as an offer to sell products

that is open for acceptance or the grant, conveyance or

implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Semiconductors’ product specifications.

Export control ⎯ This document as well as the item(s)

described herein may be subject to export control

regulations. Export might require a prior authorization from

national authorities.

2001 Feb 02

22

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product

solutions that leverage its leading RF, Analog, Power Management,

Interface, Security and Digital Processing expertise

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal

definitions and disclaimers. No changes were made to the technical content, except for package outline

drawings which were updated to the latest version.

Contact information

For additional information please visit: http://www.nxp.com

For sales offices addresses send e-mail to: salesaddresses@nxp.com

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

753503/05/pp23

Date of release: 2001 Feb 02

Document order number: 9397 750 07939


型号：	935286237118
厂家：	NXP
描述：	SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 输入元件光电二极管转换器
文件：	总23页 (文件大小：165K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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