LPC2292FET144 [PHILIPS]
Microcontroller, 32-Bit, FLASH, ARM7 CPU, 30MHz, CMOS, PQFP144,;型号: | LPC2292FET144 |
厂家: | PHILIPS SEMICONDUCTORS |
描述: | Microcontroller, 32-Bit, FLASH, ARM7 CPU, 30MHz, CMOS, PQFP144, 时钟 微控制器 外围集成电路 |
文件: | 总48页 (文件大小:255K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LPC2292/LPC2294
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with
CAN, 10-bit ADC and external memory interface
Rev. 04 — 11 July 2006
Product data sheet
1. General description
The LPC2292/LPC2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU
with real-time emulation and embedded trace support, together with 256 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For critical code size
applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with
minimal performance penalty.
With their 144-pin package, low power consumption, various 32-bit timers, 8-channel
10-bit ADC, 2/4 (LPC2292/LPC2294) advanced CAN channels, PWM channels and up to
nine external interrupt pins these microcontrollers are particularly suitable for automotive
and industrial control applications as well as medical systems and fault-tolerant
maintenance buses. The number of available GPIOs ranges from 76 (with external
memory) through 112 (single-chip). With a wide range of additional serial communications
interfaces, they are also suited for communication gateways and protocol converters as
well as many other general-purpose applications.
2. Features
2.1 Key features
I 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.
I 16 kB on-chip static RAM and 256 kB on-chip flash program memory. 128-bit wide
interface/accelerator enables high-speed 60 MHz operation.
I In-System Programming/In-Application Programming (ISP/IAP) via on-chip bootloader
software. Single flash sector or full chip erase in 400 ms and programming of 256 B in
1 ms.
I EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software as well as high-speed real-time tracing of instruction
execution.
I Two/four (LPC2292/LPC2294) interconnected CAN interfaces with advanced
acceptance filters. Additional serial interfaces include two UARTs (16C550), Fast
I2C-bus (400 kbit/s) and two SPIs.
I Eight channel 10-bit ADC with conversion time as low as 2.44 µs.
I Two 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real-Time Clock (RTC) and watchdog.
I Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
I Configurable external memory interface with up to four banks, each up to 16 MB and
8/16/32-bit data width.
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
I Up to 112 general purpose I/O pins (5 V tolerant). Up to nine edge/level sensitive
external interrupt pins available.
I 60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 µs.
I On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
I Power saving modes include Idle and Power-down.
I Processor wake-up from Power-down mode via external interrupt.
I Individual enable/disable of peripheral functions for power optimization.
I Dual power supply:
N CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).
N I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC2292FBD144
LPC2292FBD144/00
LPC2292FET144
LQFP144
plastic low profile quad flat package;
144 leads; body 20 × 20 × 1.4 mm
SOT486-1
LQFP144
plastic low profile quad flat package;
144 leads; body 20 × 20 × 1.4 mm
SOT486-1
TFBGA144 plastic thin fine-pitch ball grid array package; SOT569-1
144 balls; body 12 × 12 × 0.8 mm
LPC2292FET144/00
LPC2294HBD144
LPC2294HBD144/00
TFBGA144 plastic thin fine-pitch ball grid array package; SOT569-1
144 balls; body 12 × 12 × 0.8 mm
LQFP144
LQFP144
plastic low profile quad flat package;
144 leads; body 20 × 20 × 1.4 mm
SOT486-1
SOT486-1
plastic low profile quad flat package;
144 leads; body 20 × 20 × 1.4 mm
3.1 Ordering options
Table 2.
Ordering options
Type number
LPC2292FBD144
Flash memory
RAM
CAN
Temperature range
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +125 °C
−40 °C to +125 °C
256 kB
16 kB
16 kB
16 kB
16 kB
16 kB
16 kB
2 channels
2 channels
2 channels
2 channels
4 channels
4 channels
LPC2292FBD144/00 256 kB
LPC2292FET144 256 kB
LPC2292FET144/00 256 kB
LPC2294HBD144 256 kB
LPC2294HBD144/00 256 kB
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
2 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
4. Block diagram
(1)
(1)
TMS
(1)
TDI
(1)
XTAL2
XTAL1 RST
(1)
TRST
TCK
TDO
TEST/DEBUG
INTERFACE
LPC2292/2294
SYSTEM
FUNCTIONS
PLL
ARM7TDMI-S
system
clock
VECTORED
INTERRUPT
CONTROLLER
AHB BRIDGE
ARM7 local bus
AMBA AHB
(Advanced High-performance Bus)
INTERNAL
SRAM
INTERNAL
FLASH
CONTROLLER
CONTROLLER
AHB
DECODER
(2)
16 kB
SRAM
128/256 kB
SRAM
CS3 to CS0
(2)
AHB TO VPB
BRIDGE
VPB
DIVIDER
A23 to A0
EXTERNAL MEMORY
CONTROLLER
(2)
BLS3 to BLS0
(2)
OE, WE
VPB (VLSI
(2)
D31 to D0
peripheral bus)
SCL
2
EXTERNAL
INTERRUPTS
I C-BUS SERIAL
INTERFACE
EINT3 to EINT0
SDA
SCK0, SCK1
4 × CAP0
4 × CAP1
4 × MAT0
4 × MAT1
CAPTURE/
COMPARE
TIMER 0/TIMER 1
SPI AND SSP
SERIAL INTERFACES
0 AND 1
MOSI0, MOSI1
MISO0, MISO1
SSEL0, SSEL1
TXD0, TXD1
RXD0, RXD1
AIN3 to AIN0
AIN7 to AIN4
A/D CONVERTER
UART0/UART1
DSR1, CTS1,
DCD1, RI1
P0[30:0]
P1[31:16], P1[1:0]
P2[31:0]
TD2, TD1
RD2, RD1
TD4, TD3
GENERAL
PURPOSE I/O
CAN
(3)
(3)
RD4, RD3
P3[31:0]
WATCHDOG
TIMER
PWM6 to PWM1
PWM0
SYSTEM
CONTROL
REAL-TIME CLOCK
002aaa752
(1) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(2) Pins shared with GPIO.
(3) Available in LPC2294 only.
Fig 1. Block diagram
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
3 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
5. Pinning information
5.1 Pinning
1
108
LPC2292FBD144
LPC2294HBD144
36
73
002aab361
Fig 2. LQFP144 pinning
ball A1
index area
LPC2292FET144
1
2 3 4 5 6 7 8 9 10 11 12 13
A
B
C
D
E
F
G
H
J
K
L
M
N
002aab362
Transparent top view
Fig 3. TFBGA144 pinning
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
4 of 48
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 3.
Ball allocation
Row Column
1
2
3
4
5
6
7
8
9
10
11
12
13
A
P2.22/
D22
VDDA(1V8) P1.28/
TDI
P2.21/
D21
P2.18/
D18
P2.14/
D14
P1.29/
TCK
P2.11/
D11
P2.10/
D10
P2.7/D7
VDD(3V3)
VDD(1V8)
P2.4/D4
B
VDD(3V3)
P1.27/
TDO
XTAL2
XTAL1
P0.23/
VSSA(PLL) P2.19/
D19
P2.15/
D15
P2.12/
D12
P0.20/
VDD(3V3)
P2.9/D9
P2.8/D8
P2.6/D6
P2.5/D5
VSS
P2.3/D3
P2.1/D1
P1.20/
VSS
MAT1.3/
SSEL1/
EINT3
C
D
E
P0.21/
PWM5/
CAP1.3
VSS
VSSA
RESET
P2.16/
D16
P2.13/
D13
P0.19/
P2.2/D2
VSS
VDD(3V3)
MAT1.2/
MOSI1/
CAP1.2
P0.24/
TD2
P1.19/
TRACEP RD2
KT3
P0.22/
CAP0.0/
MAT0.0
P2.20/
D20
P2.17/
D17
VSS
P0.18/
P1.30/
TMS
P0.17/
CAP1.3/
MISO1/
MAT1.3
TRACES CAP1.2/
YNC
SCK1/
MAT1.2
P2.25/
D25
P2.24/
D24
P2.23
VSS
P0.16/
P0.15/
RI1/
EINT2
P2.0/D0
P3.30/
BLS1
EINT0/
MAT0.2/
CAP0.2
F
P2.27/
D27/
BOOT1
P1.18/
TRACEP
KT2
VDDA(3V3) P2.26/
D26/
P3.31/
BLS0
P1.21/
PIPESTAT
0
VDD(3V3)
VSS
BOOT0
G
H
P2.29/
D29
P2.28/
D28
P2.30/
D30/AIN4 D31/AIN5
P2.31/
P0.14/
DCD1/
EINT1
P1.0/CS0 P3.0/A0
P1.1/OE
P3.1/A1
P0.25/
RD1
TD1
P0.27/
AIN0/
CAP0.1/
MAT0.1
P1.17/
TRACEP
KT1
P0.13/
DTR1/
MAT1.1
P1.22/
PIPESTAT
1
P3.2/A2
J
P0.28/
AIN1/
CAP0.2/
MAT0.2
VSS
P3.29/
BLS2/
AIN6
P3.28/
BLS3/
AIN7
P3.3/A3
P1.23/
PIPESTAT CTS1/
2
P0.11/
P0.12/
DSR1/
MAT1.0
CAP1.1
K
P3.27/WE P3.26/
CS1
VDD(3V3)
P3.22/
A22
P3.20/
A20
P0.1/
P3.14/
A14
P1.25/
EXTIN0
P3.11/
A11
VDD(3V3)
P0.10/
RTS1/
CAP1.0
VSS
P3.4/A4
RXD0/
PWM3/
EINT0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Ball allocation …continued
Table 3.
Row Column
1
2
3
4
5
6
7
8
9
10
11
12
13
L
P0.29/
AIN2/
CAP0.3/
MAT0.3
P0.30/
AIN3/
EINT3/
CAP0.0
P1.16/
TRACEP TXD0/
KT0
P0.0/
P3.19/
A19
P0.2/
SCL/
CAP0.0
P3.15/
A15
P0.4/
SCK0/
CAP0.1
P3.12/
A12
VSS
P1.24/
TRACEC TXD1/
LK
P0.8/
P0.9/
RXD1/
PWM6/
EINT3
PWM1
PWM4
M
N
P3.25/
CS2
P3.24/
CS3
VDD(3V3)
P1.31/
TRST
P3.18/
A18
VDD(3V3)
P3.16/
A16
P0.3/
SDA/
MAT0.0/
EINT1
P3.13/
A13
P3.9/A9
P0.7/
P3.7/A7
P3.5/A5
P3.6/A6
SSEL0/
PWM2/
EINT2
VDD(1V8)
VSS
P3.23/
A23/
XCLK
P3.21/
A21
P3.17/
A17
P1.26/
RTCK
VSS
VDD(3V3)
P0.5/
MISO0/
MAT0.1
P3.10/
A10
P0.6/
MOSI0/
CAP0.2
P3.8/A8
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
5.2 Pin description
Table 4.
Symbol
Pin description
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P0.0 to P0.31
I/O
Port 0: Port 0 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 0 pins
depends upon the pin function selected via the Pin Connect
Block.
Pins 26 and 31 of port 0 are not available.
TXD0 — Transmitter output for UART0.
PWM1 — Pulse Width Modulator output 1.
RXD0 — Receiver input for UART0.
P0.0/TXD0/
PWM1
42[2]
49[3]
L4[2]
K6[3]
O
O
I
P0.1/RXD0/
PWM3/EINT0
O
I
PWM3 — Pulse Width Modulator output 3.
EINT0 — External interrupt 0 input
P0.2/SCL/
CAP0.0
50[4]
58[4]
L6[4]
I/O
SCL — I2C-bus clock input/output. Open-drain output (for
I2C-bus compliance).
I
CAP0.0 — Capture input for Timer 0, channel 0.
SDA — I2C-bus data input/output. Open-drain output (for
I2C-bus compliance).
P0.3/SDA/
MAT0.0/EINT1
M8[4]
I/O
O
I
MAT0.0 — Match output for Timer 0, channel 0.
EINT1 — External interrupt 1 input.
P0.4/SCK0/
CAP0.1
59[2]
61[2]
68[2]
69[3]
L8[2]
I/O
SCK0 — Serial clock for SPI0. SPI clock output from master
or input to slave.
I
CAP0.1 — Capture input for Timer 0, channel 1.
P0.5/MISO0/
MAT0.1
N9[2]
I/O
MISO0 — Master In Slave OUT for SPI0. Data input to SPI
master or data output from SPI slave.
O
MAT0.1 — Match output for Timer 0, channel 1.
P0.6/MOSI0/
CAP0.2
N11[2]
M11[3]
I/O
MOSI0 — Master Out Slave In for SPI0. Data output from SPI
master or data input to SPI slave.
I
I
CAP0.2 — Capture input for Timer 0, channel 2.
P0.7/SSEL0/
PWM2/EINT2
SSEL0 — Slave Select for SPI0. Selects the SPI interface as
a slave.
O
I
PWM2 — Pulse Width Modulator output 2.
EINT2 — External interrupt 2 input.
P0.8/TXD1/
PWM4
75[2]
76[3]
L12[2]
L13[3]
O
O
I
TXD1 — Transmitter output for UART1.
PWM4 — Pulse Width Modulator output 4.
RXD1 — Receiver input for UART1.
P0.9/RXD1/
PWM6/EINT3
O
I
PWM6 — Pulse Width Modulator output 6.
EINT3 — External interrupt 3 input.
P0.10/RTS1/
CAP1.0
78[2]
83[2]
K11[2]
J12[2]
O
I
RTS1 — Request to Send output for UART1.
CAP1.0 — Capture input for Timer 1, channel 0.
CTS1 — Clear to Send input for UART1.
CAP1.1 — Capture input for Timer 1, channel 1.
P0.11/CTS1/
CAP1.1
I
I
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
7 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Symbol
Pin description …continued
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P0.12/DSR1/
MAT1.0/RD4
84[2]
J13[2]
H10[2]
G10[3]
I
DSR1 — Data Set Ready input for UART1.
MAT1.0 — Match output for Timer 1, channel 0.
RD4 — CAN4 receiver input (LPC2294 only).
DTR1 — Data Terminal Ready output for UART1.
MAT1.1 — Match output for Timer 1, channel 1.
TD4 — CAN4 transmitter output (LPC2294 only).
DCD1 — Data Carrier Detect input for UART1.
EINT1 — External interrupt 1 input.
O
I
P0.13/DTR1/
MAT1.1/TD4
85[2]
O
O
O
I
P0.14/DCD1/
EINT1
92[3]
I
Note: LOW on this pin while RESET is LOW forces on-chip
bootloader to take over control of the part after reset.
P0.15/RI1/
EINT2
99[3]
E11[3]
E10[3]
I
RI1 — Ring Indicator input for UART1.
I
EINT2 — External interrupt 2 input.
P0.16/EINT0/
100[3]
I
EINT0 — External interrupt 0 input.
MAT0.2/CAP0.2
O
MAT0.2 — Match output for Timer 0, channel 2.
CAP0.2 — Capture input for Timer 0, channel 2.
CAP1.2 — Capture input for Timer 1, channel 2.
I
P0.17/CAP1.2/ 101[2]
SCK1/MAT1.2
D13[2]
D8[2]
C8[2]
B8[3]
I
I/O
SCK1 — Serial Clock for SPI1. SPI clock output from master
or input to slave.
O
I
MAT1.2 — Match output for Timer 1, channel 2.
CAP1.3 — Capture input for Timer 1, channel 3.
P0.18/CAP1.3/ 121[2]
MISO1/MAT1.3
I/O
MISO1 — Master In Slave Out for SPI1. Data input to SPI
master or data output from SPI slave.
O
MAT1.3 — Match output for Timer 1, channel 3.
MAT1.2 — Match output for Timer 1, channel 2.
P0.19/MAT1.2/ 122[2]
MOSI1/CAP1.2
O
I/O
MOSI1 — Master Out Slave In for SPI1. Data output from SPI
master or data input to SPI slave.
I
CAP1.2 — Capture input for Timer 1, channel 2.
MAT1.3 — Match output for Timer 1, channel 3.
P0.20/MAT1.3/ 123[3]
SSEL1/EINT3
O
I
SSEL1 — Slave Select for SPI1. Selects the SPI interface as
a slave.
I
EINT3 — External interrupt 3 input.
P0.21/PWM5/
RD3/CAP1.3
4[2]
C1[2]
D4[2]
O
I
PWM5 — Pulse Width Modulator output 5.
RD3 — CAN3 receiver input (LPC2294 only).
CAP1.3 — Capture input for Timer 1, channel 3.
TD3 — CAN3 transmitter output (LPC2294 only).
CAP0.0 — Capture input for Timer 0, channel 0.
MAT0.0 — Match output for Timer 0, channel 0.
RD2 — CAN2 receiver input.
I
P0.22/CAP0.0/ 5[2]
MAT0.0
O
I
O
I
P0.23/RD2
P0.24/TD2
P0.25
6[2]
8[2]
21[2]
D3[2]
D1[2]
H1[2]
O
I
TD2 — CAN2 transmitter output.
RD1 — CAN1 receiver input.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
8 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Symbol
Pin description …continued
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P0.27/AIN0/
CAP0.1/MAT0.1
23[5]
H3[5]
J1[5]
L1[5]
L2[5]
I
AIN0 — ADC, input 0. This analog input is always connected
to its pin.
I
CAP0.1 — Capture input for Timer 0, channel 1.
MAT0.1 — Match output for Timer 0, channel 1.
O
I
P0.28/AIN1/
CAP0.2/MAT0.2
25[5]
32[5]
33[5]
AIN1 — ADC, input 1. This analog input is always connected
to its pin.
I
CAP0.2 — Capture input for Timer 0, channel 2.
MAT0.2 — Match output for Timer 0, channel 2.
O
I
P0.29/AIN2/
CAP0.3/MAT0.3
AIN2 — ADC, input 2. This analog input is always connected
to its pin.
I
CAP0.3 — Capture input for Timer 0, Channel 3.
MAT0.3 — Match output for Timer 0, channel 3.
O
I
P0.30/AIN3/
AIN3 — ADC, input 3. This analog input is always connected
EINT3/CAP0.0
to its pin.
I
EINT3 — External interrupt 3 input.
I
CAP0.0 — Capture input for Timer 0, channel 0.
P1.0 to P1.31
I/O
Port 1: Port 1 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 1 pins
depends upon the pin function selected via the Pin Connect
Block.
Pins 2 through 15 of port 1 are not available.
CS0 — LOW-active Chip Select 0 signal.
(Bank 0 addresses range 8000 0000 to 80FF FFFF)
OE — LOW-active Output Enable signal.
P1.0/CS0
P1.1/OE
91[6]
G11[6]
O
90[6]
34[6]
G13[6]
L3[6]
O
O
P1.16/
TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with
TRACEPKT0
internal pull-up.
P1.17/
TRACEPKT1
24[6]
15[6]
7[6]
H4[6]
F2[6]
O
O
O
O
TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with
internal pull-up.
P1.18/
TRACEPKT2
TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with
internal pull-up.
P1.19/
TRACEPKT3
D2[6]
D12[6]
TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with
internal pull-up.
P1.20/
102[6]
TRACESYNC — Trace Synchronization. Standard I/O port
TRACESYNC
with internal pull-up.
Note: LOW on this pin while RESET is LOW, enables pins
P1[25:16] to operate as Trace port after reset.
P1.21/
PIPESTAT0
95[6]
86[6]
82[6]
70[6]
F11[6]
H11[6]
J11[6]
L11[6]
O
O
O
O
PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with
internal pull-up.
P1.22/
PIPESTAT1
PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with
internal pull-up.
P1.23/
PIPESTAT2
PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with
internal pull-up.
P1.24/
TRACECLK — Trace Clock. Standard I/O port with internal
TRACECLK
pull-up.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
9 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Symbol
Pin description …continued
Pin (LQFP)
Pin
(TFBGA)[1]
Type
I
Description
P1.25/EXTIN0 60[6]
K8[6]
N6[6]
EXTIN0 — External Trigger Input. Standard I/O with internal
pull-up.
P1.26/RTCK
52[6]
I/O
RTCK — Returned Test Clock output. Extra signal added to
the JTAG port. Assists debugger synchronization when
processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins
P1[31:26] to operate as Debug port after reset.
P1.27/TDO
P1.28/TDI
144[6]
140[6]
126[6]
113[6]
43[6]
B2[6]
A3[6]
A7[6]
D10[6]
M4[6]
O
TDO — Test Data out for JTAG interface.
TDI — Test Data in for JTAG interface.
TCK — Test Clock for JTAG interface.
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
I
P1.29/TCK
P1.30/TMS
P1.31/TRST
P2.0 to P2.31
I
I
I
I/O
Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 2 pins
depends upon the pin function selected via the Pin Connect
Block.
P2.0/D0
98[6]
E12[6]
C12[6]
C11[6]
B12[6]
A13[6]
C10[6]
B10[6]
A10[6]
D9[6]
C9[6]
A9[6]
A8[6]
B7[6]
C7[6]
A6[6]
B6[6]
C6[6]
D6[6]
A5[6]
B5[6]
D5[6]
A4[6]
A1[6]
E3[6]
E2[6]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D0 — External memory data line 0.
D1 — External memory data line 1.
D2 — External memory data line 2.
D3 — External memory data line 3.
D4 — External memory data line 4.
D5 — External memory data line 5.
D6 — External memory data line 6.
D7 — External memory data line 7.
D8 — External memory data line 8.
D9 — External memory data line 9.
D10 — External memory data line 10.
D11 — External memory data line 11.
D12 — External memory data line 12.
D13 — External memory data line 13.
D14 — External memory data line 14.
D15 — External memory data line 15.
D16 — External memory data line 16.
D17 — External memory data line 17.
D18 — External memory data line 18.
D19 — External memory data line 19.
D20 — External memory data line 20.
D21 — External memory data line 21.
D22 — External memory data line 22.
D23 — External memory data line 23.
D24 — External memory data line 24.
P2.1/D1
105[6]
106[6]
108[6]
109[6]
114[6]
115[6]
116[6]
117[6]
118[6]
120[6]
124[6]
125[6]
127[6]
129[6]
130[6]
131[6]
132[6]
133[6]
134[6]
136[6]
137[6]
1[6]
P2.2/D2
P2.3/D3
P2.4/D4
P2.5/D5
P2.6/D6
P2.7/D7
P2.8/D8
P2.9/D9
P2.10/D10
P2.11/D11
P2.12/D12
P2.13/D13
P2.14/D14
P2.15/D15
P2.16/D16
P2.17/D17
P2.18/D18
P2.19/D19
P2.20/D20
P2.21/D21
P2.22/D22
P2.23/D23
P2.24/D24
10[6]
11[6]
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
10 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Symbol
Pin description …continued
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P2.25/D25
12[6]
13[6]
E1[6]
F4[6]
I/O
I/O
I
D25 — External memory data line 25.
D26 — External memory data line 26.
P2.26/D26/
BOOT0
BOOT0 — While RESET is low, together with BOOT1 controls
booting and internal operation. Internal pull-up ensures high
state if pin is left unconnected.
P2.27/D27/
BOOT1
16[6]
F1[6]
I/O
I
D27 — External memory data line 27.
BOOT1 — While RESET is low, together with BOOT0 controls
booting and internal operation. Internal pull-up ensures high
state if pin is left unconnected.
BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.
BOOT1:0 = 01 selects 16-bit memory on CS0 for boot.
BOOT1:0 = 10 selects 32-bit memory on CS0 for boot.
BOOT1:0 = 11 selects internal flash memory.
D28 — External memory data line 28.
P2.28/D28
P2.29/D29
17[6]
18[6]
19[3]
G2[6]
G1[6]
G3[3]
I/O
I/O
I/O
I
D29 — External memory data line 29.
P2.30/D30/
AIN4
D30 — External memory data line 30.
AIN4 — ADC, input 4. This analog input is always connected
to its pin.
P2.31/D31/
AIN5
20[3]
G4[3]
I/O
I
D31 — External memory data line 31.
AIN5 — ADC, input 5. This analog input is always connected
to its pin.
P3.0 to P3.31
I/O
Port 3 — Port 3 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 3 pins
depends upon the pin function selected via the Pin Connect
Block.
P3.0/A0
89[6]
88[6]
87[6]
81[6]
80[6]
74[6]
73[6]
72[6]
71[6]
66[6]
65[6]
64[6]
63[6]
62[6]
56[6]
55[6]
53[6]
48[6]
G12[6]
H13[6]
H12[6]
J10[6]
K13[6]
M13[6]
N13[6]
M12[6]
N12[6]
M10[6]
N10[6]
K9[6]
L9[6]
M9[6]
K7[6]
L7[6]
M7[6]
N5[6]
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A0 — External memory address line 0.
A1 — External memory address line 1.
A2 — External memory address line 2.
A3 — External memory address line 3.
A4 — External memory address line 4.
A5 — External memory address line 5.
A6 — External memory address line 6.
A7 — External memory address line 7.
A8 — External memory address line 8.
A9 — External memory address line 9.
A10 — External memory address line 10.
A11 — External memory address line 11.
A12 — External memory address line 12.
A13 — External memory address line 13.
A14 — External memory address line 14.
A15 — External memory address line 15.
A16 — External memory address line 16.
A17 — External memory address line 17.
P3.1/A1
P3.2/A2
P3.3/A3
P3.4/A4
P3.5/A5
P3.6/A6
P3.7/A7
P3.8/A8
P3.9/A9
P3.10/A10
P3.11/A11
P3.12/A12
P3.13/A13
P3.14/A14
P3.15/A15
P3.16/A16
P3.17/A17
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
11 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Symbol
Pin description …continued
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P3.18/A18
P3.19/A19
P3.20/A20
P3.21/A21
P3.22/A22
47[6]
46[6]
45[6]
44[6]
41[6]
40[6]
M5[6]
L5[6]
K5[6]
N4[6]
K4[6]
N3[6]
O
O
O
O
O
I/O
O
O
A18 — External memory address line 18.
A19 — External memory address line 19.
A20 — External memory address line 20.
A21 — External memory address line 21.
A22 — External memory address line 22.
A23 — External memory address line 23.
XCLK — Clock output.
P3.23/A23/
XCLK
P3.24/CS3
P3.25/CS2
P3.26/CS1
P3.27/WE
36[6]
35[6]
30[6]
M2[6]
M1[6]
K2[6]
CS3 — LOW-active Chip Select 3 signal.
(Bank 3 addresses range 8300 0000 to 83FF FFFF)
CS2 — LOW-active Chip Select 2signal.
(Bank 2 addresses range 8200 0000 to 82FF FFFF)
CS1 — LOW-active Chip Select 1 signal.
(Bank 1 addresses range 8100 0000 to 81FF FFFF)
WE — LOW-active Write enable signal.
BLS3 — LOW-active Byte Lane Select signal (Bank 3).
O
O
29[6]
28[3]
K1[6]
J4[3]
O
O
I
P3.28/BLS3/
AIN7
AIN7 — ADC, input 7. This analog input is always connected
to its pin.
P3.29/BLS2/
AIN6
27[5]
J3[5]
O
I
BLS2 — LOW-active Byte Lane Select signal (Bank 2).
AIN6 — ADC, input 6. This analog input is always connected
to its pin.
P3.30/BLS1
P3.31/BLS0
TD1
97[5]
96[5]
22[6]
135[7]
E13[5]
F10[5]
H2[6]
O
O
O
I
BLS1 — LOW-active Byte Lane Select signal (Bank 1).
BLS0 — LOW-active Byte Lane Select signal (Bank 0).
TD1: CAN1 transmitter output.
RESET
C5[7]
External Reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
XTAL1
142[8]
141[8]
C3[8]
B3[8]
I
Input to the oscillator circuit and internal clock generator
circuits.
XTAL2
VSS
O
I
Output from the oscillator amplifier.
3, 9, 26, 38, C2, E4, J2,
54, 67, 79, N2, N7, L10,
93, 103, 107, K12, F13,
Ground: 0 V reference.
111, 128
D11, B13,
B11, D7
VSSA
139
C4
I
I
I
Analog ground: 0 V reference. This should nominally be the
same voltage as VSS, but should be isolated to minimize noise
and error.
VSSA(PLL)
138
B4
PLL analog ground: 0 V reference. This should nominally be
the same voltage as VSS, but should be isolated to minimize
noise and error.
VDD(1V8)
37, 110
N1, A12
1.8 V core power supply: This is the power supply voltage
for internal circuitry.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
12 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Symbol
Pin description …continued
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
VDDA(1V8)
143
A2
I
Analog 1.8 V core power supply: This is the power supply
voltage for internal circuitry. This should be nominally the
same voltage as VDD(1V8) but should be isolated to minimize
noise and error.
VDD(3V3)
2, 31, 39, 51, B1, K3, M3,
57, 77, 94, M6, N8, K10,
104, 112, 119 F12, C13,
A11, B9
I
I
3.3 V pad power supply: This is the power supply voltage for
the I/O ports.
VDDA(3V3)
14
F3
Analog 3.3 V pad power supply: This should be nominally
the same voltage as VDD(3V3) but should be isolated to
minimize noise and error.
[1] LPC2294 only.
[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
[3] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input
function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[4] Open drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
functionality.
[5] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured
for a digital input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input,
digital section of the pad is disabled.
[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ.
[7] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
[8] Pad provides special analog functionality.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
13 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on RISC
principles, and the instruction set and related decode mechanism are much simpler than
those of microprogrammed CISC. This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-chip flash program memory
The LPC2292/LPC2294 incorporate a 256 kB flash memory system respectively. This
memory may be used for both code and data storage. Programming of the flash memory
may be accomplished in several ways. It may be programmed In System via the serial
port. The application program may also erase and/or program the flash while the
application is running, allowing a great degree of flexibility for data storage field firmware
upgrades, etc. When the on-chip bootloader is used, 248 kB of flash memory is available
for user code.
The LPC2292/LPC2294 flash memory provides a minimum of 100000 erase/write cycles
and 20 years of data retention.
On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the
LPC2292/LPC2294 on-chip flash memory. When the CRP is enabled, the JTAG debug
port, external memory boot and ISP commands accessing either the on-chip RAM or flash
memory are disabled. However, the ISP flash erase command can be executed at any
time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of
full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is
restored.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
14 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6.3 On-chip SRAM
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8-bit, 16-bit, and 32-bit. The LPC2292/LPC2294 provide 16 kB of SRAM.
6.4 Memory map
The LPC2292/LPC2294 memory maps incorporate several distinct regions, as shown in
Figure 4.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.21
“System control”.
4.0 GB
3.75 GB
3.5 GB
0xFFFF FFFF
AHB PERIPHERALS
VPB PERIPHERALS
0xF000 0000
0xEFFF FFFF
0xE000 0000
0xDFFF FFFF
0xC000 0000
3.0 GB
RESERVED ADDRESS SPACE
0x8000 0000
0x7FFF FFFF
2.0 GB
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP FLASH MEMORY
0x7FFF E000
0x7FFF DFFF
RESERVED ADDRESS SPACE
16 KBYTE ON-CHIP STATIC RAM
0x4001 0000
0x4000 3FFF
0x4000 0000
0x3FFF FFFF
1.0 GB
RESERVED ADDRESS SPACE
0x0004 0000
0x0003 FFFF
256 KBYTE ON-CHIP FLASH MEMORY
0x0000 0000
0.0 GB
002aaa754
Fig 4. LPC2292/LPC2294 memory map
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
15 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored
IRQ, and non-vectored IRQ as defined by programmable settings. The programmable
assignment scheme means that priorities of interrupts from the various peripherals can be
dynamically assigned and adjusted.
Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned
to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor.
The fastest possible FIQ latency is achieved when only one request is classified as FIQ,
because then the FIQ service routine can simply start dealing with that device. But if more
than one request is assigned to the FIQ class, the FIQ service routine can read a word
from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Table 5 lists the interrupt sources for each peripheral function. Each peripheral device has
one interrupt line connected to the VIC, but may have several internal interrupt flags.
Individual interrupt flags may also represent more than one interrupt source.
Table 5.
Block
Interrupt sources
Flag(s)
VIC channel #
WDT
Watchdog Interrupt (WDINT)
0
1
2
3
4
-
Reserved for software interrupts only
EmbeddedICE, DbgCommRx
ARM Core
ARM Core
Timer 0
EmbeddedICE, DbgCommTx
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
RX Line Status (RLS)
Timer 1
UART0
5
6
Transmit Holding Register Empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
16 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 5.
Block
Interrupt sources …continued
Flag(s)
VIC channel #
UART1
RX Line Status (RLS)
7
Transmit Holding Register empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
SI (state change)
PWM0
I2C
8
9
SPI0
SPI1
PLL
SPIF, MODF
10
SPIF, MODF
11
PLL Lock (PLOCK)
12
RTC
RTCCIF (Counter Increment), RTCALF (Alarm)
13
System Control External Interrupt 0 (EINT0)
14
External Interrupt 1 (EINT1)
External Interrupt 2 (EINT2)
External Interrupt 3 (EINT3)
ADC
15
16
17
A/D
18
CAN
1 ORed CAN Acceptance Filter
CAN1 (TX int, RX int)
19
20, 21
22, 23
24, 25
26, 27
CAN2 (TX int, RX int)
CAN3 (TX int, RX int) - LPC2294 only
CAN4 (TX int, RX int) - LPC2294 only
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
The pin control module contains three registers as shown in Table 6.
Table 6.
Pin control module registers
Address
Name
Description
Access
0xE002 C000
0xE002 C004
0xE002 C014
PINSEL0
PINSEL1
PINSEL2
pin function select register 0
pin function select register 1
pin function select register 2
read/write
read/write
read/write
6.7 Pin function select register 0 (PINSEL0 - 0xE002 C000)
The PINSEL0 register controls the functions of the pins as per the settings listed in
Table 7. The direction control bit in the IODIR register is effective only when the GPIO
function is selected for a pin. For other functions, direction is controlled automatically.
Settings other than those shown in Table 7 are reserved, and should not be used
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
17 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 7.
PINSEL0
1:0
Pin function select register 0 (PINSEL0 - 0xE002 C000)
Pin name
Value
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Function
Value after reset
P0.0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GPIO Port 0.0
TXD (UART0)
PWM1
0
reserved
3:2
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
GPIO Port 0.1
RXD (UART0)
PWM3
0
0
0
0
0
0
0
0
0
EINT0
5:4
GPIO Port 0.2
SCL (I2C-bus)
Capture 0.0 (Timer 0)
reserved
7:6
GPIO Port 0.3
SDA (I2C-bus)
Match 0.0 (Timer 0)
EINT1
9:8
GPIO Port 0.4
SCK (SPI0)
Capture 0.1 (Timer 0)
reserved
11:10
13:12
15:14
17:16
19:18
GPIO Port 0.5
MISO (SPI0)
Match 0.1 (Timer 0)
reserved
GPIO Port 0.6
MOSI (SPI0)
Capture 0.2 (Timer 0)
reserved
GPIO Port 0.7
SSEL (SPI0)
PWM2
EINT2
GPIO Port 0.8
TXD UART1
PWM4
reserved
GPIO Port 0.9
RXD (UART1)
PWM6
EINT3
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
18 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 7.
PINSEL0
21:20
Pin function select register 0 (PINSEL0 - 0xE002 C000) …continued
Pin name
Value
Function
Value after reset
P0.10
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
GPIO Port 0.10
RTS (UART1)
Capture 1.0 (Timer 1)
reserved
0
23:22
25:24
P0.11
P0.12
GPIO Port 0.11
CTS (UART1)
Capture 1.1 (Timer 1)
reserved
0
0
GPIO Port 0.12
DSR (UART1)
Match 1.0 (Timer 1)
RD4[1] (CAN Controller
4)
27:26
29:28
31:30
P0.13
P0.14
P0.15
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
GPIO Port 0.13
DTR (UART1)
Match 1.1 (Timer 1)
TD4[1] (CAN Controller 4)
GPIO Port 0.14
DCD (UART1)
EINT1
0
0
0
reserved
GPIO Port 0.15
RI (UART1)
EINT2
reserved
[1] CAN controller 4 is available in LPC2294 only. Fields in Table 7 related to CAN4 have a reserved value for
LPC2292.
6.8 Pin function select register 1 (PINSEL1 - 0xE002 C004)
The PINSEL1 register controls the functions of the pins as per the settings listed in
Table 8. The direction control bit in the IODIR register is effective only when the GPIO
function is selected for a pin. For other functions direction is controlled automatically.
Settings other than those shown in Table 8 are reserved, and should not be used.
Table 8.
Pin function select register 1 (PINSEL1 - 0xE002 C004)
PINSEL1
Pin Name
Value
Function
Value after
reset
1:0
P0.16
0
0
1
1
0
1
0
1
GPIO Port 0.16
EINT0
0
Match 0.2 (Timer 0)
reserved
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
19 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 8.
Pin function select register 1 (PINSEL1 - 0xE002 C004) …continued
PINSEL1
Pin Name
Value
Function
Value after
reset
3:2
P0.17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GPIO Port 0.17
Capture 1.2 (Timer 1)
SCK (SPI1)
0
0
0
0
0
0
0
0
0
0
Match 1.2 (Timer 1)
GPIO Port 0.18
Capture 1.3 (Timer 1)
MISO (SPI1)
5:4
P0.18
P0.19
P0.20
P0.21
P0.22
P0.23
P0.24
P0.25
P0.26
Match 1.3 (Timer 1)
GPIO Port 0.19
Match 1.2 (Timer 1)
MOSI (SPI1)
7:6
Match 1.3 (Timer 1)
GPIO Port 0.20
Match 1.3 (Timer 1)
SSEL (SPI1)
9:8
EINT3
11:10
13:12
15:14
17:16
19:18
21:20
GPIO Port 0.21
PWM5
RD3[1] (CAN Controller 3)
Capture 1.3 (Timer 1)
GPIO Port 0.22
TD3[1] (CAN Controller 3)
Capture 0.0 (Timer 0)
Match 0.0 (Timer 0)
GPIO Port 0.23
RD2 (CAN Controller 2)
reserved
reserved
GPIO Port 0.24
TD2 (CAN Controller 2)
reserved
reserved
GPIO Port 0.25
RD1 (CAN Controller 1)
reserved
reserved
reserved
reserved
reserved
reserved
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
20 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 8.
Pin function select register 1 (PINSEL1 - 0xE002 C004) …continued
PINSEL1
Pin Name
Value
Function
Value after
reset
23:22
25:24
27:26
29:28
31:30
P0.27
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GPIO Port 0.27
AIN0 (ADC)
1
1
1
1
0
Capture 0.1 (Timer 0)
Match 0.1 (Timer 0)
GPIO Port 0.28
AIN1 (ADC)
P0.28
P0.29
P0.30
P0.31
Capture 0.2 (Timer 0)
Match 0.2 (Timer 0)
GPIO Port 0.29
AIN2 (ADC)
Capture 0.3 (Timer 0)
Match 0.3 (Timer 0)
GPIO Port 0.30
AIN3 (ADC)
EINT3
Capture 0.0 (Timer 0)
reserved
reserved
reserved
reserved
[1] CAN controller 3 is available in LPC2294 only. Fields in Table 8 related to CAN3 have a reserved value for
LPC2292.
6.9 Pin function select register 2 (PINSEL2 - 0xE002 C014)
The PINSEL2 register controls the functions of the pins as per the settings listed in
Table 9. The direction control bit in the IODIR register is effective only when the GPIO
function is selected for a pin. For other functions direction is controlled automatically.
Settings other than those shown in Table 9 are reserved, and should not be used.
Table 9.
Pin function select register 2 (PINSEL2 - 0xE002 C014)
PINSEL2 bits
Description
Reset value
-
1:0
2
reserved
When 0, pins P1[36:26] are used as GPIO pins. When 1, P1[31:26] are used as a
Debug port.
P1.26/RTCK
3
When 0, pins P1[25:16] are used as GPIO pins. When 1, P1[25:16] are used as a
Trace port.
P1.20/
TRACESYNC
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
21 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 9.
PINSEL2 bits
5:4
Pin function select register 2 (PINSEL2 - 0xE002 C014) …continued
Description
Controls the use of the data bus and strobe pins:
Reset value
BOOT1:0
Pins P2[7:0]
Pin P1.0
11 = P2[7:0]
11 = P1.0
0x or 10 = D7 to D0
0x or 10 = CS0
0x or 10 = OE
Pin P1.1
11 = P1.1
Pin P3.31
11 = P3.31
0x or 10 = BLS0
01 or 10 = D15 to D8
01 or 10 = BLS1
10 = D27 to D16
10 = D29, D28
Pins P2[15:8]
Pin P3.30
00 or 11 = P2[15:8]
00 or 11 = P3.30
0x or 11 = P2[27:16]
0x or 11 = P2[29:28] or reserved
Pins P2[27:16]
Pins P2[29:28]
Pins P2[31:30]
0x or 11 = P2[31:30] or AIN5 to
AIN4
10 = D31, D30
Pins P3[29:28]
0x or 11 = P3[29:28] or AIN7 to
AIN6
10 = BLS2, BLS3
6
7
If bits 5:4 are not 10, controls the use of pin P3.29: 0 enables P3.29, 1 enables
AIN6.
1
1
If bits 5:4 are not 10, controls the use of pin P3.28: 0 enables P3.28, 1 enables
AIN7.
8
Controls the use of pin P3.27: 0 enables P3.27, 1 enables WE.
0
-
10:9
11
12
13
reserved
Controls the use of pin P3.26: 0 enables P3.26, 1 enables CS1.
reserved
0
-
If bits 25:23 are not 111, controls the use of pin P3.23/A23/XCLK: 0 enables P3.23,
1 enables XCLK.
0
15:14
17:16
Controls the use of pin P3.25: 00 enables P3.25, 01 enables CS2, 10 and 11 are
reserved values.
00
00
Controls the use of pin P3.24: 00 enables P3.24, 01 enables CS3, 10 and 11 are
reserved values.
19:18
20
reserved
-
If bits 5:4 are not 10, controls the use of pin P2[29:28]: 0 enables P2[29:28], 1 is
reserved
0
21
22
23
If bits 5:4 are not 10, controls the use of pin P2.30: 0 enables P2.30, 1 enables
AIN4.
1
1
If bits 5:4 are not 10, controls the use of pin P2.31: 0 enables P2.31, 1 enables
AIN5.
Controls whether P3.0/A0 is a port pin (0) or an address line (1).
1 if BOOT1:0 = 00
at RESET = 0,
0 otherwise
24
Controls whether P3.1/A1 is a port pin (0) or an address line (1).
BOOT1 during
reset
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
22 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 9.
Pin function select register 2 (PINSEL2 - 0xE002 C014) …continued
PINSEL2 bits
27:25
Description
Reset value
Controls the number of pins among P3.23/A23/XCLK and P3[22:2]/A2[22:2] that are 000 if
address lines:
BOOT1:0 = 11 at
reset, 111
otherwise
000 = None
100 = A11 to A2 are address lines.
101 = A15 to A2 are address lines.
001 = A3 to A2 are address
lines.
010 = A5 to A2 are address
lines.
110 = A19 to A2 are address lines.
111 = A23 to A2 are address lines.
011 = A7 to A2 are address
lines.
31:28
reserved
6.10 External memory controller
The external Static Memory Controller is a module which provides an interface between
the system bus and external (off-chip) memory devices. It provides support for up to four
independently configurable memory banks (16 MB each with byte lane enable control)
simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash EPROM,
burst ROM memory, or some external I/O devices.
Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
6.11 General purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
6.11.1 Features
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
6.12 10-bit ADC
The LPC2292/LPC2294 each contain single 10-bit successive approximation ADC with
eight multiplexed channels.
6.12.1 Features
• Measurement range of 0 V to 3 V.
• Capable of performing more than 400000 10-bit samples per second.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
23 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6.13 CAN controllers and acceptance filter
The LPC2292/LPC2294 each contain two/four CAN controllers. The CAN is a serial
communications protocol which efficiently supports distributed real-time control with a
very high level of security. Its domain of application ranges from high-speed networks to
low cost multiplex wiring.
6.13.1 Features
• Data rates up to 1 Mbit/s on each bus.
• 32-bit register and RAM access.
• Compatible with CAN specification 2.0B, ISO 11898-1.
• Global Acceptance Filter recognizes 11-bit and 29-bit RX identifiers for all CAN buses.
• Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard identifiers.
6.14 UARTs
The LPC2292/LPC2294 each contain two UARTs. One UART provides a full modem
control handshake interface, the other provides only transmit and receive data lines.
6.14.1 Features
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in baud rate generator.
• Standard modem interface signals included on UART1.
6.15 I2C-bus serial I/O controller
The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2292/LPC2294 supports bit rate up to 400 kbit/s (Fast
I2C-bus).
6.15.1 Features
• Compliant with standard I2C-bus interface.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
24 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus may be used for test and diagnostic purposes.
6.16 SPI serial I/O controller
The LPC2292/LPC2294 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
6.16.1 Features
• Compliant with SPI specification.
• Synchronous, serial, full duplex, communication.
• Combined SPI master and slave.
• Maximum data bit rate of one eighth of the input clock rate.
6.17 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. It also includes four capture inputs to trap the timer value when an input
signal transitions, optionally generating an interrupt. Multiple pins can be selected to
perform a single capture or match function, providing an application with ‘or’ and ‘and’, as
well as ‘broadcast’ functions among them.
6.17.1 Features
• A 32-bit Timer/Counter with a programmable 32-bit prescaler.
• Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Four external outputs per timer corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
25 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
– Do nothing on match.
6.18 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
6.18.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal pre-scaler.
• Selectable time period from (Tcy(PCLK) × 256 × 4) to (Tcy(PCLK) × 232 × 4) in multiples of
T
cy(PCLK) × 4.
6.19 Real-time clock
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use little
power, making it suitable for battery powered systems where the CPU is not running
continuously (Idle mode).
6.19.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra-low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
• Programmable Reference Clock Divider allows adjustment of the RTC to match
various crystal frequencies.
6.20 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2292/LPC2294. The Timer is designed to
count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform
other actions when specified timer values occur, based on seven match registers. The
PWM function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires three
non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
26 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
6.20.1 Features
• Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
• The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit prescaler.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
27 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6.21 System control
6.21.1 Crystal oscillator
The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output
frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for
purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is
running and connected. Refer to Section 6.21.2 “PLL” for additional information.
6.21.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100 µs.
6.21.3 Reset and wake-up timer
Reset has two sources on the LPC2292/LPC2294: the RESET pin and watchdog reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip reset by any source starts the Wake-up Timer (see Wake-up Timer description
below), causing the internal chip reset to remain asserted until the external reset is
de-asserted, the oscillator is running, a fixed number of clocks have passed, and the
on-chip flash controller has completed its initialization.
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The Wake-up Timer ensures that the oscillator and other analog functions required for
chip operation are fully functional before the processor is allowed to execute instructions.
This is important at power-on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power-on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
28 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6.21.4 External interrupt inputs
The LPC2292/LPC2294 include up to nine edge or level sensitive External Interrupt Inputs
as selectable pin functions. When the pins are combined, external events can be
processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake up the processor from Power-down mode.
6.21.5 Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
6.21.6 Power control
The LPC2292/LPC2294 support two reduced power modes: Idle mode and Power-down
mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used
by the processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
6.21.7 VPB bus
The VPB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via VPB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be
slowed down to 1⁄2 to 1⁄4 of the processor clock rate. Because the VPB bus must work
properly at power-up (and its timing cannot be altered if it does not work since the VPB
divider control registers reside on the VPB bus), the default condition at reset is for the
VPB bus to run at 1⁄4 of the processor clock rate. The second purpose of the VPB divider
is to allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the VPB divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.
6.22 Emulation and debugging
The LPC2292/LPC2294 support emulation and debugging via a JTAG serial port. A trace
port allows tracing program execution. Debugging and trace functions are multiplexed only
with GPIOs on Port 1. This means that all communication, timer and interface peripherals
residing on Port 0 are available during the development and debugging phase as they are
when the application is run in the embedded system itself.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
29 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6.22.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the remote
debug protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
6.22.2 Embedded trace
Since the LPC2292/LPC2294 have significant amounts of on-chip memory, it is not
possible to determine how the processor core is operating simply by observing the
external pins. The Embedded Trace Macrocell provides real-time trace capability for
deeply embedded processor cores. It outputs information about processor execution to
the trace port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
pipeline status on a cycle by cycle basis. Trace information generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed. Self-modifying code can not be traced
because of this restriction.
6.22.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real-time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC (Debug
Communications Channel), which is present in the EmbeddedICE logic. The
LPC2292/LPC2294 contain a specific configuration of RealMonitor software programmed
into the on-chip flash memory.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
30 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
7. Limiting values
Table 10. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
VDD(1V8)
VDD(3V3)
VDDA(3V3)
VIA
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−0.5
−0.5
−0.5
-
Max
+2.5
+3.6
4.6
Unit
V
[2]
[3]
supply voltage (1.8 V)
supply voltage (3.3 V)
analog supply voltage (3.3 V)
analog input voltage
input voltage
V
V
5.1
V
[4][5]
[4][6]
[7][8]
[8][9]
[10]
VI
5 V tolerant I/O pins
other I/O pins
6.0
V
VDD(3V3) + 0.5
100
V
IDD
supply current
mA
mA
°C
W
ISS
ground current
-
100
Tstg
storage temperature
−65
-
150
Ptot(pack)
total power dissipation (per
package)
based on package heat
transfer, not device power
consumption
1.5
[11]
[12]
Vesd
electrostatic discharge voltage human body model
all pins
−2000
−200
+2000
+200
V
V
machine model
all pins
[1] The following applies to Table 10:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Internal rail.
[3] External rail.
[4] Including voltage on outputs in 3-state mode.
[5] Only valid when the VDD(3V3) supply voltage is present.
[6] Not to exceed 4.6 V.
[7] Per supply pin.
[8] The peak current is limited to 25 times the corresponding maximum current.
[9] Per ground pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
[12] Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω series resistor.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
31 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
8. Static characteristics
Table 11. Static characteristics
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol Parameter
Conditions
Min
1.65
3.0
Typ[1]
1.8
Max
1.95
3.6
Unit
V
[2]
[3]
VDD(1V8) supply voltage (1.8 V)
VDD(3V3) supply voltage (3.3 V)
3.3
V
VDDA(3V3) analog supply voltage
(3.3 V)
2.5
3.3
3.6
V
Standard port pins, RESET, RTCK
IIL
LOW-state input current
HIGH-state input current
OFF-state output current
VI = 0 V; no pull-up
-
-
-
-
-
-
3
3
3
µA
µA
µA
IIH
IOZ
VI = VDD(3V3); no pull-down
VO = 0 V, VO = VDD(3V3)
;
no pull-up/down
Ilatch
VI
I/O latch-up current
input voltage
−(0.5VDD(3V3)) < VI <
(1.5VDD(3V3)); Tj < 125 °C
100
0
-
-
-
mA
V
[4][5]
[6]
5.5
VO
output voltage
output active
0
-
VDD(3V3)
V
VIH
VIL
HIGH-state input voltage
LOW-state input voltage
hysteresis voltage
2.0
-
-
V
-
-
-
0.8
V
Vhys
VOH
VOL
IOH
IOL
0.4
-
V
[7]
[7]
[7]
[7]
[9]
HIGH-state output voltage IOH = −4 mA
V
-
DD(3V3) − 0.4 -
-
V
LOW-state output voltage
HIGH-state output current
LOW-state output current
IOL = −4 mA
-
-
-
-
0.4
-
V
VOH = VDD(3V3) − 0.4 V
VOL = 0.4 V
−4
4
-
mA
mA
mA
-
IOHS
HIGH-state short-circuit
output current
VOH = 0 V
−45
[9]
IOLS
LOW-state short-circuit
output current
VOL = VDD(3V3)
-
-
50
mA
[10]
[11]
[10]
[12]
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
10
−15
0
50
−50
0
150
−85
0
µA
µA
µA
mA
VI = 0 V
VDD(3V3) < VI < 5 V
IDD(act)
active mode supply current VDD(1V8) = 1.8 V,
CCLK = 60 MHz,
-
50
-
T
amb = 25 °C, code
while(1){}
executed from flash, no
active peripherals
IDD(pd)
Power-down mode supply
current
VDD(1V8) = 1.8 V,
-
-
-
10
-
µA
µA
µA
T
amb = 25 °C,
VDD(1V8) = 1.8 V,
amb = 85 °C
VDD(1V8) = 1.8 V,
amb = 125 °C
110
300
500
1000
T
T
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
32 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 11. Static characteristics …continued
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol Parameter
I2C-bus pins
Conditions
Min
Typ[1]
Max
Unit
VIH
VIL
Vhys
VOL
ILI
HIGH-state input voltage
0.7VDD(3V3)
-
-
V
LOW-state input voltage
hysteresis voltage
-
-
-
-
-
-
0.3VDD(3V3)
V
0.5VDD(3V3)
-
V
[7]
[8]
LOW-state output voltage
input leakage current
IOLS = 3 mA
VI = VDD(3V3)
VI = 5 V
-
0.4
4
V
2
µA
µA
10
22
Oscillator pins
Vi(XTAL1)
input voltage on pin XTAL1
0
0
-
-
1.8
1.8
V
V
Vo(XTAL2) output voltage on pin
XTAL2
[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 °C), nominal supply voltages.
[2] Internal rail.
[3] External rail.
[4] Including voltage on outputs in 3-state mode.
[5] VDD(3V3) supply voltages must be present.
[6] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.
[7] Accounts for 100 mV voltage drop in all supply lines.
[8] To VSS
.
[9] Only allowed for a short time period.
[10] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[11] Applies to P1[25:16].
[12] 1.8 V.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
33 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 12. ADC static characteristics
VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +125 °C unless otherwise specified. ADC frequency 4.5 MHz.
Symbol
VIA
Parameter
Conditions
Min
Typ
Max
VDDA
1
Unit
V
analog input voltage
0
-
-
-
Cia
analog input
capacitance
pF
ED
differential linearity
error
-
-
±1
LSB
[1][2][3]
[1][4]
[1][5]
[1][6]
[1][7]
EL(adj)
EO
integral non-linearity
offset error
-
-
-
-
-
-
-
-
±2
LSB
LSB
%
±3
EG
gain error
±0.5
±4
ET
absolute error
LSB
[1] Conditions: VSSA = 0 V, VDDA = 3.3 V.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5.
[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 5.
[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 5.
[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 5.
[7] The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the
non-calibrated ADC and the ideal transfer curve. See Figure 5.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
34 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
gain
error
offset
error
E
E
O
G
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
IA
(LSB
)
ideal
V
− V
SSA
DDA
1 LSB =
offset
error
1024
002aaa668
E
O
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 5. ADC characteristics
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
35 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
9. Dynamic characteristics
Table 13. Dynamic characteristics
Tamb = −40 °C to +125 °C; VDD(1V8), VDD(3V3) over specified ranges.[1]
Symbol
External clock
fosc
Parameter
Conditions
Min
Typ
Max
Unit
oscillator frequency
supplied by an external
oscillator (signal generator)
1
1
-
-
50
30
MHz
MHz
external clock frequency
supplied by an external
crystal oscillator
external clock frequency if
on-chip PLL is used
10
10
-
-
25
25
MHz
MHz
external clock frequency if
on-chip bootloader is used
for initial code download
Tcy(clk)
tCHCX
tCLCX
tCLCH
tCHCL
clock cycle time
clock HIGH time
clock LOW time
clock rise time
clock fall time
20
-
-
-
-
-
1000
ns
ns
ns
ns
ns
T
T
-
cy(clk) × 0.4
-
cy(clk) × 0.4
-
5
5
-
Port pins (except P0.2 and P0.3)
tr
tf
rise time
-
-
10
10
-
-
ns
ns
fall time
I2C-bus pins (P0.2 and P0.3)
[2]
tf fall time
VIH to VIL
20 + 0.1 × Cb
-
-
ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Bus capacitance Cb in pF, from 10 pF to 400 pF.
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
36 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 14. External memory interface dynamic characteristics
CL = 25 pF, Tamb = 40 °C
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Common to read and write cycles
tCHAV
XCLK HIGH to address valid
time
-
-
10
ns
tCHCSL
tCHCSH
XCLK HIGH to CS LOW time
-
-
-
-
10
10
ns
ns
XCLK HIGH to CS HIGH
time
tCHANV
XCLK HIGH to address
invalid time
-
-
10
ns
Read cycle parameters
tCSLAV CS LOW to address valid
[1]
[1]
−5
−5
−5
-
-
+10
+10
ns
ns
time
tOELAV
OE LOW to address valid
time
tCSLOEL
tam
CS LOW to OE LOW time
memory access time
-
-
+5
-
ns
ns
[2][3]
[2][3]
[2][4]
[5]
(Tcy(CCLK) × (2 + WST1)) +
(−20)
tam(ibr)
tam(sbr)
memory access time (initial
burst-ROM)
(Tcy(CCLK) × (2 + WST1)) +
(−20)
-
-
-
-
ns
ns
memory access time
Tcy(CCLK) + (−20)
(subsequent burst-ROM)
th(D)
data hold time
0
-
-
-
-
ns
ns
ns
tCSHOEH
tOEHANV
CS HIGH to OE HIGH time
−5
−5
+5
+5
OE HIGH to address invalid
time
tCHOEL
tCHOEH
XCLK HIGH to OE LOW time
−5
−5
-
-
+5
+5
ns
ns
XCLK HIGH to OE HIGH
time
Write cycle parameters
[1]
tAVCSL
address valid to CS LOW
T
cy(CCLK) − 10
-
-
ns
time
tCSLDV
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
−5
−5
−5
−5
−5
-
-
-
-
-
-
+5
+5
+5
+5
+5
ns
ns
ns
ns
ns
ns
tCSLWEL
tCSLBLSL
tWELDV
tCSLDV
[2]
[2]
[2]
tWELWEH
T
T
T
cy(CCLK) × (1 + WST2) − 5
cy(CCLK) × (1 + WST2) − 5
cy(CCLK) − 5
T
cy(CCLK) × (1 +
WST2) + 5
tBLSLBLSH BLS LOW to BLS HIGH time
-
-
Tcy(CCLK)
(1 + WST2) + 5
×
ns
ns
tWEHANV
tWEHDNV
WE HIGH to address invalid
time
Tcy(CCLK) + 5
[2]
[2]
WE HIGH to data invalid time
(2 × Tcy(CCLK)) − 5
Tcy(CCLK) − 5
-
-
(2 × Tcy(CCLK)) + 5 ns
Tcy(CCLK) + 5 ns
tBLSHANV BLS HIGH to address invalid
time
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
37 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 14. External memory interface dynamic characteristics …continued
CL = 25 pF, Tamb = 40 °C
Symbol
Parameter
Conditions
Min
Typ Max
Unit
[2]
tBLSHDNV BLS HIGH to data invalid
time
(2 × Tcy(CCLK)) − 5
-
-
-
-
-
-
-
(2 × Tcy(CCLK)) + 5 ns
tCHDV
XCLK HIGH to data valid
time
-
-
-
-
-
-
10
10
10
10
10
10
ns
ns
ns
ns
ns
ns
tCHWEL
tCHBLSL
tCHWEH
tCHBLSH
tCHDNV
XCLK HIGH to WE LOW
time
XCLK HIGH to BLS LOW
time
XCLK HIGH to WE HIGH
time
XCLK HIGH to BLS HIGH
time
XCLK HIGH to data invalid
time
[1] Except on initial access, in which case the address is set up Tcy(CCLK) earlier.
[2] Tcy(CCLK) = 1⁄CCLK.
[3] Latest of address valid, CS LOW, OE LOW to data valid.
[4] Address valid to data valid.
[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.
Table 15. Standard read access specifications
Access cycle
Max frequency
WST setting
Memory access time requirement
WST ≥ 0; round up to
integer
standard read
2 + WST1
RAM + 20 ns
t
RAM + 20 ns
tRAM ≤ tcy(CCLK) × (2 + WST1) – 20 ns
f MAX
f MAX
f MAX
f MAX
≤
≤
≤
≤
--------------------------------
WST1 ≥
WST2 ≥
– 2
--------------------------------
tcy(CCLK)
t
standard write
1 + WST2
t
WRITE – tCYC + 5
tWRITE ≤ tcy(CCLK) × (1 + WST2) – 5 ns
tINIT ≤ tcy(CCLK) × (2 + WST1) – 20 ns
---------------------------------
-------------------------------------------
t
WRITE + 5 ns
tcy(CCLK)
burst read - initial
burst read - subsequent 3×
2 + WST1
tINIT + 20 ns
-------------------------------
WST1 ≥
– 2
-------------------------------
tINIT + 20 ns
tcy(CCLK)
N/A
1
t
ROM ≤ tcy(CCLK) – 20 ns
--------------------------------
tROM + 20 ns
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
38 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
9.1 Timing
XCLK
t
t
CSHOEH
CSLAV
CS
addr
data
t
t
h(D)
am
t
CSLOEL
t
t
OEHANV
OELAV
OE
t
t
CHOEH
CHOEL
002aaa749
Fig 6. External memory read access
XCLK
CS
t
CSLDV
t
AVCSL
t
WELWEH
t
CSLWEL
t
BLSLBLSH
BLS/WE
addr
t
WEHANV
t
t
WELDV
CSLBLSL
t
BLSHANV
t
t
WEHDNV
BLSHDNV
t
CSLDV
data
OE
002aaa750
Fig 7. External memory write access
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
39 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
V
DD
− 0.5 V
0.2V
+ 0.9 V
DD
0.2V
− 0.1 V
DD
0.45 V
t
CHCX
t
t
t
CHCL
CLCX
CLCH
T
cy(clk)
002aaa907
Fig 8. External clock timing
9.2 LPC2292/LPC2294 power consumption measurements
002aab452
60
I
current
DD
(mA)
(1)
(2)
40
20
0
0
10
20
30
40
50
60
frequency (MHz)
Test conditions: code executed from on-chip RAM; all peripherals are enabled in PCONP register; PCLK = CCLK⁄4.
(1) 1.8 V core at 25 °C (typical)
(2) 1.65 V core at 25 °C (typical)
Fig 9. LPC2292/LPC2294 IDD(act) measured at different frequencies (CCLK) and temperatures
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
40 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
002aab453
15
I
current
DD
(mA)
10
(1)
(2)
5
0
0
10
20
30
40
50
60
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register;
PCLK = CCLK⁄4.
(1) 1.8 V core at 25 °C (typical)
(2) 1.65 V core at 25 °C (typical)
Fig 10. LPC2292/LPC2294 IDD idle measured at different frequencies (CCLK) and temperatures
002aab454
500
I
current
(µA)
DD
(1)
(2)
(3)
400
300
200
100
0
−100
−50
0
50
100
150
temp (°C)
Test conditions: Power-down mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP
register.
(1) 1.95 V core
(2) 1.8 V core
(3) 1.65 V core
Fig 11. LPC2292/LPC2294 IDD(pd) measured at different temperatures
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
41 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
10. Package outline
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
SOT486-1
y
X
A
108
109
73
72
Z
E
e
H
A
E
2
A
E
(A )
3
A
1
θ
w M
p
L
p
b
L
pin 1 index
detail X
37
144
1
36
v
M
A
Z
w M
D
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 20.1 20.1
0.17 0.09 19.9 19.9
22.15 22.15
21.85 21.85
0.75
0.45
1.4
1.1
1.4
1.1
mm
1.6
0.25
1
0.2 0.08 0.08
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-03-14
03-02-20
SOT486-1
136E23
MS-026
Fig 12. Package outline SOT486-1 (LQFP144)
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
42 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
TFBGA144: plastic thin fine-pitch ball grid array package; 144 balls; body 12 x 12 x 0.8 mm
SOT569-1
B
D
A
D
1
ball A1
index area
A
2
A
E
E
A
1
1
detail X
C
e
1
y
y
v M
C
C
A B
C
1
b
e
w M
N
M
L
e
K
J
H
G
F
e
2
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
7
8
9 10111213
shape
X
optional (4×)
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
E
e
e
e
2
y
D
D
E
v
w
y
1
1
2
1
1
1
max.
0.36 0.84 0.53 12.2 11.9 12.2 11.9
0.24 0.74 0.43 11.8 11.7 11.8 11.7
mm
1.2
0.1
0.1
0.8
9.6
9.6
0.15 0.08
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
03-07-09
05-09-14
SOT569-1
MO-216
Fig 13. Package outline SOT569-1 (TFBGA144)
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
43 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
11. Abbreviations
Table 16. Acronym list
Acronym
ADC
Description
Analog-to-Digital Converter
Advanced Microcontroller Bus Architecture
Controller Area Network
AMBA
CAN
CISC
CPU
Complex Instruction Set Computer
Central Processing Unit
FIFO
GPIO
PLL
First In, First Out
General Purpose Input/Output
Phase-Locked Loop
PWM
RAM
RISC
SPI
Pulse Width Modulator
Random Access Memory
Reduced Instruction Set Computer
Serial Peripheral Interface
Static Random Access Memory
Synchronous Serial Port
SRAM
SSP
TTL
Transistor-Transistor Logic
Universal Asynchronous Receiver/Transmitter
VLSI Peripheral Bus
UART
VPB
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
44 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
12. Revision history
Table 17. Revision history
Document ID
LPC2292_2294_4
Modifications:
Release date
20060711
Data sheet status
Change notice
Supersedes
Product data sheet
-
LPC2292_2294_3
• Section 3 “Ordering information”; added new devices LPC2292FBD144/00,
LPC2292FET144/00, and LPC2294HBD144/00; removed LPC2294JBD144.
LPC2292_2294_3
LPC2292_2294-02
20051101
20041223
Product data sheet
Product data
-
-
LPC2292_2294-02
LPC2292_2294-01
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
45 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
13. Legal information
13.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.semiconductors.philips.com.
to result in personal injury, death or severe property or environmental
13.2 Definitions
damage. Philips Semiconductors accepts no liability for inclusion and/or use
of Philips Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Philips Semiconductors
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Terms and conditions of sale — Philips Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.semiconductors.philips.com/profile/terms, including those
pertaining to warranty, intellectual property rights infringement and limitation
of liability, unless explicitly otherwise agreed to in writing by Philips
13.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, Philips Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Semiconductors. In case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — Philips Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — Philips Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a Philips Semiconductors product can reasonably be expected
I2C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.
14. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
46 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Notes
LPC2292_2294_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 11 July 2006
47 of 48
LPC2292/LPC2294
Philips Semiconductors
16/32-bit ARM microcontrollers with external memory interface
15. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.21.3
6.21.4
6.21.5
6.21.6
6.21.7
6.22
6.22.1
6.22.2
6.22.3
Reset and wake-up timer . . . . . . . . . . . . . . . . 28
External interrupt inputs. . . . . . . . . . . . . . . . . 29
Memory mapping control . . . . . . . . . . . . . . . . 29
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 29
VPB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Emulation and debugging. . . . . . . . . . . . . . . . 29
EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 30
Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 30
RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2
2.1
3
3.1
4
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31
Static characteristics . . . . . . . . . . . . . . . . . . . 32
6
Functional description . . . . . . . . . . . . . . . . . . 14
Architectural overview. . . . . . . . . . . . . . . . . . . 14
On-chip flash program memory . . . . . . . . . . . 14
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 16
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 16
Pin connect block . . . . . . . . . . . . . . . . . . . . . . 17
Pin function select register 0 (PINSEL0 -
6.1
6.2
6.3
6.4
6.5
6.5.1
6.6
6.7
9
9.1
9.2
Dynamic characteristics. . . . . . . . . . . . . . . . . 36
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LPC2292/LPC2294 power consumption
measurements . . . . . . . . . . . . . . . . . . . . . . . . 40
10
11
12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 42
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision history . . . . . . . . . . . . . . . . . . . . . . . 45
0xE002 C000). . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin function select register 1 (PINSEL1 -
0xE002 C004). . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin function select register 2 (PINSEL2 -
13
Legal information . . . . . . . . . . . . . . . . . . . . . . 46
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.8
6.9
13.1
13.2
13.3
13.4
0xE002 C014). . . . . . . . . . . . . . . . . . . . . . . . . 21
External memory controller. . . . . . . . . . . . . . . 23
General purpose parallel I/O. . . . . . . . . . . . . . 23
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CAN controllers and acceptance filter . . . . . . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I2C-bus serial I/O controller . . . . . . . . . . . . . . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
General purpose timers . . . . . . . . . . . . . . . . . 25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pulse width modulator . . . . . . . . . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
System control . . . . . . . . . . . . . . . . . . . . . . . . 28
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 28
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10
6.11
6.11.1
6.12
6.12.1
6.13
6.13.1
6.14
6.14.1
6.15
6.15.1
6.16
6.16.1
6.17
6.17.1
6.18
6.18.1
6.19
6.19.1
6.20
6.20.1
6.21
14
15
Contact information . . . . . . . . . . . . . . . . . . . . 46
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.21.1
6.21.2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com.
For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.
Date of release: 11 July 2006
Document identifier: LPC2292_2294_4
相关型号:
LPC2292FET144/00
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface
NXP
LPC2292FET144/00,5
LPC2292/2294 - 16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface BGA 144-Pin
NXP
LPC2292FET144/01
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface
NXP
LPC2292FET144/G
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface
NXP
LPC2292_07
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface
NXP
LPC2294
16/32-bit ARM microcontrollers 256 kB ISP/IAP Flash with CAN, 10-bit ADC and external memory interface
NXP
LPC2294HBD144
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface
NXP
LPC2294HBD144/00
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface
NXP
LPC2294HBD144/01
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface
NXP
LPC2294HBD144/01,5
LPC2292/2294 - 16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface QFP 144-Pin
NXP
LPC2294JBD144
16/32-bit ARM microcontrollers 256 kB ISP/IAP Flash with CAN, 10-bit ADC and external memory interface
NXP
©2020 ICPDF网 联系我们和版权申明